JPH03133157A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03133157A JPH03133157A JP27285489A JP27285489A JPH03133157A JP H03133157 A JPH03133157 A JP H03133157A JP 27285489 A JP27285489 A JP 27285489A JP 27285489 A JP27285489 A JP 27285489A JP H03133157 A JPH03133157 A JP H03133157A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- thin film
- insulating film
- resistance element
- film resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010408 film Substances 0.000 claims abstract description 72
- 239000010409 thin film Substances 0.000 claims abstract description 49
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 10
- 238000004544 sputter deposition Methods 0.000 abstract description 9
- 239000006185 dispersion Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 64
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 8
- -1 argon ions Chemical class 0.000 description 8
- 229910000599 Cr alloy Inorganic materials 0.000 description 5
- 239000007864 aqueous solution Substances 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910001120 nichrome Inorganic materials 0.000 description 4
- 229910017604 nitric acid Inorganic materials 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- 229910000676 Si alloy Inorganic materials 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 229910052801 chlorine Inorganic materials 0.000 description 3
- 239000000788 chromium alloy Substances 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- DYRBFMPPJATHRF-UHFFFAOYSA-N chromium silicon Chemical compound [Si].[Cr] DYRBFMPPJATHRF-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は薄膜抵抗素子を用いた半導体装置の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device using a thin film resistive element.
従来の技術
一般に、薄膜抵抗素子は高精度な集積回路に用いられ、
例えば、アナログ−ディジタルやディジタル−アナログ
変換器で基準電流を定めるリファレンス抵抗や各ビット
電流の重みづけに対応するラダー抵抗としたり、あるい
はベアのトランジスタの特性バランスを調整する抵抗と
して利用する。Conventional technology Generally, thin film resistive elements are used in high-precision integrated circuits.
For example, it can be used as a reference resistor for determining the reference current in an analog-to-digital or digital-to-analog converter, a ladder resistor for weighting each bit current, or as a resistor for adjusting the characteristic balance of bare transistors.
以下に従来の薄膜抵抗素子を用いた半導体装置を具体例
について、第２図を参照して説明する。A specific example of a semiconductor device using a conventional thin film resistance element will be described below with reference to FIG.
第２図は従来の薄膜抵抗素子を用いた半導体装置の断面
図である（参考文献、 １９８３年Ｖｏｌ：５Ｃ−１８
゜嵐＝６ アイイーイーイー インターナショナルソリ
ッド−ステート サーキット コンファレンス（ＩＥＥ
Ｅ Ｉ ｎｔｅｒｎａｔｉｏｎａｌ ５ｏｌｉｄ−ｓｔ
ａｔｅ Ｃ１ｒｃｕｉｔＣｏｎ４ｅｒｅｎｃｅ ） ）
。FIG. 2 is a cross-sectional view of a semiconductor device using a conventional thin film resistance element (Reference, 1983 Vol. 5C-18).
゜Arashi=6 IEE International Solid-State Circuit Conference (IEE
E international 5 solid-st
ateC1rcuitCon4erence ) )
.
この場合、シリコンなどの半導体基板１の内部に形成さ
れたＮ型やＰ型の導電性を有す拡散領域２を設け、その
表面に、熱酸化またはＣＶＤ法による表面絶縁膜３を被
覆し、この表面絶縁膜３上に、ニクロム・クロム系合金
やクロム・シリコン系合金などの薄膜抵抗素子１６を形
成し、この薄膜抵抗素子１６の両端からは電気的に接続
するため、アルミニウムなどを用いた配線層２４が設け
られる。この配線層２４は通常の７オトリソ法によりパ
ターニングされるが、薄膜抵抗素子１６の膜厚が１００
Ａ〜３００八であるため、薄膜抵抗素子１６との選択比
が大きいリン酸と硝酸などを調合した水溶、液でエツチ
ングされる。In this case, a diffusion region 2 having N-type or P-type conductivity is formed inside a semiconductor substrate 1 made of silicon or the like, and its surface is covered with a surface insulating film 3 formed by thermal oxidation or CVD. A thin film resistance element 16 made of a nichrome/chromium alloy or a chromium/silicon alloy is formed on the surface insulating film 3, and aluminum or the like is used to electrically connect both ends of the thin film resistance element 16. A wiring layer 24 is provided. This wiring layer 24 is patterned by the usual 7-otolithography method, but the film thickness of the thin film resistive element 16 is 100 mm.
Since it is A~3008, it is etched with an aqueous solution prepared by mixing phosphoric acid and nitric acid, etc., which has a high selectivity with respect to the thin film resistive element 16.
最後に、外部の汚染から保護するため、これらの素子表
面をＣＶＤ法またはスパッタ法により酸化膜や窒化膜な
どから成る最終保護膜３１で覆っている。Finally, in order to protect them from external contamination, the surfaces of these elements are covered with a final protective film 31 made of an oxide film, a nitride film, or the like by CVD or sputtering.
発明が解決しようとする課題
しかしながら上記従来の構造では、半導体基板に形成さ
れた素子を接続する配線層が単層配線であり、パターニ
ングにもリン酸と硝酸などを調合した水溶液でエツチン
グしているので、チップ内で配線の占める割合が大きく
、高集積な回路を実現しようとすると、素子占有面積が
太き（なり、歩留りの低下やコスト高になるし、微細な
配線はエツチングのばらつきで断線不良が発生するとい
う欠点を有している。Problems to be Solved by the Invention However, in the conventional structure described above, the wiring layer connecting the elements formed on the semiconductor substrate is a single layer wiring, and patterning is also performed by etching with an aqueous solution containing phosphoric acid and nitric acid. Therefore, when trying to realize a highly integrated circuit in which wiring occupies a large proportion of the chip, the area occupied by the element becomes large (resulting in lower yields and higher costs), and fine wiring is prone to disconnection due to uneven etching. It has the disadvantage that defects occur.
これらの欠点は多層配線技術を用いれば解決されるが、
高精度な薄膜抵抗素子を形成するには別の問題が生じ、
製品化の実現を困難にしている。These drawbacks can be solved by using multilayer wiring technology, but
Another problem arises when forming highly accurate thin film resistive elements.
This makes commercialization difficult.
例えば、この多層配線技術は第１配線層を設けた後に、
中間絶縁膜で第１配線層を被覆し、この中間絶縁膜上に
薄膜抵抗素子を形成し、第１配線層とコンタクトをとる
ため中間絶縁膜に開口部を選択的に設け、第１配線層や
薄膜抵抗素子を電気的に接続する第２配線層を形成する
という方法がある。ところがこの方法は、第１配線層の
材料にアルミニウムを用いると表面にアルミナが生じ、
このアルミナを除去しなければ第１配線層と第２配線層
の接触抵抗が大きくなる。そのため、第２配線層を蒸着
する前に、第１配線層の表面に生じたアルミナをアルゴ
ンイオンのスパッタ法で除去する工程を含める。この除
去の工程により、薄膜抵抗の材料であるニクロム・クロ
ム系合金やクロム・シリコン系合金はアルミナに比べて
２〜１０倍以上の膜減りを生じ、高精度で安定した薄膜
抵抗が実現できない。For example, in this multilayer wiring technology, after providing the first wiring layer,
A first wiring layer is covered with an intermediate insulating film, a thin film resistance element is formed on the intermediate insulating film, an opening is selectively provided in the intermediate insulating film to make contact with the first wiring layer, and the first wiring layer is covered with an intermediate insulating film. There is also a method of forming a second wiring layer that electrically connects thin film resistance elements. However, in this method, when aluminum is used as the material for the first wiring layer, alumina is generated on the surface.
If this alumina is not removed, the contact resistance between the first wiring layer and the second wiring layer will increase. Therefore, before depositing the second wiring layer, a step of removing alumina formed on the surface of the first wiring layer by sputtering with argon ions is included. Due to this removal process, the thickness of the nichrome-chromium alloy or chromium-silicon alloy, which is the material of the thin film resistor, is reduced 2 to 10 times more than that of alumina, making it impossible to realize a highly accurate and stable thin film resistor.
本発明は上記従来の問題点を解決するもので、薄膜抵抗
素子を用いた半導体装置の製造方法を提供することを目
的とする。The present invention solves the above-mentioned conventional problems, and aims to provide a method for manufacturing a semiconductor device using a thin film resistive element.
課題を解決するための手段
この目的を達成するために本発明は、拡散領域を備えた
半導体基板上に薄膜抵抗素子を含む半導体装置を製造す
るにあたり、前記拡散領域の電極なる第１配線層を形成
し、前記第１配線層上に下層絶縁膜を被覆し、前記下層
絶縁膜上に薄膜抵抗材料を蒸着゛し、選択的に除去して
前記薄膜抵抗素子を形成した後に、前記薄膜抵抗素子の
両端に電極となる第２配線層を形成して、前記第２配線
層上に上層絶縁膜を被覆し、前記第１配線層上に被覆さ
れた前記下層絶縁膜と前記上層絶縁膜および、前記第２
配線層上の前記上層絶縁膜を選択的に除去し、開口部を
形成する工程と、前記上層絶縁膜の表面で前記開口部よ
り少なくとも前記第１配線層と前記第２配線層の一部に
接続する第３配線層を設ける工程を備えた構造を有して
いる。Means for Solving the Problems To achieve this object, the present invention provides a method for manufacturing a semiconductor device including a thin film resistive element on a semiconductor substrate having a diffusion region, by forming a first wiring layer serving as an electrode in the diffusion region. a lower insulating film is formed on the first wiring layer, a thin film resistive material is deposited on the lower insulating film and selectively removed to form the thin film resistive element; a second wiring layer serving as an electrode is formed on both ends of the wiring layer, an upper insulating film is coated on the second wiring layer, the lower insulating film and the upper insulating film are coated on the first wiring layer, and Said second
selectively removing the upper insulating film on the wiring layer to form an opening; and at least part of the first wiring layer and the second wiring layer from the opening on the surface of the upper insulating film. It has a structure including a step of providing a third wiring layer for connection.
作用
この構造により、第１配線層のエツチングは薄膜抵抗を
形成する前に処理され、第３配線層のエツチングでは薄
膜抵抗素子が上層絶縁膜で保護されており、薄膜抵抗素
子の膜減りは発生しない。Effect: With this structure, the first wiring layer is etched before forming the thin film resistor, and when the third wiring layer is etched, the thin film resistor element is protected by the upper insulating film, so that film thinning of the thin film resistor element occurs. do not.
そのため、薄膜抵抗素子を除（集積回路を構成する各素
子を電気的に接続するに第１配線層と第３配線層を用い
ることができ、それらの配線のエツチングは、一般によ
（用いられるｃｃｃ４やＢＣ（！３などの塩素イオンが
使用できる。従って、微細な配線パターンも寸法が変化
することな（実現でき、素子占有面積が大きくならない
。Therefore, except for thin film resistive elements, a first wiring layer and a third wiring layer can be used to electrically connect each element constituting an integrated circuit. Chlorine ions such as and BC (!3) can be used. Therefore, even fine wiring patterns can be realized without changing dimensions, and the area occupied by the device does not increase.
さらに、本研明は多層配線技術を用いているにもかかわ
らず、第１配線層と第２配線層の表面に形成されるアル
ミナなどの酸化物をスパッタ法で除去しても、薄膜抵抗
素子が上層絶縁膜で被覆されているので、損傷を受けず
膜減りのない高精度で安定した特性を有する。Furthermore, although this research uses multilayer wiring technology, even if oxides such as alumina formed on the surfaces of the first and second wiring layers are removed by sputtering, the thin film resistor Since it is covered with an upper layer insulating film, it has high precision and stable characteristics without being damaged and without film loss.
実施例
以下、本発明の一実施例について、図面を参照しながら
説明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図ａ−ｆは本発明の一実施例を製造工程順に示した
断面図である。同図ａにおいては、シリコンなどの半導
体基板１の内部にＮ型やＰ型の導電性を有す拡散領域２
を設け、熱酸化やＣＶＤ法により表面絶縁膜３として０
．３〜１．０μｍの膜厚の酸化膜を形成し、拡散領域２
の電極を設けるため、表面絶縁膜３を選択的に除去して
開口部を形成し、さらに、全面に０．６〜２．０μｍの
膜厚でアルミニウムなどの電極材料を被覆し、塩素イオ
ンを用いたプラズマエツチングにより選択的にエツチン
グして第１配線層４を形成する。また、同図すにおいて
は、第１配線層４を以降に形成する配線層と絶縁するた
め、ＣＶＤ法で０．３〜１．０μｍの膜厚を有す窒化膜
を用いて下層絶縁膜５を形成した後に、スパッタ法によ
りニクロム・クロム（組成比８０ ： ２０）を１００
〜３００Ａの膜厚で蒸着し、水酸化カリウムなどのアル
カリ性水溶液で選択的に除去し、薄膜抵抗素子６を形成
する。次に同図Ｃにおいては、薄膜抵抗素子６の表面に
０．２〜０．８μｍの膜厚を有すアルミニウムなどの電
極材料を被覆し、ニクロム・クロムとの選択比が大きい
リン酸と硝酸などを調合した水溶液で選択的にエツチン
グし、薄膜抵抗の電極として作用する第２配線層７を形
成する。さらに、同図ｄにおいては、ＣＶＤ法で０ 、
２〜０ 、８ ａ ｍの膜厚の酸化膜を用いて上層絶縁
膜８を形成し、第１配線層および第２配線層を取出すた
め、下層絶縁膜５と上層絶縁膜８を選択的にエツチング
して開口部９を設ける。次いで、同図ｅにおいて、１０
−５〜１０−フＴｏｒｒ状態で開口部９を介してアルゴ
ンイオンを第１配線層４と第２配線層７に照射し、同じ
線層表面に生じたアルミナなどの異物を除去した後に、
０．８〜２．０μｍの膜厚なる電極材料を被覆し、プラ
ズマエツチングあるいはリン酸や硝酸などの調合水溶液
を用いて選択的にエツチングし、第３配線層１０を形成
する。最後に、同図ｆでは外部からの汚染を防ぐため、
ＣＶＤ法やスパッタ法により０．３〜１．０μｍの厚み
で酸化膜や窒化膜を用いて、最終保護膜１１を形成して
いる。FIGS. 1a to 1f are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps. In FIG.
0 as the surface insulating film 3 by thermal oxidation or CVD method.
．． An oxide film with a thickness of 3 to 1.0 μm is formed, and the diffusion region 2 is
In order to provide an electrode, the surface insulating film 3 is selectively removed to form an opening, and the entire surface is coated with an electrode material such as aluminum with a film thickness of 0.6 to 2.0 μm, and chlorine ions are removed. The first wiring layer 4 is formed by selectively etching using plasma etching. In addition, in the same figure, in order to insulate the first wiring layer 4 from wiring layers to be formed thereafter, a nitride film having a thickness of 0.3 to 1.0 μm is used by the CVD method to form a lower insulating film 5. After forming, 100% nichrome chromium (composition ratio 80:20) was added by sputtering.
The film is deposited to a thickness of ~300 A, and selectively removed with an alkaline aqueous solution such as potassium hydroxide to form the thin film resistance element 6. Next, in Figure C, the surface of the thin film resistance element 6 is coated with an electrode material such as aluminum having a film thickness of 0.2 to 0.8 μm, and phosphoric acid and nitric acid, which have a high selectivity with nichrome and chromium, are coated. A second wiring layer 7 is formed by selectively etching with an aqueous solution containing the following. Furthermore, in Figure d, 0,
The upper insulating film 8 is formed using an oxide film with a thickness of 2 to 0.8 am, and the lower insulating film 5 and the upper insulating film 8 are selectively removed in order to take out the first wiring layer and the second wiring layer. An opening 9 is provided by etching. Next, in e of the same figure, 10
-5 to 10- After irradiating the first wiring layer 4 and the second wiring layer 7 with argon ions through the opening 9 in a Torr state to remove foreign substances such as alumina generated on the surface of the same wiring layer,
The third wiring layer 10 is formed by coating the electrode material with a film thickness of 0.8 to 2.0 μm and selectively etching it using plasma etching or a mixed aqueous solution of phosphoric acid, nitric acid, or the like. Finally, in Figure f, to prevent contamination from the outside,
The final protective film 11 is formed using an oxide film or a nitride film with a thickness of 0.3 to 1.0 μm by a CVD method or a sputtering method.
本発明では、半導体基板の内部に形成した拡散領域と説
明したが、これはアナログ・ディジタル変換器や基準電
源回路などを構成するＭＯＳトランジスタ、バイポーラ
トランジスタや抵抗などに相当するものである。Although the present invention has been described as a diffusion region formed inside a semiconductor substrate, this corresponds to a MOS transistor, a bipolar transistor, a resistor, etc. that constitute an analog-to-digital converter, a reference power supply circuit, and the like.
集積回路を構成する素子を電気的に接続するのは、第１
配線層と第３配線層であり、第１配線層は薄膜抵抗素子
を形成する前にエツチングされ、第３配線層のエツチン
グでは上層絶縁膜で薄膜抵抗が保護されており、薄膜抵
抗素子の膜減りがない。The first step is to electrically connect the elements that make up the integrated circuit.
The first wiring layer is etched before forming the thin film resistance element, and in the etching of the third wiring layer, the thin film resistance is protected by the upper insulating film, and the film of the thin film resistance element is etched. There is no decrease.
また、第１配線層と第２配線層を第３配線層に電気的に
接続する場合、第１配線層と第２配線層の表面に形成さ
れるアルミナなどの異物をスパッタ法でアルゴンイオン
を照射し除去しても、薄膜抵抗素子は上層絶縁膜で被覆
されており損傷を受けることな（膜減りも発生しない。In addition, when electrically connecting the first wiring layer and the second wiring layer to the third wiring layer, foreign substances such as alumina formed on the surfaces of the first wiring layer and the second wiring layer are removed using argon ions by sputtering. Even if it is removed by irradiation, the thin film resistance element is covered with the upper insulating film and will not be damaged (no film thinning will occur).
なお、薄膜抵抗素子６はシート抵抗が１００〜５００Ω
／口のニクロム・クロム系合金やクロム・シリコン系合
金を材料としたが、モリブデン。Note that the sheet resistance of the thin film resistance element 6 is 100 to 500Ω.
/ The material used is nichrome/chromium alloy or chromium/silicon alloy, but molybdenum is used.
タングステンやチタンなどの金属を用いた比較的、シー
ト抵抗が低い薄膜抵抗素子を形成する場合にも本発明は
有効である。さらに、本発明では第１配線層４と第２配
線層７上に設ける開口部９を同時に形成しているが、各
開口部の絶縁膜の厚みが異なるため、工程数は増加する
が別々に開口部を形成すれば、その寸法バラツキは抑え
られる。また、下層絶縁膜５．上層絶縁膜８や最終保護
膜１１はＣＶＤ法やスパッタ法で形成するとしたが、け
い素化合物を有機溶剤に溶解した溶液を用いる塗布法で
形成してもよいことは言うまでもない。The present invention is also effective when forming a thin film resistance element using a metal such as tungsten or titanium and having a relatively low sheet resistance. Furthermore, in the present invention, the openings 9 provided on the first wiring layer 4 and the second wiring layer 7 are formed simultaneously, but since the thickness of the insulating film of each opening is different, the number of steps increases, but the openings 9 are formed separately. By forming the opening, the dimensional variation can be suppressed. Further, the lower layer insulating film 5. Although the upper insulating film 8 and the final protective film 11 are formed by the CVD method or the sputtering method, it goes without saying that they may be formed by a coating method using a solution of a silicon compound dissolved in an organic solvent.
発明の効果
本発明は、拡散領域の電極になる第１配線層を形成し下
層絶縁膜を被覆してこの絶縁膜上に薄膜抵抗素子を形成
しており、また、薄膜抵抗素子の両端に電極となる第２
配線層を形成した後に、上層絶縁膜を被覆しており、第
３配線層のエツチングでは薄膜抵抗素子が上層絶縁膜に
保護され、第１配線層と第３配線層のエツチングに薄膜
抵抗素子は全く膜減りしないため、両前線層の形成には
薄膜抵抗材料と選択比が低いｃｃｃ４やＢＣｅ３などの
塩素系イオンを用いたプラズマエツチング法を利用でき
、エツチングばらつきの少ない断線も生じない微細な高
密度配線が実現でき、高集積な回路でも素子占有面積が
大きくならず、歩留りが向上して低いコストで生産が可
能となる。さらに、第３配線層との電気的接続を妨げる
第１配線層と第２配線層の表面に形成されるアルミナな
どの酸化物をアルゴンイオンを用いたスパッタ法で除去
しても、その損傷を受けることな（膜減りもおこらない
高精度で安定した特性を有す。しかも、薄膜抵抗素子の
表面は、上層絶縁膜として酸化膜および最終保護膜とし
て窒化膜で被覆されており、より高精度な薄膜抵抗素子
を得るため、レーザートリミングで抵抗値を調整しても
、高精度な抵抗を保証する高信頼性を実現できる。Effects of the Invention The present invention forms a first wiring layer that becomes an electrode in a diffusion region, covers a lower insulating film, and forms a thin film resistive element on this insulating film, and also provides electrodes at both ends of the thin film resistive element. The second
After forming the wiring layer, the upper insulating film is covered, and the thin film resistive element is protected by the upper insulating film when etching the third wiring layer, and the thin film resistive element is protected by the upper insulating film when etching the first wiring layer and the third wiring layer. Because there is no film loss at all, plasma etching using a thin film resistor material and chlorine ions such as CCC4 or BCe3, which have a low selectivity, can be used to form both front layers. Density wiring can be realized, the area occupied by elements does not become large even in highly integrated circuits, yields are improved, and production can be performed at low cost. Furthermore, even if oxides such as alumina formed on the surfaces of the first wiring layer and the second wiring layer that prevent electrical connection with the third wiring layer are removed by sputtering using argon ions, the damage will not occur. It has high precision and stable characteristics that do not cause damage (no film loss occurs).Moreover, the surface of the thin film resistor element is covered with an oxide film as the upper layer insulating film and a nitride film as the final protective film, making it possible to achieve even higher precision. Even if the resistance value is adjusted by laser trimming to obtain a thin-film resistive element, it is possible to achieve high reliability by guaranteeing highly accurate resistance.
【図面の簡単な説明】
第１図ａ−ｆは本発明の一実施例を製造工程順に示した
断面図、第２図は従来の構造の薄膜抵抗素子を用いた半
導体装置の断面図である。
１・・・・・・半導体基板、２・・・・・・拡散領域、
３・・・・・・表面絶縁膜、４・・・・・・第１配線層
、５・・・・・・下層絶縁膜、６・・・・・・薄膜抵抗
素子、７・・・・・・第２配線層、８・・・・・・上層
絶縁膜、９・・・・・・開口部、１０・・・・・・第３
配線層、１１・・・・・・最終保護膜。[Brief Description of the Drawings] Figures 1a-f are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps, and Figure 2 is a cross-sectional view of a semiconductor device using a thin film resistor element with a conventional structure. . 1... Semiconductor substrate, 2... Diffusion region,
3... Surface insulating film, 4... First wiring layer, 5... Lower layer insulating film, 6... Thin film resistance element, 7... ...Second wiring layer, 8...Upper layer insulating film, 9...Opening, 10...Third
Wiring layer, 11...Final protective film.
Claims (1)
半導体装置を製造するにあたり、前記拡散領域の電極に
なる第１配線層を形成し、前記第１配線層上に下層絶縁
膜を被覆し、前記下層絶縁膜上に薄膜抵抗材料を蒸着し
、選択的に除去して前記薄膜抵抗素子を形成した後、前
記薄膜抵抗素子の両端に電極となる第２配線層を形成し
て、前記第２配線層上に上層絶縁膜を被覆し、前記第１
配線層上に被覆された前記下層絶縁膜と前記上層絶縁膜
および、前記第２配線上の前記上層絶縁膜を選択的に除
去し、開口部を形成する工程と、前記上層絶縁膜の表面
で前記開口部より少なくとも前記第１配線層と前記第２
配線層の一部に接続する第３配線層を設ける工程を備え
たことを特徴とする半導体装置の製造方法。In manufacturing a semiconductor device including a thin film resistance element on a semiconductor substrate having a diffusion region, forming a first wiring layer that becomes an electrode of the diffusion region, covering the first wiring layer with a lower insulating film, After depositing a thin film resistance material on the lower insulating film and selectively removing it to form the thin film resistance element, a second wiring layer serving as an electrode is formed on both ends of the thin film resistance element, and the second An upper insulating film is coated on the wiring layer, and the first
selectively removing the lower insulating film and the upper insulating film coated on the wiring layer and the upper insulating film on the second wiring to form an opening; At least the first wiring layer and the second wiring layer are separated from the opening.
A method for manufacturing a semiconductor device, comprising the step of providing a third wiring layer connected to a part of the wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27285489A JPH03133157A (en) | 1989-10-19 | 1989-10-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27285489A JPH03133157A (en) | 1989-10-19 | 1989-10-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03133157A true JPH03133157A (en) | 1991-06-06 |
Family
ID=17519700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27285489A Pending JPH03133157A (en) | 1989-10-19 | 1989-10-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03133157A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05175428A (en) * | 1991-12-26 | 1993-07-13 | Nippon Precision Circuits Kk | Integrated circuit device |
| JP2017079254A (en) * | 2015-10-20 | 2017-04-27 | 新日本無線株式会社 | Semiconductor device |
-
1989
- 1989-10-19 JP JP27285489A patent/JPH03133157A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05175428A (en) * | 1991-12-26 | 1993-07-13 | Nippon Precision Circuits Kk | Integrated circuit device |
| JP2017079254A (en) * | 2015-10-20 | 2017-04-27 | 新日本無線株式会社 | Semiconductor device |
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