JPS6119162A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To bore a contact hole through one-time punching without lowering a function by a method wherein a polycrystalline Si region is formed selectively, PSG in low concentration is applied, PSG in low concentration is applied onto the PSG in low concentration and flattened, an opening is bored to an insulating film in a fuse section through etching, PSG in low concentration is applied and the contact hole is bored through etching. CONSTITUTION:A thick field oxide film 2 is formed onto an Si semiconductor substrate, and polycrystalline Si 3a for a fuse and polycrystalline Si 3b for a wiring are shaped selectively onto the field oxide film 2. A diffusion layer 4 having a conduction type reverse to the substrate 1 is formed, and an Si oxide film 5 is shaped onto the surface of the diffusion layer 4 through thermal oxidation. PSG6 in low concentration is applied, and PSG in low concentration is applied 7 onto the PSG6, flattened and sintered. The insulating film in the fusion cutting section of Si used as a fuse is etched to form an opening 10, and the surface of polycrystalline Si3a is exposed. A PSG film 8 in low concentration is applied onto the whole surface. Contact holes to the diffusion layer 4 and polycrystalline Si3b are bored through etching at a time while penetrating the inter- layer insulating films 5-8, and a wiring is performed 9 selectively.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor integrated circuit device.

In particular, the present invention relates to a method of manufacturing a semiconductor integrated circuit device including a variable resistance circuit using polycrystalline silicon as a fuse.

[Prior Art] Conventionally, in semiconductor integrated circuit devices with a built-in reference voltage generation circuit in A/D, D/A conversion circuits, etc., one method for realizing a highly accurate reference voltage is to use multiple resistors. Variable resistors are used that are connected in series and have a fuse placed in parallel with each resistor to short-circuit each resistor. In other words, the total resistance value is controlled by selectively cutting the fuses,
In a silicon gate/MIS type semiconductor integrated circuit that can obtain a voltage within a desired range, polycrystalline silicon, which is used as a fuse, gate electrode, and wiring, is used to realize the variable resistance circuit. be done. Polycrystalline silicon used as a fuse is blown by passing an excessive current through thermal breakdown, but the protective insulating film may be significantly damaged due to volume changes and thermal shock. This part becomes a source of contamination and affects the internal active region, reducing the long-term reliability of the device. In the prior art, polycrystalline silicon is coated with a thermal oxide film and then coated with a high concentration phosphorus glass film (hereinafter referred to as high concentration PEG).
If the above-mentioned polycrystalline silicon is used as a fuse that has been flattened with a thermal oxidation film, the critical current for fusing will be high, and the upper insulating film will be severely damaged after fusing. Therefore, as a countermeasure, first remove the thermal oxide film and high-concentration PSG that cover the polycrystalline silicon in the part that will blow as a fuse, and then remove the low-concentration PSG.
If the coating is protected by EG, the polycrystalline silicon can be fused with a low current without damaging the insulating film due to the weak coating.

The formation of the diffusion layer of the integrated circuit device and the contact hole in the polycrystalline silicon by the above manufacturing method is carried out at the same time in the process of etching the upper thermal oxide film of the polycrystalline silicon, which is usually used as a fuse, and the high concentration PEG, which has a high etching rate. A first contact etching is performed, and then a second contact etching is performed on the deposited low concentration PEG with the same size or a slightly smaller contact size, and the shape of the contact part is made into two stages. It is necessary to prevent disconnection of the contact portion of the aluminum wiring.

That is, a two-degree contact etching method has been used.

In recent years, the miniaturization of integrated circuit devices has progressed markedly, and in order to form contact holes as small as 2 microns square, the double contact method requires the alignment of the first contact hole and the second contact hole. High precision is required, and the hole area ratio is a problem in mass production.

In addition, the high concentration P8G used for flattening the polycrystalline silicon layer has a problem in terms of moisture resistance. Conventionally, a 1 to 2 micron thick low concentration P8G was applied on the surface concentration PSG to improve moisture resistance. [Objective of the Invention] The object of the present invention is to provide an excellent semiconductor integrated circuit with a fuse in a semiconductor integrated circuit using polycrystalline silicon as a fuse. The purpose of the present invention is to provide a method for manufacturing a circuit device.

[Structure of the invention]

The method of manufacturing a semiconductor integrated circuit device of the present invention is a method of manufacturing a semiconductor integrated circuit device using polycrystalline silicon of one conductivity type as a fuse, in which the polycrystalline silicon region is selectively formed and then a first low concentration phosphor layer is formed. a process of depositing a glass film, a process of depositing a low concentration phosphorus glass film by a coating method on the first low concentration phosphorus glass film to flatten the surface, and a fused portion of polycrystalline silicon used as a fuse. A step of etching only the upper insulating film to make the surface of the polycrystalline silicon unparalleled, a step of depositing a second low concentration phosphorus glass film, and a contact hole to the polycrystalline silicon, substrate, diffusion layer, etc. The process includes the step of etching and forming holes.

[Effect]

In the semiconductor integrated circuit device formed according to the present invention, unlike the conventional example, the thermal oxide film is removed from the surface of the fuse blown part and a low concentration PSG film is deposited on it, so that it is protected from thermal breakdown of the fuse. The membrane is not significantly damaged. The contact opening has a three-layer structure consisting of a first low concentration PSG film, a low concentration P8G film formed by a coating method, and a second low concentration PSG film. The etching rate of the PSG film was changed to the second low concentration PSG.
Since the etching speed can be made equal to or slower than the etching speed of the film, the contact hole generally has a beveled shape, and disconnection of the aluminum wiring at the contact area does not occur.
- Since it is a double contact etching method, it is possible to form contact holes as small as 2 microns square. Furthermore, since the insulating films are all low-concentration PEG films, it goes without saying that excellent moisture resistance can be obtained.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1 fal to 1 fdl are cross-sectional views shown in order of steps to explain an embodiment of the present invention.

First, as shown in FIG. 1fa), a thick field oxide film 2 is formed on the surface of a silicon semiconductor substrate 10, and polycrystalline silicon 3a for fuses of one conductivity type and polycrystalline silicon 3b for interconnections of one conductivity type are selectively deposited on the top surface of the thick field oxide film 2. to form. Furthermore, a diffusion layer 4 having a conductivity type opposite to that of the silicon semiconductor substrate 1 is formed, and the surface of the substrate and the polycrystalline silicon layer are thermally oxidized to form a silicon oxide film 5 that covers the surface.

Next, as shown in FIG. 1(b), a first low concentration PSG film 6 with a thickness of about 0.5 microns is formed as an interlayer insulating film.
Next, in order to flatten the surface, a low concentration PSG film 7 is deposited by a coating method, and this is sintered by thermal oxidation or heat treatment, so that the first low concentration PSG 6 and the t-hill are homogenized.

Next, as shown in FIG. 1C, only the insulating film on the blown portion of the polycrystalline silicon 3 used as a fuse is etched to form an opening 10 and expose the polycrystalline silicon surface. Next, a second low concentration PEG film 8 is coated on the entire surface with a coating of about O, S.
It adheres to the order of microns.

Next, as shown in FIG. 1(d), contact holes for the diffusion layer 4 and the polycrystalline silicon 3b for wiring are formed in one go through the interlayer insulating films 5, 6, 7.8. Machining, drilling, and drilling. Then, by selectively wiring 9 using aluminum or the like as a wiring metal, a semiconductor integrated circuit device according to an embodiment of the present invention is completed.

In the above example, polycrystalline silicon was flattened using the first low-concentration PSG and a silicon oxide film formed by coating, but it is possible to replace this with high-temperature low-concentration PSG growth, which has a high level difference smoothing effect. It goes without saying that it can be done.

〔Effect of the invention〕

As explained above, according to the present invention, fine contact holes can be formed by punching without impairing the function of polycrystalline silicon as pews, and since low concentration PSG is used, moisture resistance is achieved. 0 that can manufacture excellent semiconductor integrated circuit devices.

[Brief explanation of drawings]

1 (a1 to d) are cross-sectional views shown in the order of steps to explain one embodiment of the present invention. 1...Silicon semiconductor substrate, 2...Field oxidation Film, 3a...Polycrystalline silicon for fuse, 3b...Polycrystalline silicon for wiring, 4.
... Diffusion layer, 5 ... Thin thermal oxide film, 6.
...First low concentration PSG film, 7...Low concentration PEG film by coating method, 8...Second low concentration PSG film, 9... Aluminum wiring, 10...
...Opening of polycrystalline silicon for fuse.

Claims (3)

[Claims] (1) In a method of manufacturing a semiconductor integrated circuit device using polycrystalline silicon of one conductivity type as a fuse, the step of selectively forming the polycrystalline silicon region and then depositing a first low concentration phosphorus glass film; A process of depositing a low concentration phosphorus glass film by a coating method on the first low concentration phosphorus glass film and flattening the surface, and etching holes only in the insulating film on the fused portion of polycrystalline silicon used as a fuse. the step of exposing the surface of the polycrystalline silicon; the step of depositing a second low concentration phosphorus glass film; and the step of etching a contact hole to the polycrystalline silicon, the substrate, the diffusion layer, etc. A method for manufacturing a semiconductor integrated circuit device, characterized by: (2) Claim No. 1 characterized in that the first and second low concentration phosphorus glass films and the low concentration phosphorus glass film deposited by the coating method have a phosphorus concentration of approximately 3 to 5 mol%. ) The method for manufacturing a semiconductor integrated circuit device according to item 2. (3) The first low-concentration phosphorus glass film and the etching rate of the low-concentration phosphorus glass film by the coating method are equal to or slightly slower than the etching rate of the second low-concentration phosphorus glass. A method for manufacturing a semiconductor integrated circuit device according to item (1).