JPS59148340A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS59148340A JPS59148340A JP2228683A JP2228683A JPS59148340A JP S59148340 A JPS59148340 A JP S59148340A JP 2228683 A JP2228683 A JP 2228683A JP 2228683 A JP2228683 A JP 2228683A JP S59148340 A JPS59148340 A JP S59148340A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- electrode
- layer
- window
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Abstract
Description
【発明の詳細な説明】
(al 発明の技術分野
本発明は集積回路基板の配線バターニングにおいて電極
窓に伝導性金属層を被膜形成させ、配線パターン巾を微
細化し高集積化に有効な半導体装置及びその製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device which is effective for high integration by forming a conductive metal layer on an electrode window in wiring patterning of an integrated circuit board to miniaturize the wiring pattern width. and its manufacturing method.
(b) 技術の背景
集積回路基板の回路構成に用いられる一般的な配線材料
はアルミニウム(A t)またはシリコン(St)とア
ルミニウムの合金であシ、スパッタ法等により形成され
るアルミニウム膜は抵抗値が小さく、。(b) Background of the technology The general wiring material used in the circuit configuration of integrated circuit boards is aluminum (At) or an alloy of silicon (St) and aluminum, and aluminum films formed by sputtering etc. are used as resistors. The value is small.
シリコン酸化膜等に対して接着性及び加工性に優れてい
る。反面耐湿性に劣シ、マイグレーション(elect
romigration)を起し易く、シリコンと共晶
点を持つため、アルミニウム膜とシリコ/酸化膜とが接
する接触面に共晶合金を作り、シリコン層に深いピット
を生ずる。一方ソース、ドレイン領域の電極窓に施すア
ルミニウム又はアルミニウム合金膜等の配線処理は微細
な配線パターンを描画したマスクを基板に重ね合せて露
光によりバターニングするが位置合せにかなりの精度を
必要とし、上記領域の電極窓よシずれることがあるため
、このずれ量を考慮してデバイス設計を行なう必要があ
る。Excellent adhesion and processability to silicon oxide films, etc. On the other hand, it has poor moisture resistance and migration (elect
Because it has a eutectic point with silicon, a eutectic alloy is formed at the contact surface where the aluminum film and the silicon/oxide film are in contact, causing deep pits in the silicon layer. On the other hand, wiring processing for aluminum or aluminum alloy films applied to the electrode windows in the source and drain regions involves placing a mask with a fine wiring pattern on the substrate and patterning it by exposing it to light, but this requires considerable precision in positioning. Since the electrode window in the above region may shift, it is necessary to take this amount of shift into account when designing the device.
(c) 従来技術と問題点
第1図、第2図の各(a) 、 (b1図はMO8型半
導体基板の従来例を示す構成図であり、(a)は断面図
、(b)は配線パターンと電極を示す平面図である。(c) Prior art and problems Figures (a) and (b1) in Figures 1 and 2 are block diagrams showing a conventional example of an MO8 type semiconductor substrate, where (a) is a cross-sectional view and (b) is a cross-sectional view. FIG. 3 is a plan view showing a wiring pattern and electrodes.
集積回路基板に形成される配線パターンは例えばMOS
デバイスに於ては第1図及び第2図に示すように多結晶
シリコン(Poly−8t)でなる電極1を拡散マスク
としてイオン打込によシソース2゜ドレイン3拡散を行
ない打込まれる不純物はn型の場合りん(P)或いはひ
素(A8)が拡散されてn領域となる。りんシリケート
ガラス!4(PSG)で被膜して電極窓5を形成し、メ
ルト処理する。ソース、ドレイン2,3領域の電極窓5
にアルミ電極6及び配線パターン7を蒸着する。電極窓
は1μ程度の微細長であり、配線パターン7幅も1μ〜
2μでありパターン転写時マスク位置合せは厳しい精度
が要求され、第1図に示す電極6及び配線パターン7が
理想的であるがパターン幅が大きくなり基板の集積度が
制約を受けることになシしかも上述したようにマスク位
置合せが困難である。The wiring pattern formed on the integrated circuit board is, for example, a MOS
In the device, source 2° and drain 3 diffusion is performed by ion implantation using an electrode 1 made of polycrystalline silicon (Poly-8T) as a diffusion mask, as shown in Figures 1 and 2. In the case of n-type, phosphorus (P) or arsenic (A8) is diffused to form an n region. Phosphorus silicate glass! 4 (PSG) to form an electrode window 5, and melt-processed. Electrode window 5 in source and drain 2 and 3 regions
An aluminum electrode 6 and a wiring pattern 7 are deposited on the substrate. The electrode window has a minute length of about 1μ, and the width of the wiring pattern 7 is also 1μ~
2μ, and strict precision is required for mask positioning during pattern transfer.The electrode 6 and wiring pattern 7 shown in Fig. 1 is ideal, but the pattern width becomes large and the degree of integration of the substrate is restricted. Moreover, as described above, mask alignment is difficult.
そこでパターン巾を小さくとり電極窓5との重ね合せが
多少ずれても素子動作が可能となるよう設計することに
よシマスフ位置合せ精度は軽減するが活性領域(ソース
、ドレイン)の一部が露出しパターン形成時のエツチン
グに際しアルミニウム膜と共にエツチングされ深いビッ
ト8を生じ、n+領領域p領域との接合部でリークをお
こし、基板にダメージを与える。Therefore, by making the pattern width small and designing the device so that it can operate even if the overlapping with the electrode window 5 is slightly misaligned, the alignment accuracy of the strips will be reduced, but a part of the active region (source, drain) will be exposed. However, during etching during pattern formation, it is etched together with the aluminum film, resulting in deep bits 8, causing leakage at the junction with the n+ region and the p region, and damaging the substrate.
(d) 発明の目的
本発明は上記の点に鑑み電極窓に伝導性金属層を被着形
成させる被膜手段を提供し、配線パターン幅をより微細
化し半導体基板の集積化を計ることを目的とする。(d) Purpose of the Invention In view of the above points, the present invention has an object to provide a coating means for depositing and forming a conductive metal layer on an electrode window, thereby further reducing the width of a wiring pattern and increasing the integration of a semiconductor substrate. do.
(e) 発明の構成
上記目的は本発明によれば基板に施す電極パターニング
において該基板上の絶縁膜に窓をあけ、窓を覆って第1
の導電層を形成後該第1の導1層上に第2の導電層を形
成し、該第1の導電層をストッパとして該第2の導電層
をパターニングし、該第2の導電層をマスクにして該第
1の4電層をエツチング除去することによって達せられ
る。(e) Structure of the Invention According to the present invention, in electrode patterning on a substrate, a window is formed in the insulating film on the substrate, and the first
After forming a conductive layer, a second conductive layer is formed on the first conductive layer, and the second conductive layer is patterned using the first conductive layer as a stopper. This is achieved by etching away the first quaternary layer using a mask.
(f) 発明の実施例 以下本発明の実施例を図面によシ詳述する。(f) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.
第3図は本発明の一実施例である半導体装置の製造プロ
セスを示す図である。(a) K示すように拡散工程に
よりソースドレイン領域を形成した集積回路基板11に
スパッタ法により伝導性金属膜を形成させる。被着させ
る金属膜12は500^〜1oooAの膜厚でアルミニ
ウムエツチングに対して選択性ある部材即ちアルミ配線
のパターニングに際してストッパーとなりソース、ドレ
イン領域を浸食しない例えばタングステン(W)又はモ
リブデン(Mo)等を用いる。次いで(b)に示すよう
にスパッタ法によりアルミニウム層を形成させ、マスク
合せによりアルミ電極14及び回路パターンを形成する
。次いでアルミニウム層をエツチングし更にアルミ電極
14及びアルミ配線をマスクにして金属膜12をエツチ
ングする。アルミニウム層のエツチングに際して′電極
窓13の周辺はアルミエッチャントに対して選択性のあ
る金属膜12で被覆されているためソースあるいはドレ
インのn+層がエツチングされることはな〈従来のより
なn+p接合リークは阻止される。またアルミ電極14
は図により明らかなように高融点のタングステン又はモ
リブデン等の金属膜」2がバリア材として介在するため
シリコン層との共晶は防止される。FIG. 3 is a diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. (a) As shown in K, a conductive metal film is formed by sputtering on an integrated circuit substrate 11 on which source and drain regions have been formed by a diffusion process. The metal film 12 to be deposited has a film thickness of 500^ to 100A and is a material that is selective to aluminum etching, that is, a material such as tungsten (W) or molybdenum (Mo) that acts as a stopper during patterning of aluminum wiring and does not corrode the source and drain regions. Use. Next, as shown in (b), an aluminum layer is formed by sputtering, and aluminum electrodes 14 and a circuit pattern are formed by mask alignment. Next, the aluminum layer is etched, and the metal film 12 is further etched using the aluminum electrode 14 and aluminum wiring as a mask. When etching the aluminum layer, the periphery of the electrode window 13 is covered with a metal film 12 that is selective to aluminum etchant, so the n+ layer of the source or drain is not etched. Leak is prevented. Also, aluminum electrode 14
As is clear from the figure, a metal film 2 such as tungsten or molybdenum having a high melting point is interposed as a barrier material, so that eutectic formation with the silicon layer is prevented.
第4図は本発明の他の実施例である半導体基板を示す断
面図である。図において集積回路基板21の電極窓23
に伝導性金属22をスパッタ法により埋込み形成し、エ
ツチング形成した後にアルミ電極24及びアルミ配線を
行なうようにしたものである。この場合伝導性金属22
は膜厚を十分とれるのでアルミエッチャントに対して選
択性があってもなくてもよい。FIG. 4 is a sectional view showing a semiconductor substrate according to another embodiment of the present invention. In the figure, an electrode window 23 of an integrated circuit board 21
A conductive metal 22 is embedded by sputtering, and after etching, aluminum electrodes 24 and aluminum wiring are formed. In this case conductive metal 22
Since the film can be sufficiently thick, it may or may not be selective to aluminum etchant.
(g) 発明の効果
以上詳細に説明したように本発明の半導体プロセスにお
いて、伝導性金属を電極窓に被着形成した集積回路とす
ることにより、電極窓と電極との重ね合せは不要となシ
、パターニングに際してマスク位置合せ精度は簡易化さ
れ、高集積化が期待できる等優れた効果がある。(g) Effects of the Invention As explained in detail above, in the semiconductor process of the present invention, by forming an integrated circuit in which conductive metal is deposited on the electrode window, there is no need to overlap the electrode window and the electrode. Furthermore, mask alignment accuracy during patterning is simplified, and high integration can be expected.
第1図、第2図の各(a)、 (b)図はMO8型半導
体基明の一実施例である半導体装置の製造プロセスを示
す図、第4図は本発明の他の実施例である半導体基板を
示す断面図である。
図中、11.21・・・・・・集積回路基板、12.2
2・・・・・・金属膜、13.23・・・・・・電極窓
、14.24・・・・・・アルミ電極。
峯 1 閉
(”) ’(−4
)≠?閃
第
キ・Figures 1 and 2 (a) and 2 (b) are diagrams showing the manufacturing process of a semiconductor device which is an embodiment of the MO8 type semiconductor based device, and Figure 4 is a diagram showing another embodiment of the present invention. FIG. 1 is a cross-sectional view showing a certain semiconductor substrate. In the figure, 11.21... integrated circuit board, 12.2
2... Metal film, 13.23... Electrode window, 14.24... Aluminum electrode. Mine 1 Close (”) '(-4
)≠? Sendai Ki・
Claims (2)
は異種金属の導電層上に形成されてなり、該電極を該電
極窓よシ微細パターンとなし得るように構成されている
ことを特徴とする半導体装置。(1) The electrode formed in the electrode window on the substrate is formed on a conductive layer of a different metal from the electrode, and is configured so that the electrode can be formed into a fine pattern similar to the electrode window. A semiconductor device characterized by:
板上の絶縁膜に窓をあけ、窓を覆って第1の導N、J侵
を形成後、該第1の導電層上に第2の導電層を形成し、
該第1の導電層をストッパとして該第2の導を層をパタ
ーニングし、該第2の導電層をマスクにして該第1の導
電層をエツチング除去してなることを特徴とする半導体
装置の製造方法。(2) In the electrode patterning performed on the substrate, a window is formed in the insulating film on the substrate, and after forming a first conductive layer by covering the window, a second conductive layer is formed on the first conductive layer. form a layer,
A semiconductor device characterized in that the second conductive layer is patterned using the first conductive layer as a stopper, and the first conductive layer is etched away using the second conductive layer as a mask. Production method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2228683A JPS59148340A (en) | 1983-02-14 | 1983-02-14 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2228683A JPS59148340A (en) | 1983-02-14 | 1983-02-14 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59148340A true JPS59148340A (en) | 1984-08-25 |
Family
ID=12078499
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2228683A Pending JPS59148340A (en) | 1983-02-14 | 1983-02-14 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59148340A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56155550A (en) * | 1980-05-02 | 1981-12-01 | Hitachi Ltd | Multilayer wiring structure and manufacture thereof |
JPS56167331A (en) * | 1980-05-28 | 1981-12-23 | Sony Corp | Manufacture of semiconductor device |
-
1983
- 1983-02-14 JP JP2228683A patent/JPS59148340A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56155550A (en) * | 1980-05-02 | 1981-12-01 | Hitachi Ltd | Multilayer wiring structure and manufacture thereof |
JPS56167331A (en) * | 1980-05-28 | 1981-12-23 | Sony Corp | Manufacture of semiconductor device |
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