JP3136714B2 - Resistance formation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a resistor suitable for use in the manufacture of an integrated circuit device such as a digital-analog mixed LSI, and more particularly to a method of forming a resistor on a part of a high resistivity material layer.
After forming an insulating layer by laying on the high resistivity material layer and insulating layer
To form a low-resistivity material layer,
Of high resistivity material layer, high resistivity material layer, insulating layer and low resistivity
A low resistance and a high resistance can be formed with a small number of steps by patterning the laminated material layer with a single etching process.

[0002]

2. Description of the Related Art Conventionally, a polycide gate process has been known as a process for manufacturing a MOS type LSI. In this process, polycide is used as a gate electrode or wiring material, and source and drain regions are formed by selectively implanting impurity ions into the semiconductor surface using the polycide gate pattern as a mask. Here, the polycide is a silicide (for example, Mo ₃₎ on the polysilicon layer.
(Si ₄ , WSi, TiSi, etc.) layer is formed, and the resistivity is reduced to about 1/10 compared to polysilicon.

When a resistance is required in the polycide gate process, low resistance can be formed in the same step as the polycide gate, but high resistance can be formed in the same step as the polycide gate. It is conceivable that the gate is formed in a step different from that of the polycide gate. As an LSI requiring high resistance, for example, there is a digital-analog mixed LSI such as a DA converter or an AD converter. In this type of LSI, for example, a high-precision high resistance as a ladder resistor is formed in a small size. Is required.

[0004]

As described above, in the method of forming a high resistance in the same step as that of the polycide gate, it is necessary to form a long resistance path, which results in an increase in chip size and floating. There has been a problem that the increase in the capacity hinders the increase in speed.

Further, in the method of forming a high resistance in a step different from that of the polycide gate, it is necessary to add a step of depositing a material having a high resistivity such as polysilicon and patterning the same, thereby increasing the cost. There was an inconvenience.

An object of the present invention is to provide a novel resistance forming method capable of forming a low resistance (or an electrode or a wiring) and a high resistance in a small number of steps.

[0007]

According to the present invention, there is provided a method for forming a resistor, comprising the steps of: (a) forming a first resistive material layer by applying a resistive material having a relatively high resistivity on an insulating surface of a substrate; (B) forming an insulating layer overlying a part of the first resistance material ;
And (c) comparing the first resistive material layer and the insulating layer by superimposing them.
A second resistive material layer by depositing a resistive material with low electrical resistivity
A step of, first laminate consisting of; (d) first and second resistive material layer
And the first resistance material layer, the insulating layer, and the second resistance
A second resistive pattern and a second resistive pattern
Simultaneously with the pattern and the second resistance pattern.
To remain corresponding to the first resistance pattern.
A first resistor comprising a portion of the first stack
Remaining in correspondence with the resistance pattern of
Forming a second resistor consisting of the remaining portion of the first resistance material layer electrically separated from the remaining portion of the second resistance material layer .

In such a resistance forming method, a conductive material layer and a conductive pattern are used instead of the first resistive material layer and the first resistive pattern, respectively, so that an electrode or a wiring is used instead of the first resistive material. May be formed.

[0009]

[0010]

[0011]

According to the method of forming a resistor according to the present invention, except that a step of forming an insulating layer for the second resistor is added .
The steps up to patterning for the first and second resistors are common. This is the same when an electrode or a wiring is formed instead of the first resistor.

[0012]

[0013]

1 to 3 show a method of forming a resistor for explaining the present invention. Steps (1) to (1) corresponding to the respective drawings are shown.
(3) will be described sequentially.

(1) Polysilicon is deposited as a material having a relatively high resistivity on the insulating film 12 such as silicon oxide which covers the surface of the semiconductor substrate 10 such as silicon to form a polysilicon layer 14. Then, the polysilicon layer 14
A silicide, such as WSi, is deposited as a material having a relatively low resistivity to form a silicide layer 16. In FIG. 1, the portion to the left of the arrow A is a portion where an analog circuit is to be integrated, and the portion to the right of the arrow D is a portion where a digital circuit is to be integrated.

(2) Next, a resist layer corresponding to a desired low-resistance pattern and a high-resistance pattern is disposed on the polysilicon layer 14 and the silicide layer 16 (polycide layer). Patterning is performed by selectively etching the polycide layer as a mask. After that, the resist layer is removed. As a result, a low-resistance RD including the polysilicon remaining portion 14D and the silicide remaining portion 16D corresponding to the low-resistance pattern is formed, and the polysilicon remaining portion 14A and the silicide remaining portion 16A are left corresponding to the high-resistance pattern. .

(3) Next, after a resist layer is disposed on the upper surface of the substrate so as to expose a portion on the left side of arrow A and cover a portion on the right side of arrow D, selective etching is performed using the resist layer as a mask. Due to silicide remaining part 1
6A is removed. After that, the resist layer is removed. As a result, a high resistance RA composed of the polysilicon remaining portion 14A is obtained.

In this case, in the selective etching process, etching is performed so as to leave the first and second portions 16a and 16b of the silicide remaining portion 16A corresponding to both ends of the polysilicon remaining portion 14A. Alternatively, the second portions 16a and 16b may be used as terminals of the high resistance RA. As another method of forming the terminal, a method of forming a conductive layer in advance on portions to be located at both ends of the polysilicon remaining portion 14A may be used.

According to the above-described resistance forming method, the low resistance RD
The low resistance RD and the high resistance RA can be easily obtained only by adding a step of removing the silicide remaining portion 16A to the step of forming the above. When patterning is performed in the process of FIG. 2 in accordance with an electrode pattern such as a gate electrode or a wiring pattern, an electrode or a wiring made of polycide is obtained as in the case of the low resistance RD. Before patterning, for example, arrow A in FIG.
The silicide layer 16 may be etched away at the left side to expose a part of the polysilicon layer 14, and then the low resistance RD and the high resistance RA may be obtained by simultaneous patterning. In this method, the high resistance RA has higher accuracy.

Since the resistance RA made of polysilicon has a small variation in resistance value, it is suitable for use in a high-precision analog circuit. Further, an electrode or wiring made of polycide has a small resistance value, and thus is suitable for use in a high-speed logic circuit.

FIGS. 4 to 6 show a first embodiment of the present invention.
That resistor forming method indicates the omitted details are denoted by the same reference numerals description the same parts as FIGS.

In the step shown in FIG. 4, after a polysilicon layer 14 is formed on the insulating film 12 covering the surface of the semiconductor substrate 10, SiO 2 is formed on the polysilicon layer 14 on the left side of the arrow A.
An insulating layer 18 such as ₂ is formed. Specifically, after forming a SiO ₂ layer on the polysilicon layer 14 by the CVD method or the like is etched remove the SiO ₂ layer in the unnecessary portion (the right portion from the arrow D). Thereafter, a silicide layer 16 is formed to cover the polysilicon layer 14 and the insulating layer 18.

Next, in the step of FIG.
Then, the lamination of the silicide layer 16 and the lamination of the polysilicon layer 14, the insulating layer 18, and the silicide layer 16 are simultaneously patterned according to the low resistance pattern and the high resistance pattern, respectively. As a result, a low resistance RD including the polysilicon remaining portion 14D and the silicide remaining portion 16D corresponding to the low resistance pattern is formed, and a high resistance RA including the polysilicon remaining portion 14A corresponding to the high resistance pattern is formed.
Is formed. In this case, the remaining portion 18A of the insulating layer 18
Are the polysilicon remaining portion 14A and the silicide remaining portion 16
A is electrically separated from A to form a silicide remaining portion 1
6A prevents it from acting as a resistor.

Thereafter, in the step of FIG. 6, an oxidation process is performed to form an oxide film 20D on the remaining portions 14D and 16D and an oxide film 20A on the remaining portions 14A and 16A, respectively.

According to the resistance forming method shown in FIGS.
By simply adding the step of forming the insulating layer 18 to the step of forming D, the low resistance RD and the high resistance RA can be easily obtained. When patterning is performed in the step of FIG. 5 in accordance with an electrode pattern such as a gate electrode or a wiring pattern, an electrode or wiring made of polycide is obtained as in the case of the low resistance RD.

FIG. 7 is a view for explaining a resistance forming method according to a second embodiment of the present invention. In FIG. 7, parts similar to those in FIGS. Detailed description is omitted.

The feature of the embodiment of FIG. 7 is that when the insulating layer 18 is selectively etched in the process of FIG.
And second terminal holes are formed, and the first and second portions 16a and 16b of the silicide layer 16 are left corresponding to the first and second terminal holes when patterning is performed in the step of FIG. And serve as a terminal. In this case, the silicide remaining portion 16A is electrically separated from the first and second portions 16a and 16b by a groove or the like, or is entirely etched away so as not to be left.

In the resistance forming method shown in FIGS.
Not only the terminal formation method shown in FIG. 7, but also a method in which a terminal conductive layer is formed in advance on portions to be located at both ends of the polysilicon remaining portion 14A can be used.

[0028]

As is evident from the foregoing description, according to the invention, the step forming a low resistance to most of the process by simply adding a step of forming an insulating layer for separation for high resistance (or electrodes or wires) Therefore, a low resistance (or an electrode or a wiring) and a high resistance can be formed with a small number of steps, and the effect of reducing cost can be obtained.

[Brief description of the drawings]

FIG. 1 illustrates a method of forming a resistor according to the present invention .
FIG. 4 is a cross-sectional view of a substrate showing a step of forming a polysilicon layer and a silicide layer .

FIG. 2 shows a polysilicon layer and a silicon layer following the process of FIG. 1;
FIG. 4 is a cross-sectional view of a substrate showing a patterning step of an id layer.

FIG. 3 is a process of removing a remaining silicide portion following the process of FIG. 2;
FIG.

FIG. 4 illustrates a resistance forming method according to a first embodiment of the present invention;
Of polysilicon layer, insulating layer and silicide layer in
It is a board | substrate sectional view which shows a process .

FIG. 5 shows a polysilicon layer, an insulating layer, and the like following the process of FIG. 4;
Substrate cross-sectional view showing the patterning process of
is there.

FIG. 6 is a sectional view of the substrate showing an oxidation step following the step of FIG. 5;
It is.

FIG. 7 is a sectional view of a substrate for explaining a resistance forming method according to a second embodiment of the present invention.

[Explanation of symbols]

10: semiconductor substrate, 12: insulating film, 14: polysilicon layer, 16: silicide layer, 18: insulating layer, RA: high resistance, RD: low resistance.

Claims (2)

(57) [Claims] 1. A (a) forming a first resistive material layer a high resistance material having a relatively resistivity insulating surface of the substrate by adhering, one (b) said first resistive material To form an insulating layer
And (c) comparing the first resistive material layer and the insulating layer by superimposing them.
A second resistive material layer by depositing a resistive material with low electrical resistivity
A step of, first laminate consisting of; (d) first and second resistive material layer
And the first resistance material layer, the insulating layer, and the second resistance
A second resistive pattern and a second resistive pattern
Simultaneously with the pattern and the second resistance pattern.
To remain corresponding to the first resistance pattern.
A first resistor comprising a portion of the first stack
Remaining in correspondence with the resistance pattern of
Forming a second resistor consisting of the remaining portion of the first resistance material layer electrically separated from the remaining portion of the second resistance material layer . And (b) forming a resistive material layer by applying a resistive material to an insulating surface of the substrate; and (b) forming an insulating layer on part of the resistive material layer.
And (c) coating a conductive material on the resistive material layer and the insulating layer.
Forming a conductive material layer is deposited, the first product consisting of the resistive material layer and the conductive material layer (d)
Layer, the resistance material layer, the insulating layer, and the conductive material layer.
A second laminate and a conductive pattern and a resistance pattern, respectively.
By conducting patterning simultaneously according to
From a portion of the first stack remaining corresponding to the pattern
Electrode or wiring and the resistance pattern
The insulating layer electrically connects the remaining portion of the conductive material layer
Forming a resistance comprising the separated remaining portion of the resistance material layer.