JPS63132453A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To reduce leakage current and gate resistance, and make an element minute, by forming metal interconnections after exposing the surfaces of a gate electrode and an ohmic electrode on the substrate surface on which metal electrodes are formed, and forming a flat insulating film. CONSTITUTION:After a gate electrode 12 and an ohmic electrode 13 are formed on a channel region 1a and a contact region 1b of a compound semiconductor substrate, respectively, an insulating film 14 and a resist film 19 are formed. By reactive ion etching, the film 14 is made flat, and the surfaces of the electrodes 12 and 13 are exposed. After the residual part 19a of the resist film 19 is eliminated, wiring metal is vapor-deposited on the film 14 and patterned by etching to form metal interconnections 18 and 17 to the electrodes 12 and 13.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Field of Application) 1. This relates to a method for manufacturing a compound semiconductor device, in detail (1) connection of metal electrodes and metal wiring in the device. This applies to

(Prior art) In a GaAs conduit circuit, the metal wiring is semi-insulating i
Generally, an it'f junction is formed on Jlfi.

This is an attempt to shorten the process by taking advantage of the semi-insulating properties unique to GaAs substrates, but with the recent increase in the integration of GaAs integrated circuits, leakage current flowing through semi-insulating substrates,
Problems such as the puck-gating effect cannot be avoided with this construction.

In order to eliminate these problems, there is a method of forming a 5i02 film before forming the metal wiring, forming a contact hole therein, and connecting the polar metal and the metal wiring, as in the case of silicon integrated circuits. In this method, as shown in the cross-sectional view of the device in FIG.
! ! An insulating film 4 is formed on a compound semiconductor substrate 1 on which a conductive layer 1a and an N+ conductive layer 1b, a goo electrode 2, and an ohmic electrode 3 are provided. A gate electrode contact hole 6 is opened in the pad portion 2a of the gate electrode drawn out of the area. Next, the wiring metal is deposited, parquet is performed, and the 1N metal arrangement is connected at the contact hole 5°6! Form j17.8.

However, in the conventional method of forming the insulating film, the metal wirings 7 and 8 are formed on the insulating film 4, and although problems such as the leakage current described above are reduced, there are still the following drawbacks.

That is, as shown in FIG. 8, the Goo 1-Kawa method for miniaturized field effect transistors has almost the minimum pattern size, and the pad portion 2a of the drawer is used for wiring connection between Goo 1 and electrode 2. is necessary.

Since both the pad portion 2a of the gate electrode and the ohmic electrode 3 are formed on the QaAs substrate, the phase difference is high! It is necessary to allow for a design margin in order to maintain the insulation of 1, and therefore the area occupied by the device on the Qa AS substrate increases.

Recently, compound semiconductor field effect transistors have increasingly become self-line type transistors that use a high-melting point metal for the gate electrode for the purpose of high-integration and high-speed operation. When this high melting point metal is used for the gate electrode, it is extremely difficult to increase the thickness of the metal film due to problems in adhesion and workability. Therefore, the film thickness of a normal gate electrode is 3000 to 50 mm.
00 people is the maximum. When the gate size falls into the submicron range, the gate resistance in the structure shown in Figure 8 is several hundred Ω.
may reach. The Iζ resistor placed in series with such a gate reduces the maximum operating frequency of the field effect transistor, and an increase in gate resistance significantly reduces the switching speed of the device.

(Problems to be Solved by the Invention) The present invention has been made for the purpose of eliminating the drawbacks of the prior art described above. With the aim of
At the same time, the aim is to simplify the manufacturing process.
The present invention provides a manufacturing method that enables highly integrated and high-speed compound semiconductor devices.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, a field effect transistor having a gate electrode and an ohmic electrode is formed on a compound semiconductor substrate, and an insulating film is first coated on this substrate. wear. Thereafter, this insulating film is etched back to expose the surface of the gate electrode. On the other hand, regarding the ohmic electrode, there are two methods: a method in which the surface of the ohmic electrode is exposed together with the surface of the gate electrode in the etch-back step, and a method in which a contact hole for the ohmic electrode is simultaneously formed in the etch-back step. The former is the first invention, and the latter is the second invention. The method of manufacturing a semiconductor device is characterized in that a metal wiring pattern is formed to connect to the surface or contact hole exposed by the etch-back process.

(Example) Example 1 according to the first invention will be described with reference to the process diagram of FIG.

As shown in FIG. 1(a), a channel region 111a and an N+ contact f are formed on a compound semiconductor substrate 1.
f1fi! Ib, electrodes 1 to 12 formed only on the channel region kila without a pad portion, and ohmic electrode 13 formed on the contact 1VA1b.
In a field-effect transistor consisting of a shock[-ki] J'3, the gate voltage l'fi12 is like W? The ohmic electrode 13 is made of an Au-Qe alloy and has a thickness of 2000×. First, as shown in FIG. 1(b), CVI) SiO214 is formed on this substrate to a thickness of 3,000 to 5,000 layers, and then a resist 19 is coated with a thickness of approximately 1 μm.
At 9, I play Subinko 1~. Next, as shown in FIG. 1(C), etchback is performed using reactive ion etching (RrE) to flatten the CVD 5in 214 and expose both the surfaces of the goo 1-electrode 12 and the ohmic film 13. . After removing the remaining resist 19a, the flattened 5i is removed as shown in FIG. 1(d).
A metal wiring metal such as A1 is deposited on o2a14, and wiring patterning of a metal wiring 18 connected to the gate/electrode 12 and a metal wiring 17 connected to the ohmic electrode 13 is performed by etching. In order to prevent the reaction between this ohmic electrode 13 and gate electrode 4412 and the △1 wiring key 4 material,
It is also possible to deposit a barrier metal layer such as a Ti-W alloy before depositing AI and use a two-layer wiring material such as ri-W/AI.

Regarding the steps after the wiring shown in FIG. 1 (d>), if there is only one layer of wiring, a passivation film may be formed thereon, or it is also possible to proceed with a two-layer wiring process.

FIG. 2 is a cross-sectional view of the Schottky field effect transistor obtained by the manufacturing method of Example 1 (same as FIG. 1(d));
FIG. 3 is a plan view of the arrangement of the metal N-pole and wiring metal shown in FIG. 2. As can be seen from both figures, since the gate electrode 12 can be connected to the wiring 18 on its entire surface, the gate resistance can be reduced.

In the case of Example 1 in which AI wiring was used as the wiring 18, the value of this gate resistance could be reduced to 1/100 compared to the conventional technology shown in FIGS. 7 and 8.

FIG. 3 also shows the gate electrode extension portion 2a in FIG.
Since there is no such thing, it is advantageous for the integration of elements. Furthermore, the process of the first embodiment shown in FIG. 1 does not include a mask alignment process for forming the contact hole 1, thereby simplifying the manufacturing process.

Next, the process of Example 2 according to the second invention will be explained with reference to FIG.
explain.

The semiconductor substrate 1 used in Example 2 has a
Compound semiconductor (,+i channel region 1a formed in substrate 1, N+ contact region li!1 as shown in
b. In a Schottky field effect transistor consisting of a gate electrode 42 formed only on the channel region 1a and having no pad portion, and an ohmic electrode 43 formed on the contact region 1b, the thickness of the refractory metal of the gate electrode 42 The thickness of the AU-Ge alloy of the ohmic electrode 43 is relatively thick at 5000×, and the thickness of the AU-G e alloy is relatively thin at 1000×. First, as shown in FIG. 4(b), 3000 ml of CVDSi 0244
~5000. & Ml, and further spin-coded four resists with a film thickness of approximately 1 μm, and this resist 49
Contacts 1 for ohmic electrodes to hole patterning 4.9a are formed. Next, as shown in FIG. 4(C), etching back is performed by reactive ion etching (RIE) to flatten the cvos:0244 and expose the surface of the gate electrode 42.

Here, the CVD exposed in the resist pattern 49a
Si 02 part is etched in RIE and CVDS
Contact hole 4 for ohmic electrode on i 0244
4a is formed simultaneously. Next, the residue 49 of Regis 1~
After removing a, as shown in FIG. 4(d), Example 1
Same metal arrangement as in! Form 47.48.

FIG. 5 is a cross-sectional view of the Schottky field effect transistor obtained by the manufacturing method of Example 2 (same as FIG. 4(d));
FIG. 6 is a plan view of the arrangement of the metal electrodes and wiring metal shown in FIG. 5. As can be seen from both figures, since the gate electrode 42 can be connected to the wiring 48 on its entire surface, the gate resistance can be reduced.

When the wiring 48 is the A1 wiring, this gate resistance is +/10 compared to the conventional technology shown in FIGS. 7 and 8.
We were able to reduce it to 0. Further, FIG. 6 does not have a gate electrode extension part as shown in FIG. 8, which is advantageous for device integration. Roughly speaking, in the process of the second embodiment shown in FIG. 4, there is no elaborate mask alignment process for forming a contact hole for a gate electrode, which simplifies the manufacturing process.

[Effects of the Invention] According to the present invention, the gate resistance can be reduced to about 1/100 compared to the conventional technology, as explained in the practical example above.
Therefore, the dependence of gate resistance on gate dimensions can be reduced, which is extremely advantageous when shortening the gate length and improving the maximum operating frequency of a field effect transistor.

Moreover, when comparing FIGS. 3 and 6, which are pattern drawings of the field effect transistor according to the present invention, with FIG. 8, which is a pattern drawing of a conventional structure, it is found that the gate electrode lead-out portion can be omitted according to the present invention, resulting in miniaturization of the device. can be achieved. In general, according to the present invention, since the gate electrode contact is formed in a self-lined manner by etching back, the mask alignment process can be omitted, and the manufacturing process can be simplified.

As described above, the manufacturing method of the present invention capable of manufacturing highly integrated and high-speed semiconductor devices has been provided.

[Brief explanation of the drawing]

1(a) to d) are device cross-sectional views showing the steps of Example 1 of the present invention, FIG. 2 is a device cross-sectional view of the field effect l-transistor obtained in Example 1, and FIG. Figure 2 is a planar layout of metal electrodes and metal wiring in a transistor, Figures 4 (a) to d) are cross-sectional views of the device showing the steps of Example 2 of the present invention, and Figure 5 is the electric field obtained in Example 2. Effect 1 - A cross-sectional view of a transistor; FIG. 6 is a planar layout of metal electrodes and metal wiring in a transistor; FIG. 7 is a cross-sectional view of a charge effect transistor obtained by a conventional manufacturing method; FIG. FIG. 7 is a plan layout diagram of metal electrodes and metal wiring in a conventional transistor. DESCRIPTION OF SYMBOLS 1... Compound semiconductor substrate, 1a... Channel region, 1b... N1 conductive layer, 2.12.42... Metal electrode (gate electrode), 3,13.43... Metal electrode (ohmic electrode), 4,14.44...insulating film,
44a...Patterning opening, 7.17, 47°8
．． 18.48...Metal wiring, 19.49...Resist film. Figure 1 Figure 2 Figure 3 Figure 5

Claims (1)

[Claims] 1. In manufacturing a semiconductor device comprising a metal electrode formed on a compound semiconductor substrate and a metal wiring connected to the metal electrode, an insulating film is formed on the compound semiconductor substrate on which the metal electrode is formed. manufacturing a compound semiconductor device, which comprises a step of forming a gate electrode and an ohmic electrode by planarizing the insulating film, and a step of forming a metal wiring to connect to the exposed metal electrode. Method. 2. In manufacturing a compound semiconductor device comprising a metal electrode formed on a compound semiconductor substrate and a metal wiring connected to the metal electrode, a step of forming an insulating film on the compound semiconductor substrate on which the metal electrode is formed. , a step of patterning the insulating film on the ohmic electrode to form an opening and at the same time exposing the surface of the gate electrode by flattening the insulating film on the gate electrode, and metal wiring connected to the opened ohmic electrode and the exposed gate electrode. A method for manufacturing a compound semiconductor device, comprising the step of forming a compound semiconductor device.