JP2000133708A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JP2000133708A JP2000133708A JP10306545A JP30654598A JP2000133708A JP 2000133708 A JP2000133708 A JP 2000133708A JP 10306545 A JP10306545 A JP 10306545A JP 30654598 A JP30654598 A JP 30654598A JP 2000133708 A JP2000133708 A JP 2000133708A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- forming
- film
- wiring
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明は電圧依存性がない容
量素子を搭載した半導体装置の製造方法に関するもので
ある。[0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing a semiconductor device having a capacitance element having no voltage dependency.
【０００２】[0002]
【従来の技術】近年、Ａ／Ｄコンバータ、Ｄ／Ａコンバ
ータ等のアナログ又はアナログ・デジタルＬＳＩに内蔵
するフィルタ回路や積分回路の精度を向上させるため
に、高精度で電圧依存性の無い容量素子が望まれてい
る。2. Description of the Related Art In recent years, in order to improve the accuracy of a filter circuit and an integrating circuit built in an analog or analog / digital LSI such as an A / D converter and a D / A converter, a capacitor element having high accuracy and no voltage dependency has been developed. Is desired.
【０００３】この電圧依存性とは以下の式で与えられ
る。The voltage dependency is given by the following equation.
【０００４】 電圧依存性γ＝（Ｃ（Ｖ）−Ｃ（０））／Ｃ（０）Ｖ ここで、Ｃ（Ｖ）、Ｃ（０）は印加電圧がＶ及び０のと
きのキャパシタの容量値である。高精度なＡ／Ｄコンバ
ータ、Ｄ／Ａコンバータでは低い電圧依存性が要求され
る。例えば、１４ＢｉｔのＡ／Ｄコンバータでは電圧依
存性は１００ｐｐｍ以下である。Voltage dependence γ = (C (V) −C (0)) / C (0) V Here, C (V) and C (0) are capacitances of the capacitor when the applied voltage is V and 0. Value. A high-precision A / D converter and D / A converter require low voltage dependency. For example, in a 14-bit A / D converter, the voltage dependency is 100 ppm or less.
【０００５】従来このような容量素子としては、下部電
極に拡散層又はポリシリコン層を、上部電極にポリシリ
コン又はアルミニウム配線層を用いたものが使用されて
きた。Conventionally, as such a capacitive element, an element using a diffusion layer or a polysilicon layer for a lower electrode and using a polysilicon or aluminum wiring layer for an upper electrode has been used.
【０００６】また、高精度で電圧依存性がない容量素子
として、半導体基板上に形成された第１の多層配線層を
下層配線に、その下層配線上に形成された絶縁膜とその
絶縁膜上に形成された第２の多層用金属膜を上部電極と
した容量素子が特開平５−９５０８２号公報に開示され
ている。以下、図２を用いてこの従来技術を説明する。Further, as a capacitor element having high accuracy and no voltage dependency, a first multilayer wiring layer formed on a semiconductor substrate is used as a lower wiring, an insulating film formed on the lower wiring and an insulating film formed on the lower wiring. Japanese Patent Application Laid-Open No. 5-95082 discloses a capacitive element using the second multilayer metal film formed as the upper electrode as an upper electrode. Hereinafter, this prior art will be described with reference to FIG.
【０００７】まず、図２（ａ）に示すように、シリコン
基板２９を熱酸化し、素子分離領域に膜厚が５００ｎｍ
程度のシリコン酸化膜２０を形成した後、スパッタ法に
よって、膜厚が１μｍ程度の第１アルミニウム膜２１を
形成し、更にスパッタ法により、膜厚０．１μｍ程度の
窒化チタン２２を形成する。次に、フォトリソグラフィ
によるレジストをマスクとして窒化チタン２２と第１ア
ルミニウム膜２１をドライエッチングによってパターニ
ングし、第１配線及び容量下部電極を形成する。First, as shown in FIG. 2A, a silicon substrate 29 is thermally oxidized to a thickness of 500 nm in an element isolation region.
After the silicon oxide film 20 having a thickness of about 1 μm, a first aluminum film 21 having a thickness of about 1 μm is formed by sputtering, and a titanium nitride 22 having a thickness of about 0.1 μm is formed by sputtering. Next, the titanium nitride 22 and the first aluminum film 21 are patterned by dry etching using a photolithographic resist as a mask to form a first wiring and a capacitor lower electrode.
【０００８】次に、図２（ｂ）に示すように、配線層間
膜として常圧ＣＶＤ法による膜厚５００ｎｍ程度のＰＳ
Ｇ膜２３を形成する。次に、フォトリソグラフィによ
り、レジストマスクで容量素子の対向電極面に対応する
領域のＰＳＧ膜２３をドライエッチングによって、開口
する。その後、スパッタ法により、膜厚５０ｎｍ程度の
シリコン窒化膜２４を容量絶縁膜として形成する。Next, as shown in FIG. 2B, a PS having a thickness of about 500 nm is formed as a wiring interlayer film by a normal pressure CVD method.
A G film 23 is formed. Next, an opening is formed by dry etching in the PSG film 23 in a region corresponding to the counter electrode surface of the capacitor with a resist mask by photolithography. Thereafter, a silicon nitride film 24 having a thickness of about 50 nm is formed as a capacitor insulating film by a sputtering method.
【０００９】次に、図２（ｃ）に示すように、フォトリ
ソグラフィにより、レジストマスクで、ドライエッチン
グによって、配線間コンタクト領域２５のＰＳＧ膜２３
を開口し、スパッタ法によって、膜厚１μｍ程度の第２
アルミニウム膜２６を形成し、フォトリソグラフィによ
り、レジストマスクで第２アルミニウム膜２６をドライ
エッチングによってパターニングし、第２配線層を形成
する。Next, as shown in FIG. 2C, the PSG film 23 in the inter-wiring contact region 25 is formed by photolithography using a resist mask and dry etching.
And a second film having a thickness of about 1 μm is formed by sputtering.
An aluminum film 26 is formed, and the second aluminum film 26 is patterned by dry etching using a resist mask by photolithography to form a second wiring layer.
【００１０】[0010]
【発明が解決しようとする課題】しかしながら、上述し
た従来の半導体装置に搭載した容量素子では、下部電極
に拡散層又はポリシリコンという半導体材料を用いてい
るため、上下電極間に印加された電圧関係によって、下
部電極の拡散層又はポリシリコンの容量絶縁膜表面近傍
に空乏層が形成される。このため、従来の半導体装置に
搭載した容量素子では、容量値が電圧依存性をもつ。こ
のような容量値が電圧依存性をもつ容量素子フィルタ回
路や積分回路等のアナログ信号処理回路に用いられる
と、回路特性が非線形型になり、出力信号に歪みが生じ
たり、精度が低下したりするという問題が生じる。However, in the above-mentioned capacitive element mounted on the conventional semiconductor device, since the lower electrode is made of a semiconductor material such as a diffusion layer or polysilicon, the voltage relation applied between the upper and lower electrodes is reduced. As a result, a depletion layer is formed in the vicinity of the diffusion layer of the lower electrode or the surface of the polysilicon capacitance insulating film. For this reason, in a capacitance element mounted on a conventional semiconductor device, the capacitance value has a voltage dependency. When such a capacitance value is used for an analog signal processing circuit such as a capacitive element filter circuit or an integrating circuit having a voltage dependency, the circuit characteristic becomes non-linear, and the output signal is distorted or the accuracy is reduced. Problem arises.
【００１１】また、高精度で電圧依存性がない容量素子
として、半導体基板上に形成された第１多層配線を下層
配線に、その下層配線上に形成された絶縁膜とその絶縁
膜上に形成された第２多層用金属膜を上部電極とした、
特開平５−９５０８２号公報に開示された容量素子で
は、下部電極がゲート電極と同一材料で形成されてい
る、即ち、下部電極は容量素子以外の配線（ゲート電
極）と同一となるため、キャパシタは素子分離領域上に
形成する必要があり、チップサイズが広がるという問題
点がある。In addition, a first multilayer wiring formed on a semiconductor substrate is formed as a lower wiring, an insulating film formed on the lower wiring, and an insulating film formed on the insulating film as a high-precision capacitive element having no voltage dependency. The obtained second multilayer metal film was used as an upper electrode.
In the capacitor disclosed in JP-A-5-95082, the lower electrode is formed of the same material as the gate electrode, that is, the lower electrode is the same as the wiring (gate electrode) other than the capacitor. Must be formed on the element isolation region, and there is a problem that the chip size is increased.
【００１２】本発明は、電圧依存性がなく、高精度フィ
ルタ回路等に組み込める容量素子を有する半導体装置の
製造方法を提供することを目的とする。An object of the present invention is to provide a method for manufacturing a semiconductor device having a capacitance element which has no voltage dependency and can be incorporated in a high-precision filter circuit or the like.
【００１３】[0013]
【課題を解決するための手段】請求項１に記載の本発明
の半導体装置の製造方法は、拡散領域を有する半導体素
子が形成された半導体基板上に第１の層間絶縁膜を形成
する工程と、上記第１の層間絶縁膜の上記拡散領域上に
コンタクトホールを形成し、該コンタクホール内に導電
性プラグを埋設する工程と、上記第１の層間絶縁膜上
に、上記コンタクトプラグと電気的に接続された下部電
極となる金属膜とキャパシタ絶縁膜となる絶縁膜と上部
電極となる金属膜とを順次形成する工程と、キャパシタ
形成領域及び配線形成領域をマスクして、上記上部電極
及び下部電極となる金属膜と上記絶縁膜とを除去する工
程と、キャパシタ形成領域のみをマスクして、上記上部
電極となる金属膜及び上記絶縁膜を除去する工程と、全
面に第２の層間絶縁膜を形成し、該第２の層間絶縁膜の
所定の位置に上記キャパシタの上部電極又は下部電極と
なる金属膜表面が露出するようにコンタクトホールを形
成し、該コンタクトホール内に導電性プラグを埋設する
工程と、上記第２の層間絶縁膜上に配線材料を形成し、
所定の形状にパターニングし、上記導電性プラグを介し
て、上記金属膜と電気的に接続された配線を形成する工
程とを有することを特徴とするものである。According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first interlayer insulating film on a semiconductor substrate on which a semiconductor element having a diffusion region is formed; Forming a contact hole on the diffusion region of the first interlayer insulating film and burying a conductive plug in the contact hole; and forming an electrical contact with the contact plug on the first interlayer insulating film. Sequentially forming a metal film serving as a lower electrode, an insulating film serving as a capacitor insulating film, and a metal film serving as an upper electrode connected to the upper electrode and the lower electrode by masking a capacitor forming region and a wiring forming region. Removing the metal film serving as an electrode and the insulating film, removing the metal film serving as the upper electrode and the insulating film by masking only the capacitor formation region, and forming a second interlayer insulating film over the entire surface. And forming a contact hole at a predetermined position of the second interlayer insulating film so that a metal film surface serving as an upper electrode or a lower electrode of the capacitor is exposed, and a conductive plug is buried in the contact hole. Forming a wiring material on the second interlayer insulating film;
Patterning into a predetermined shape, and forming a wiring electrically connected to the metal film via the conductive plug.
【００１４】また、請求項２に記載の本発明の半導体装
置の製造方法は、拡散領域を有する半導体素子が形成さ
れた半導体基板上に第１の層間絶縁膜を形成する工程
と、上記第１の層間絶縁膜の上記拡散領域上にコンタク
トホールを形成し、該コンタクホール内に導電性プラグ
を埋設する工程と、上記第１の層間絶縁膜上に、上記コ
ンタクトプラグと電気的に接続された下部電極となる金
属膜とキャパシタ絶縁膜となる絶縁膜と上部電極となる
金属膜とを順次形成する工程と、キャパシタ形成領域と
下層配線形成領域とをマスクして、上記上部電極及び下
部電極となる金属膜と上記絶縁膜とを除去する工程と、
キャパシタ形成領域のみをマスクして、上記上部電極と
なる金属膜及び上記絶縁膜を除去し、下層配線を形成す
る工程と、全面に第２の層間絶縁膜を形成し、該第２の
層間絶縁膜の所定の位置に上記キャパシタの上部電極及
び上層配線と接続される下層配線となる金属膜表面が露
出するようにコンタクトホールを形成し、該コンタクト
ホール内に導電性プラグを埋設する工程と、上記第２の
層間絶縁膜上に配線材料を形成し、所定の形状にパター
ニングし、上記導電性プラグを介して、上記キャパシタ
の上部電極又は上記下層配線に電気的に接続された上記
上層配線を形成する工程とを有することを特徴とするも
のである。According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first interlayer insulating film on a semiconductor substrate on which a semiconductor element having a diffusion region is formed; Forming a contact hole on the diffusion region of the interlayer insulating film, and burying a conductive plug in the contact hole; and electrically connecting the contact plug on the first interlayer insulating film. Forming a metal film serving as a lower electrode, an insulating film serving as a capacitor insulating film, and a metal film serving as an upper electrode in order, and masking a capacitor forming region and a lower wiring forming region to form the upper electrode and the lower electrode; Removing the metal film and the insulating film,
Forming only a capacitor forming region, removing the metal film serving as the upper electrode and the insulating film, and forming a lower wiring, and forming a second interlayer insulating film on the entire surface, and forming the second interlayer insulating film. Forming a contact hole at a predetermined position of the film so that a metal film surface serving as a lower wiring connected to the upper electrode and the upper wiring of the capacitor is exposed, and burying a conductive plug in the contact hole; A wiring material is formed on the second interlayer insulating film, patterned into a predetermined shape, and the upper layer wiring electrically connected to the upper electrode or the lower wiring of the capacitor via the conductive plug. And a forming step.
【００１５】[0015]
【発明の実施の形態】以下、実施の形態に基づいて本発
明について詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.
【００１６】図１は本発明の一実施の形態の半導体装置
の製造工程図であり、図１において、１はゲート電極、
２はゲート酸化膜、３はシリコン酸化膜、４はＢＰＳＧ
膜、５は第１層目金属配線又は下部電極となるアルミニ
ウム膜、６はキャパシタ絶縁膜となるシリコン窒化膜、
７は上部電極となるアルミニウム膜、８はレジスト、９
はＰＥ−ＴＥＯＳ膜、１０は第２層目金属配線となるア
ルミニウム膜、１１は半導体基板、１２はロコス酸化膜
である。FIG. 1 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a gate electrode;
2 is a gate oxide film, 3 is a silicon oxide film, 4 is BPSG
Film 5, an aluminum film serving as a first-layer metal wiring or lower electrode, 6 a silicon nitride film serving as a capacitor insulating film,
7 is an aluminum film serving as an upper electrode, 8 is a resist, 9
Denotes a PE-TEOS film, 10 denotes an aluminum film serving as a second-layer metal wiring, 11 denotes a semiconductor substrate, and 12 denotes a LOCOS oxide film.
【００１７】まず、図１（ａ）に示すように、従来技術
に基づき、半導体基板１１にゲート酸化膜２を介してゲ
ート電極１を形成し、ソース／ドレイン領域（図示せ
ず）を形成する。次に、ＢＰＳＧ膜４を堆積させ、ソー
ス／ドレイン領域上のＢＰＳＧ膜４にコンタクトホール
を形成する。次に、このコンタクトホールにを埋設し、
エッチバックにより、コンタクトプラグ１３を形成す
る。First, as shown in FIG. 1A, based on a conventional technique, a gate electrode 1 is formed on a semiconductor substrate 11 via a gate oxide film 2, and a source / drain region (not shown) is formed. . Next, a BPSG film 4 is deposited, and a contact hole is formed in the BPSG film 4 on the source / drain region. Next, bury this contact hole,
The contact plug 13 is formed by etch back.
【００１８】次に、第１層目金属配線又は、キャパシタ
の下部電極となるアルミニウム膜５を膜厚６００μｍ程
度に形成する。次に、減圧ＣＶＤ法により、膜厚２０ｎ
ｍ程度のシリコン窒化膜６を形成し、更にスパッタ法に
より膜厚１５０ｎｍ程度のキャパシタの上部電極となる
アルミニウム膜７を形成する。Next, an aluminum film 5 serving as a first-layer metal wiring or a lower electrode of a capacitor is formed to a thickness of about 600 μm. Next, the film thickness of 20 n
A silicon nitride film 6 having a thickness of about m is formed, and an aluminum film 7 serving as an upper electrode of a capacitor having a thickness of about 150 nm is formed by a sputtering method.
【００１９】次に、図１（ｂ）に示すように、フォトリ
ソグラフィによるレジストをマスクとして、１層目金属
配線と、キャパシタ領域以外の金属配線材料（アルミニ
ウム膜５、７）及びシリコン窒化膜３をドライエッチン
グにより除去する。Next, as shown in FIG. 1B, using a photolithographic resist as a mask, the first-layer metal wiring, metal wiring materials (aluminum films 5 and 7) and silicon nitride film 3 other than the capacitor region are formed. Is removed by dry etching.
【００２０】次に、図１（ｃ）に示すように、フォトリ
ソグラフィによるレジストをマスクとして、キャパシタ
領域以外の金属配線材料（アルミニウム膜７）とシリコ
ン窒化膜３をドライエッチングで除去する。エッチング
ガスは、金属配線には、流量比を１：１としたＢＣｌ3
とＣｌ2とを、また、シリコン窒化膜には、流量比を
１：１としたＣＦ4とＣＨ3とを用いる。Next, as shown in FIG. 1C, using a resist formed by photolithography as a mask, the metal wiring material (aluminum film 7) and the silicon nitride film 3 other than the capacitor region are removed by dry etching. The etching gas is BCl 3 with a flow ratio of 1: 1 for the metal wiring.
And Cl 2, and CF 4 and CH 3 with a flow ratio of 1: 1 are used for the silicon nitride film.
【００２１】次に、図１（ｄ）に示すように、常圧ＣＶ
Ｄ法により、膜厚２５００ｎｍ程度のＰＥ−ＴＥＯＳ膜
９を形成し、ＣＭＰ法により膜厚５００ｎｍ程度研磨す
る。Next, as shown in FIG.
The PE-TEOS film 9 having a thickness of about 2500 nm is formed by the D method, and is polished by the CMP method to a thickness of about 500 nm.
【００２２】次に、フォトリソグラフィによるレジスト
をマスクとして、キャパシタの上部電極及び第１層目金
属配線と第２層目金属配線との間のヴィアホール領域の
ＰＥ−ＴＥＯＳ膜９をドライエッチングにより開口し、
ブランケット法により、ヴィアホール内にＷＦ6ガスを
用いてタングステン１４を埋設する。その後、スパッタ
法により、第２層目金属配線となるアルミニウム膜１０
を形成し、フォトリソグラフィによるレジストをマスク
としてドライエッチングによってアルミニウム膜１０の
パターニングし、第２層目金属配線を形成する。Next, using a resist formed by photolithography as a mask, the upper electrode of the capacitor and the PE-TEOS film 9 in the via hole region between the first-layer metal wiring and the second-layer metal wiring are opened by dry etching. And
Tungsten 14 is buried in the via hole using WF 6 gas by a blanket method. Thereafter, the aluminum film 10 serving as the second-layer metal wiring is formed by sputtering.
Is formed, and the aluminum film 10 is patterned by dry etching using a resist formed by photolithography as a mask to form a second-layer metal wiring.
【００２３】このように、本発明によれば、容量素子の
下部電極（アルミニウム膜５）と上部電極（アルミニウ
ム膜７）を金属導電性材料で構成することができ、電極
の絶縁膜側表面近傍の空乏層の形成がなく、容量値が電
圧依存性を持たない容量素子を形成することができる。As described above, according to the present invention, the lower electrode (aluminum film 5) and the upper electrode (aluminum film 7) of the capacitive element can be made of a metal conductive material, and the vicinity of the surface of the electrode on the insulating film side can be obtained. A depletion layer is not formed, and a capacitance element whose capacitance value does not have voltage dependency can be formed.
【００２４】[0024]
【発明の効果】以上、詳細に説明したように、本発明を
用いることにより、金属配線材料の下部電極と、その下
部電極上の所定部を含む領域に形成された絶縁膜と、そ
の絶縁膜上の所定部を含む領域に形成された金属配線材
料の上部電極とを有する容量素子を有する構成によるの
で、電圧依存性がなく、高精度フィルタ回路等に組み込
める容量素子を有する半導体装置を提供することができ
る。As described in detail above, by using the present invention, the lower electrode of the metal wiring material, the insulating film formed in the region including the predetermined portion on the lower electrode, and the insulating film Provided is a semiconductor device having a capacitance element having a capacitance element having an upper electrode of a metal wiring material formed in a region including an upper predetermined portion and having no voltage dependency and being incorporated in a high-precision filter circuit or the like. be able to.
【００２５】また、図２に示した従来のアナログキャパ
シタでは、電圧依存性が数千［ｐｐｍ／Ｖ］であるのに
対して、図１に示した本発明の構成のアナログキャパシ
タでは電圧依存性を数十［ｐｐｍ／Ｖ］まで低減可能で
あるため、高精度で電圧依存性のないフィルタ回路や積
分回路等が形成可能となる。The voltage dependency of the conventional analog capacitor shown in FIG. 2 is several thousands [ppm / V], whereas the voltage dependency of the analog capacitor of the present invention shown in FIG. Can be reduced to several tens [ppm / V], so that a filter circuit, an integrating circuit, and the like with high accuracy and no voltage dependency can be formed.
【００２６】更に、配線層にてキャパシタを形成してい
るため、特開平５−９５０８２号公報に開示された従来
技術のように、素子分離領域上に形成する必要はなく、
層間絶縁膜を上に形成することができ、チップサイズの
縮小が可能となる。Further, since the capacitor is formed by the wiring layer, it is not necessary to form the capacitor on the element isolation region as in the prior art disclosed in Japanese Patent Application Laid-Open No. 5-95082.
An interlayer insulating film can be formed thereon, and the chip size can be reduced.
【図１】本発明の一実施の形態の半導体装置の製造工程
図である。FIG. 1 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.
【図２】従来のアナログキャパシタを有する半導体装置
の製造工程図である。FIG. 2 is a manufacturing process diagram of a semiconductor device having a conventional analog capacitor.
１ ゲート電極 ２ ゲート酸化膜 ３ シリコン酸化膜 ４ ＢＰＳＧ膜 ５ 下部電極となるアルミニウム膜 ６ キャパシタ絶縁膜となるシリコン窒化膜 ７ 上部電極となるアルミニウム膜 ８ レジスト ９ ＰＥ−ＴＥＯＳ膜 １０ ２層目金属配線となるアルミニウム膜 DESCRIPTION OF SYMBOLS 1 Gate electrode 2 Gate oxide film 3 Silicon oxide film 4 BPSG film 5 Aluminum film used as a lower electrode 6 Silicon nitride film used as a capacitor insulating film 7 Aluminum film used as an upper electrode 8 Resist 9 PE-TEOS film 10 Second metal wiring Aluminum film
Claims (2)
た半導体基板上に第１の層間絶縁膜を形成する工程と、 上記第１の層間絶縁膜の上記拡散領域上にコンタクトホ
ールを形成し、該コンタクホール内に導電性プラグを埋
設する工程と、 上記第１の層間絶縁膜上に、上記コンタクトプラグと電
気的に接続された下部電極となる金属膜とキャパシタ絶
縁膜となる絶縁膜と上部電極となる金属膜とを順次形成
する工程と、 キャパシタ形成領域及び配線形成領域をマスクして、上
記上部電極及び下部電極となる金属膜と上記絶縁膜とを
除去する工程と、 キャパシタ形成領域のみをマスクして、上記上部電極と
なる金属膜及び上記絶縁膜を除去する工程と、 全面に第２の層間絶縁膜を形成し、該第２の層間絶縁膜
の所定の位置に上記キャパシタの上部電極又は下部電極
となる金属膜表面が露出するようにコンタクトホールを
形成し、該コンタクトホール内に導電性プラグを埋設す
る工程と、 上記第２の層間絶縁膜上に配線材料を形成し、所定の形
状にパターニングし、上記導電性プラグを介して、上記
金属膜と電気的に接続された配線を形成する工程とを有
することを特徴とする、半導体装置の製造方法。A step of forming a first interlayer insulating film on a semiconductor substrate on which a semiconductor element having a diffusion region is formed; and forming a contact hole on the diffusion region of the first interlayer insulating film; Burying a conductive plug in the contact hole; and forming, on the first interlayer insulating film, a metal film serving as a lower electrode electrically connected to the contact plug, an insulating film serving as a capacitor insulating film, and an upper portion. A step of sequentially forming a metal film to be an electrode; a step of masking a capacitor formation region and a wiring formation region to remove the metal film to be the upper electrode and the lower electrode and the insulating film; Removing the metal film to be the upper electrode and the insulating film by forming a mask, forming a second interlayer insulating film on the entire surface, and forming the second interlayer insulating film at a predetermined position of the second interlayer insulating film. Forming a contact hole such that the surface of the metal film serving as a part electrode or a lower electrode is exposed, and burying a conductive plug in the contact hole; and forming a wiring material on the second interlayer insulating film; Patterning into a predetermined shape and forming a wiring electrically connected to the metal film via the conductive plug.
た半導体基板上に第１の層間絶縁膜を形成する工程と、 上記第１の層間絶縁膜の上記拡散領域上にコンタクトホ
ールを形成し、該コンタクホール内に導電性プラグを埋
設する工程と、 上記第１の層間絶縁膜上に、上記コンタクトプラグと電
気的に接続された下部電極となる金属膜とキャパシタ絶
縁膜となる絶縁膜と上部電極となる金属膜とを順次形成
する工程と、 キャパシタ形成領域と下層配線形成領域とをマスクし
て、上記上部電極及び下部電極となる金属膜と上記絶縁
膜とを除去する工程と、 キャパシタ形成領域のみをマスクして、上記上部電極と
なる金属膜及び上記絶縁膜を除去し、下層配線を形成す
る工程と、 全面に第２の層間絶縁膜を形成し、該第２の層間絶縁膜
の所定の位置に上記キャパシタの上部電極及び上層配線
と接続される下層配線となる金属膜表面が露出するよう
にコンタクトホールを形成し、該コンタクトホール内に
導電性プラグを埋設する工程と、 上記第２の層間絶縁膜上に配線材料を形成し、所定の形
状にパターニングし、上記導電性プラグを介して、上記
キャパシタの上部電極又は上記下層配線に電気的に接続
された上記上層配線を形成する工程とを有することを特
徴とする、半導体装置の製造方法。A step of forming a first interlayer insulating film on a semiconductor substrate on which a semiconductor element having a diffusion region is formed; and forming a contact hole on the diffusion region of the first interlayer insulating film; Burying a conductive plug in the contact hole; and forming, on the first interlayer insulating film, a metal film serving as a lower electrode electrically connected to the contact plug, an insulating film serving as a capacitor insulating film, and an upper portion. Forming a metal film to be an electrode sequentially; removing a metal film to be an upper electrode and a lower electrode and the insulating film by masking a capacitor formation region and a lower wiring formation region; and forming a capacitor. Forming a lower layer wiring by removing only the region and masking the metal film serving as the upper electrode and the insulating film; forming a second interlayer insulating film over the entire surface; Predetermined Forming a contact hole such that a surface of a metal film serving as a lower wiring connected to an upper electrode and an upper wiring of the capacitor is exposed, and burying a conductive plug in the contact hole; Forming a wiring material on the interlayer insulating film, patterning the wiring material into a predetermined shape, and forming the upper layer wiring electrically connected to the upper electrode or the lower wiring of the capacitor via the conductive plug; A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30654598A JP3623377B2 (en) | 1998-10-28 | 1998-10-28 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30654598A JP3623377B2 (en) | 1998-10-28 | 1998-10-28 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000133708A true JP2000133708A (en) | 2000-05-12 |
| JP3623377B2 JP3623377B2 (en) | 2005-02-23 |
Family
ID=17958337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30654598A Expired - Fee Related JP3623377B2 (en) | 1998-10-28 | 1998-10-28 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3623377B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6603163B2 (en) | 2000-12-15 | 2003-08-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with capacitor and method of manufacturing thereof |
| US6927124B2 (en) | 2002-06-12 | 2005-08-09 | Oki Electric Industry Co., Ltd. | Method of manufacturing semiconductor device |
| JP2007173437A (en) * | 2005-12-21 | 2007-07-05 | Fujitsu Ltd | Electronic component |
-
1998
- 1998-10-28 JP JP30654598A patent/JP3623377B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6603163B2 (en) | 2000-12-15 | 2003-08-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with capacitor and method of manufacturing thereof |
| US6927124B2 (en) | 2002-06-12 | 2005-08-09 | Oki Electric Industry Co., Ltd. | Method of manufacturing semiconductor device |
| JP2007173437A (en) * | 2005-12-21 | 2007-07-05 | Fujitsu Ltd | Electronic component |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3623377B2 (en) | 2005-02-23 |
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