JPS6020908B2 - Method for manufacturing MOS dual polycrystalline integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing integrated circuits using double polycrystalline silicon layers.

In some MOS integrated circuits, double polycrystalline silicon layers are used in the construction of many routing structures.

Typically, the upper or second polysilicon layer is separated from the silicon substrate by an oxide layer from the upper or second polysilicon layer. These layers are used in memory devices that use floating gates, capacitors, interconnect lines, etc.
It is manufactured using known photolithography technology. The technology is currently used in commercially available charge-coupled devices and programmable memory devices. In some of these dual polycrystalline integrated circuits, it is desirable to have components made from the upper layer aligned with layers made from the lower layer.

For example, when the upper and lower layers are used to make gates in a field effect device, alignment between the gates is important. However, it is difficult to perform such positioning using the method of manufacturing a subordinate column. The manner in which conventional methods indirectly solve this scale alignment problem will be explained later with reference to FIG. The method of the invention is used in the manufacture of MOS integrated circuits using double polycrystalline silicon layers.

forming a first polycrystalline silicon layer on the substrate;
A second polycrystalline silicon layer is formed over the layer. The method of the present invention forms circuit structures in a first silicon layer that are aligned with circuit structures in a second silicon layer. First, a circuit structure is formed in a second silicon layer, and then a circuit structure is formed in a first silicon layer.
The structure is used as a masking member to etch the silicon layer. The etched structures in the first silicon layer will then register with the structures in the second silicon layer. The method of the invention allows the creation of aligned polycrystalline silicon structures from first and second silicon layers.

For example, if the structures are the top and bottom gates of a field effect device, source and drain regions can be created in the substrate that align with the two gates. In the following description, the present invention will be described by taking as an example the fabrication of a floating gate memory device in which the first and second layer structures are gates. However, the method can also be used to construct other integrated circuit components and devices, such as capacitors, interconnect lines, and the like. Further, in the following description, the method of the present invention will be explained using a double polycrystalline silicon layer as an example, but the present invention is also useful for circuit configurations using two or more polycrystalline silicon layers. As is clear from the description of the method of the present invention that follows, in order to avoid complicating the explanation, explanations of matters well known in this technical field are omitted, and even matters that are considered to be impractical may be used to carry out the present invention. It should be understood that additional material is included that is not necessary and is merely convenient to assist in explaining the invention.

First, the prior art will be specifically explained with reference to FIG.

A secondary MOS dual polycrystalline silicon floating gate device is shown above the P-type substrate 10. Ions are implanted into the top surface of the substrate 10 to form a host region 11 for a floating gate device. This device has the upper surface of the substrate 10 and the floating gate 1
6 and a gate oxide 14 disposed between the gate oxide 14 and the gate oxide 14 . This gate is composed of polycrystalline silicon. In manufacturing this device, an oxide layer and a polycrystalline silicon layer are formed on the top surface of the substrate. Gate 16 and oxide layer 14 are fabricated from these layers using known photolithographic techniques. A lightly doped N-type region 21 is then formed in alignment with gate i6 and oxide layer 14. Thereafter, another polycrystalline silicon layer and an oxide layer are formed over the floating gate 16 and then etched to form the oxide layer 18 and the upper or control gate 20. After the control gate 20 is created, an N-type region 22 is formed within region 21 and aligned with the control gate. Ideally gate 16
and 20 so that an N-type region can be created aligned with those two gates.

However, because the tolerances for aligning the mask for making gate 20 with gate 16 are very small,
It is difficult to do the above. Gates 20 and 16
are not aligned, requiring separate doping steps to form the source and gate regions of this device. Furthermore, the area of gate 20 is larger than the area of gate 16, thereby increasing the area of the device. As will be explained later, when the device shown in FIG. 1 is manufactured by the method of the present invention, the positions of the control gate and floating gate are aligned, so no doping step is required to create the source region and drain region. One time is enough.

Furthermore, since the area of the element becomes narrower, it is possible to fabricate a higher density element. Next, an embodiment of the present invention will be described with reference to FIGS. 2 to 7. In Figure 2,
25 is a P-type silicon substrate, on the top surface of which a silicon oxide layer 27 is grown. A first polycrystalline silicon layer 29 is formed on the top surface of this layer 27. In the example described here, the silicon layer 29 is heavily doped with an n-type impurity such as phosphorous using a conventional diffusion method. A second oxide layer 31 is grown on the exposed surface of the first polycrystalline silicon layer 29 . For example, the thickness of oxide layers 27 and 31 is 500-1
000A, and the thickness of the first silicon layer 29 is 4500A.
~6000A. The substrate shown in FIG. 2 and the layers formed thereon are the same as the substrate 10 shown in FIG. are equivalent to each other. FIG. 3 shows the state at the time when a second polycrystalline silicon layer 33 is formed on the upper surface of the oxide layer 31 and then an oxide layer 35 is grown on the upper surface of the silicon layer 33.
The state of the element shown in FIG. 2 is shown.

These layers can be formed using conventional techniques. The formation of these layers on top of oxide layer 31 was described in connection with the device shown in FIG. Different from traditional methods. It will be appreciated that FIGS. 2-7 only show one cross-section of the element. First polycrystalline silicon layer 29 can be masked and etched in other parts of substrate 25 (such as between devices) so that layer 29 is not coextensive with layer 33. 2 through 7 mainly show the gate region of the floating gate device. If the first silicon layer 29 is etched, an oxidation step is required to insulate those etched regions. Therefore, the oxide layer 31 shown in FIG.
If layer 31 of FIG. 3 is regrown, it can be a different oxide. After forming the oxide layer 35, a masking member is fabricated in that layer.

This member is shown in FIG. 4 as masking member 35a. This masking member 35a conforms to a predetermined pattern and can be made using known photolithography techniques. Following the formation of this masking member, a known silicon etchant is applied to the polycrystalline silicon layer 33 to etch the layer, and as shown in FIG.
The gate 33a, that is, the upper gate 33a is made. After forming the second gate 33a, the exposed portion of the oxide layer 31 and the masking member 35a are removed using a known oxide etchant.

The first polycrystalline silicon layer is then etched to form a lower gate 29a as shown in FIG. During this etching step, upper gate 33a functions as a masking member so that lower gate 29a is aligned with upper gate 33a as shown in FIG. In the embodiment described here, a selective etchant is used for etching the silicon layer 29. This etchant distinguishes between doped polycrystalline silicon and undoped polycrystalline silicon, removes only the doped silicon, and leaves the upper gate 33a almost intact. The structure shown in FIG. 5 is the result of such selective etching and includes a lower gate 29a, an upper gate 33a, and a gate oxide 31a located intermediate the gates. In this example, the etchant includes hydrofluoric acid, nitric acid, and acetylic acid. This etchant performs the necessary selection of materials and etches only polycrystalline silicon doped with phosphorus. Although in this embodiment only the lower polycrystalline silicon layer is doped and the upper polycrystalline silicon layer is undoped, other combinations of doped and undoped layers may also be employed. In that case, the upper layer is first etched to form a polycrystalline silicon structure, and this structure is used as a masking member for etching the lower layer. For example, the upper layer can be doped with boron (P-type) while the lower layer is undoped. At that time, hot KOH was used to selectively etch the underlying undoped polycrystalline silicon layer.
can be used. This special etchant has little effect on the upper doped silicon layer. This etchant can also be used when the lower layer is lightly doped and the upper layer is highly doped. In some structures, the lower layer may be doped with P-type impurities and the upper layer may be doped with N-type impurities.

An etchant consisting of CrC3, hydrofluoric acid and water (SIRTL) can be used for etching the lower layer.

If the structure shown in FIG. 5 is to be used as a floating gate memory device, holes 38 are provided through oxide layer 27 near gates 29a and 33a.

A well is then formed within the hole 38 by implantation of boron ions. Next, an oxidation driver step diffuses the impurities in this well beyond the peripheral wall of the hole 38, and the sixth
A P-type well 40 shown in the figure is formed. During this oxidation driver step, oxide 42 is formed as shown in FIG. Following the formation of P-type well 40, a pair of holes 44 passing through oxide layer 27 are formed near gates 29a and 33a.

Then an N-type impurity such as phosphorus is used to
5 and a drain region 46 are formed. Holes 38 and 40, P-type well 40, source region 45, and drain region 46 can be formed by a known MOS processing method. For the embodiment shown in FIGS. 6 and 7, a P-type well 40 may be used, but the substrate 25 may be more heavily doped or the top surface of the substrate may be implanted with ions to host the device. Such wells are not required for the formation of memory elements such as those that form .

For example, in the device shown in FIG. 1, ions were implanted into the top surface of the substrate without using a P-type well (region 11). Using the method of the present invention to fabricate the device shown in FIG. 7 provides several advantages over the conventional device shown in FIG.

First, the performance of the device shown in FIG. 1 is independent of mask alignment associated with upper gate fabrication. The alignment obtained by the method of the present invention provides even better performance. Furthermore, in devices made by the method of the present invention, the top gate is no larger than the bottom gate, so the device dimensions are reduced by 4 mm. To correct for mask alignment errors, the upper gate of the device shown in FIG. 1 is larger than the lower gate. A programmable read-only memory can be constructed by combining a plurality of elements shown in FIG.

In that case, the memory is a 1-chip digital computer.
It forms part of the evening. In this embodiment, a P-type well such as well 40 is not used, and the host region of the device is implanted.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a MOS floating gate device in which one silicon layer structure is misaligned with a second silicon layer structure made in a conventional manner using a double layer polycrystalline silicon structure; FIG. FIG. 3 is a cross-sectional view of the substrate on which the first polycrystalline silicon layer is formed; FIG. 3 is a cross-sectional view of the substrate shown in FIG. 3 is a cross-sectional view of the substrate of FIG. 3 having a first structure made by photolithography in a second silicon layer, and FIG.
A cross-sectional view of the substrate of FIG. 4 with the first silicon layer being etched using the first structure of the layers as a masking member; FIG. FIG. 7 is a cross-sectional view of the substrate of FIG. 6 with source and drain regions formed therein. 10,25...Substrate, 11...Host region, 14,18,27,31,35,42...Oxide layer, 16...Floating gate, 20,33a・
... Upper gate, 21, 22... N-type region, 29, 33... Lower polycrystalline layer, 35a...
...Masking section, 29a ... Lower gate, 38 ... Hole, 40 ... Impurity well. Gosha Z N'Kyo 2 Rikikyo 3 Eimitsu〆kugishu, 5 Eta. 6 Shoes evening

Claims (1)

[Claims] 1. A step of forming a first polycrystalline silicon layer on a silicon substrate, a step of forming an insulating layer on this first silicon layer, and a step of forming a second polycrystalline silicon layer on this insulating layer. forming a crystalline silicon layer, one of the first and second silicon layers being doped, and etching the second silicon layer and the insulating layer to form a structure with a predetermined pattern. using the structure as a mask to deposit onto the structure and the first silicon layer an etchant that selectively etches the first silicon layer depending on the doping-based etching selectivity; A method of manufacturing a MOS dual polycrystalline integrated circuit, further comprising: forming a dual polycrystalline silicon structure on the substrate. 2. The method of claim 1, wherein the substrate includes a first oxide layer. 3. The method according to claim 2, wherein the first silicon layer is doped with phosphorus. 4. The method according to claim 2, wherein the insulating layer includes a second oxide layer. 5. The method according to claim 1, wherein the second silicon layer is doped with boron. 6. A method of manufacturing a MOS floating gate memory on the silicon substrate according to the method according to claim 4, comprising the steps of doping the first silicon layer and doping the second silicon layer. forming a gate mask member, the etching step including etching the second silicon layer to form an upper gate, and removing exposed portions of the second oxide layer. further comprising, the etchant selectively etching the first silicon layer to form a lower gate, the upper gate functioning as a mask during etching of the lower gate, such that the lower gate is A method characterized in that the upper gates are aligned. 7. The method according to claim 6, including the step of forming a source region and a gate region in a portion of the substrate near the gate. 8. The method according to claim 6, wherein the source region and drain region are comprised of n-type regions.