JPS6020892B2 - semiconductor element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to the formation of a protective film on the surface of a semiconductor device.

In general, the surface of a silicon planar semiconductor element is coated and protected with a Si02 film to stabilize it, but it is difficult to form a completely clean Si02 film using normal device manufacturing methods, and it is often difficult to form a completely clean Si02 film. Certain impurities are introduced.

In particular, when the impurity is a permeable substance or an ionic substance, the Sj surface directly under the Si02 film containing the impurity is polarized, charges are induced there, and a depletion layer or channel layer is likely to be formed. This adversely affects the electrical characteristics of the device. For example, for a silicon planar NPN transistor, Si02 is coated on the P-type base surface.
When the impurity enters the film, a negative charge is induced on the P-type base surface directly below the Si02 pus, and a depletion layer or N
type channel layer appears and the recombination current on the surface increases,
For example, low current hFE etc. are reduced. Also, taking a PNP transistor as an example, SiQ can be coated on the P-type collector surface.
Negative charges are induced on the collector surface by impurities in the film, and an N-type channel layer appears there, and in particular, a reverse channel current between the collector and the base appears. All of the above examples are well-known phenomena in which negative charges are transferred to the P-type silicon surface due to positive charge components in the SiQ film, and conventional measures such as phosphor glass layers have been used as countermeasures. Various methods have been used, such as getting positive ions.

However, on the other hand, there have been few reports on the phenomenon in which positive charges are induced on the n-type silicon surface by negative charge components in the Si02 matrix. However, according to the inventor's investigation, there is a good possibility that a negative charge component will be introduced into the Si02 film during the device manufacturing process, and this negative charge component will form a P-type channel layer on the n-type silicon surface directly under the Si02 film. It was clearly recognized that That is, this minor charge component can be removed by treating the surface of the device with an aqueous solution containing ammonia before and after forming a general Si02 film, or by applying metal oxides such as aluminum oxide, titanium oxide, tantalum oxide, etc. to the general Si02 surface. Due to the presence of ions, a negative charge component is introduced into the Si02 layer, and a P-type channel layer is formed on the surface of the N-type silicon. For example, in the case of a silicon NPN type transistor element, when a P type channel layer is formed on the N type collector surface directly under the SiO2 layer containing the negative charge component, the channel layer reaches the scribe window for element division and the collector base. This significantly increases the reverse channel current, or leakage current. In particular, this channel layer is formed more easily as the specific resistance on the collector side is higher and as the Si02 film thickness is thinner.

The object of the present invention is to prevent the adverse effects of a P-type channel layer formed on the surface of N-type silicon.

The structure of the present invention is to first coat the N-type silicon surface with Si0
2 film is partially or almost completely removed, and then a very low-grade silicon oxide film containing a positive charge component is formed on the exposed Si surface by heat treatment at a low temperature in an oxidizing atmosphere. It is characterized in that the P-type channel layer is blocked by inducing negative charges on the N-type silicon surface directly under the iQ film due to the positive charge component contained in the Si02 film. Therefore, the N-type silicon surface has a structure including a low-grade silicon oxide film formed by low-temperature heat treatment containing positive components. Here, the term "low-grade silicon oxide film" refers to a low-grade silicon oxide film containing a positive charge component, which is formed by performing low-temperature heat treatment at room temperature or below 450 pm, and is a general regular silicon oxide film. It is not an oxide film (SiO2 concentration), and oxygen is deficient and S
Since compounds such as i○, Si20tSi203 are formed, the stoichiometric composition changes and the oxygen space (Vaca
This refers to a silicon oxide film in a state in which there are a large number of unpaired electrons (ncy) or in a state in which there are many unpaired electrons in which Si-0 bonds are broken at various places. According to the present invention, for example, in the production of an NPN transistor element, SiO
By forming two films, it is possible to stabilize the P-type base surface, and as a result, it is possible to improve the level of low-current hF ears, low-frequency noise levels, etc., and to further stabilize the P-type channel formed on the N-type collector surface. By locally removing the layer, it is possible to increase the effect of eliminating the channel current in the opposite direction between the collector and the base.Therefore, the manufacturing yield, quality, and reliability of semiconductor devices are further improved.Next Now, the present invention will be explained based on specific embodiments with reference to the drawings.

In this embodiment, a case will be described in which the present invention is applied to a planar type NPN transistor.

Figure 1 shows an N-type emitter diffusion layer 1, a P-type base diffusion layer 2,
N-type collector layer 3 "NPN with ripely grown Si02 film 4, emitter electrode 5, and base electrode 6 formed by a known method.
A cross-sectional view of a transistor element is shown. In addition, FIG. 1 shows a scribe window 8 exposing a silicon surface for facilitating device division, and a diffusion layer 7 which is conveniently formed in the scribe window 8 during the device manufacturing process.

Since there is no particular need to form a junction in the diffusion layer 7, the irregular diffusion layers 7 of P type and N type are formed at the same time as the emitter and base diffusion from the scribe window of the same size. Therefore, the scribe window 8 is almost short-circuited with the collector layer 3. FIG. 2 shows a state in which when the Si02 film 4 on the collector side of the transistor element formed as shown in FIG. 1 contains a negative charge component, positive charges are induced on the N-type collector surface and a P-type channel layer 9 is formed. show.

That is, in FIG. 2, Si02 containing a negative charge component
The membrane can be treated, for example, as a pretreatment for diffusion, oxidation, and electrode formation.
Commonly used cleaning liquids such as ammonia water (30
% aqueous solution) and 2 parts of hydrogen peroxide (30% aqueous solution).
It is formed by using a mixed aqueous solution of 1 part and 6 parts of pure water, maintaining the temperature in the aqueous solution at 70 qo, and washing with 2 parts of HZ ultrasonic waves applied. Further, in order to be easily influenced by the Si02 film 4 containing the negative charge component, an epitaxial layer having a relatively high resistivity of 40 arc was used as the collector layer, and the SiQ concentration was formed to be 8000A.

Note that there are many transistor elements formed in this manner, not only in this embodiment. As shown in Figure 2,
There is a channel layer 9 directly under the Si02 film 4 covering the N-type collector layer 3, and when the channel layer 9 reaches the scribe window 8, a collector-base reverse current is formed from the collector layer 3 to the scribe window 8. It flows into the base region 2 through the irregular diffusion layer 7 and further through the channel layer 9, so that it increases instantaneously.

As mentioned above, this phenomenon is caused by the negative charge component in the Si02 film. On the other hand, when a SiQ film containing a negative charge component is coated on the P-type base surface, this Si02
Since the film 4' has a direction that induces negative charges on the base surface, the formation of a depletion layer, an inversion layer, etc. on the surface is prevented, so recombination on the surface is prevented compared to a normal Si02 film containing a positive charge component. The current is significantly reduced, and noise levels etc. are significantly improved with low current hFE and low frequency. Therefore, the transistor element shown in FIG. 2 has further improved device characteristics only by erasing the channel layer 9 on the collector side. The present invention is carried out by a method in which the channel layer 9 is erased midway to cut off the current path in the reverse direction between the collector and the base.

That is, as an embodiment of the present invention, as shown in FIG. 3, the Si02 film 4 coated on the collector layer 3 is selectively removed in a ring shape using a hydrofluoric acid aqueous solution, and then exposed to an oxidizing atmosphere at room temperature or below 45,000 ℃. For example, a low grade oxide film 11 of 10 to 200 A is selectively formed on the yielding window 10 in air. In forming the oxide film, a lower grade oxide film 12 is inevitably formed on the scribe window 8, but with a film thickness of this level, there is no problem at all during scribing. As long as the lower oxide film 11 is formed through this process, it will definitely contain a positive charge component sufficient to induce negative charges near the surface of the N-type collector layer in contact with the lower oxide film 11.
Negative charges are induced on the N-type collector surface directly under the i02 film 11, and the P-type channel layer 9 is completely erased on this surface. Therefore, the reverse current path is completely cut off at the same time. Next, as another embodiment of the present invention, as shown in FIG.
The collector surface 13 is exposed by removing almost the entire film 9.
Another method is to prevent the formation of the channel layer 9 by forming the low-grade silicon oxide film 14 by low-temperature heat treatment at 450° C. or lower, as in the previous embodiment, and to completely cut off the reverse current path.

According to the device surface structure shown in FIGS. 3 and 4 of this embodiment, not only the collector-base reverse current is reduced, but also the recombination current on the base surface is reduced as described above, thereby improving all device characteristics. As a result, the manufacturing yield, quality, reliability, etc. of semiconductor devices are significantly improved.

As explained above, the present invention involves partially or almost completely removing the Si02 film covering the N-type silicon surface, and forming a low-grade silicon oxide film containing a positive charge component on the exposed Si surface. It is characterized by erasing the P-type channel layer induced on the N-type silicon surface,
In this embodiment, an NPN transistor is taken as an example, but it goes without saying that the present invention is not limited to this transistor, but can be applied to any semiconductor device such as a diode or an integrated circuit as long as it accomplishes the purpose.

Furthermore, in this example, Si02 containing a negative charge component
Although an aqueous solution containing ammonia water was used to form a film,
The method is not necessarily limited to this method, and other methods such as the application of a compound containing an ammonia group or the application of a metal oxide are also conceivable.

Furthermore, it is not out of the question that the method for erasing a P-type channel layer according to the present invention can be easily applied to protective films other than the Si02 film containing a negative charge component as described in this embodiment.

[Brief explanation of the drawing]

3 to 4 are cross-sectional views for explaining the manufacturing process of the surface of a semiconductor device according to an embodiment of the present invention, and FIGS. 3 and 4 show typical device surface structures of the present invention. FIG. 1... Emitter diffusion layer, 2... Base diffusion layer, 3... Collector layer, 4, 4'... Mature silicon oxide film, 5, 6...・Element electrode layer, 7...
...Diffusion layer from the scribe window, 8...Scribe window, 9...P-type channel layer, 10.
...Ring window, 11, 12, 14...
Low grade silicon oxide film, 13... Collector surface. Graduation 1 figure 2 figure 3 Ryuta 4 figure

Claims (1)

[Claims] 1. A semiconductor element having an N-type silicon layer and a silicon oxide film having a negative charge component on the surface of the silicon layer formed on the surface of a semiconductor substrate, wherein the surface of the N-type silicon layer of the semiconductor substrate is A semiconductor device characterized by a ring-shaped or almost entirely formed low-grade silicon oxide film containing a positive charge component.