JPS6196761A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the current amplification degree and breakdown- withholding capability by a method wherein impurity concentration in a base region is eventually lowered without reducing the quantity of impurity to be diffused during a base region forming process. CONSTITUTION:On a first semiconductor layer 1a on a substrate 1, a silicon oxide film 2 is formed, therein an opening 2a is provided by the selective removal method. A boron-doped oxide film 3 is formed to cover the opening 2a and the remaining silicon oxide film 2. A heating process follows whereby the impurity (boron) in the film 3 is diffused through the opening 2a into the semiconductor layer 1a for the formation of a P type low-concentration first region 4 (base region). The oxide film 3 is subjected to elective removal and the exposed first region 4 is removed by etching for the formation of a recess 4a. An impurity (phosphorus) is caused to be diffused through the inside walls of the recess 4a into a section in the first region 4 for the formation of an N type second region 5 (emitter region), when the impurity diffusion concentration from the recess walls is reduced and an emitter region 5 is formed wherein a high-concentration region 5a is contained in a low-concentration region 5b.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, such as a transistor, and more particularly to an improved method for improving current amplification factor and breakdown protection.

[Technical background of the invention and its problems]

An example of a conventional method for manufacturing an NPN transistor will be explained with reference to the drawings.

First step As shown in FIG. 2(a), the first N-type semiconductor (N)f4)la and high? A silicon substrate 1 consisting of a1 degree N-type semi-coherent layer (N+ layer) lb is prepared.

Then, a silicon oxide film 2 is formed on one main surface of the first semiconductor layer 1a.

A boron-doped oxide film 3 is deposited on the opening 2a and the remaining silicon oxide film 2. Next, by performing a heat treatment, the impurity (boro/) in the film 3 is diffused into the semiconductor layer 1a through the opening 2a, thereby forming a P-type base region 4.

Third step As shown in FIG. 2(c), the film 3 is selectively removed to form an opening 3a. Then, a phosphorus-doped oxide film 6 is formed over the opening 3a and the remaining film 3. Next, by performing a heat treatment, the impurity (phosphorus) in the film 6 is diffused into the space region 4 through the opening 3a, thereby forming an N-type emitter region 5.

Fourth step As shown in FIG. 2 fd), an open lower b for the base electrode and an open lower b for the emitter electrode are formed on the film 3 and the film 6 so that a part of the base region 4 and a part of the emitter region 5 are exposed. An open lower e is formed.

5th step As shown in FIG. 2(e), a base electrode 8b and an emitter electrode 8e are formed through the entire seven parts of the open lower b+ described above, and a high concentration N-type semi-abrasive body layer (N+ layer) lb
K forms the collector electrode 8c.

In order to improve the current amplification factor of such a conventional transistor/dimetal, there may be a method of lowering the base impurity concentration, a method of increasing the emitter impurity concentration, etc.

However, in order to lower the base impurity level, it has been necessary to reduce the amount of diffusion of impurities. Such low concentration diffusion is difficult to control and causes variations in the impurity concentration within the base, which in turn causes variations in the current amplification factor.

Furthermore, if the amount of diffusion of impurities is increased in order to increase the emitter impurity concentration, the crystal structure will be disrupted and defects will increase, or the impurities will be partially diffused deeply, resulting in an increase in leakage current.

In order to improve the breaking strength, there are conventional methods such as using a resistive material in the base electrode and emitter electrode.
According to such a method, a power loss occurs due to the grinding pile, which deteriorates the characteristics in the forward direction.

[Purpose of the invention]

The present invention solves the above-mentioned conventional problems, and ultimately lowers the impurity concentration in the base region without reducing the amount of diffusion of impurities for forming the base region in the diffusion process, improves the current amplification factor, and improves the breakdown strength. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can also improve the performance.

[Summary of the invention]

The present invention provides a first conductivity type first conductivity type to achieve the above object.
A second conductivity type impurity is diffused over the whole surface of the semiconductor layer to form a second conductivity type impurity.
A step of forming a first region of a conductivity type, a step of etching away a part of the surface of the first region to form a recess of a predetermined depth, and removing an impurity of the first conductivity type from an inner wall of the recess.
introducing into the region to form a second region of the first conductivity type;
A method for manufacturing a semiconductor device, comprising the step of lapping and removing the main surface to a depth of the bottom surface of the recess.

[Embodiments of the invention]

An example of manufacturing an NPN transistor by the method according to the present invention will be described with reference to the drawings.

First step As shown in FIG. 1(a), an N-type first semiconductor 1n(N/1)la and a highly concentrated IiN-type semiconductor layer (N+ layer)
A silicon oxide film 2 having a thickness of about 3 μm is formed on the first semi-dedicated layer 1a.

Second step As shown in FIG. 1 (bl), the silicon oxide film 2 is selectively removed to form an opening 2a.
A polo/doped oxide film 3 is deposited on the silicon oxide film 2 and the remaining silicon oxide film 2. Next, by performing a heat treatment, the impurity (boro/) in the film 3 is diffused into the semiconductor layer 1a through the opening 2a, thereby forming a P-type low # degree first region (base region) 4. This base region 4 is formed to have a depth of about 30 μm and a surface impurity concentration of about IX 10 ”an-3.

Third step As shown in FIG. 1(C), the oxide film 3
Select and remove the first one from here. A section of the area surface is misted. Next, one section of the exposed first region is removed by etching to form a recess 4a with a depth of about 10 μm.

The recess 4a is formed, for example, by immersion in an etching solution made of a mixture of butic acid and nitric acid for 10 to 15 minutes.

4th step As shown in FIG.
A second mold region (emitter region) 5 is formed to have a depth of about 10 μm and a surface impurity concentration of about 1×10 2 DEG crn-3.

At this time, the concentration of impurity diffused from the sidewall of the recess is reduced, and an emitter region 5 is formed in which the low concentration region 5b encompasses the high concentration region 5a. Note that this diffusion of impurities is caused by, for example, P
Used as an impurity evaporation source for diffusion with OCl2 (sulfolyl chloride). -@5 process Figure 1 (e
), the surface of the first semiconductor layer 1a on which the base region 4 is formed is removed by a lapping process to the depth of the bottom surface of the recess 4a. After that, the surface is lightly etched using an etching solution containing a mixture of butic acid and pox acid.

As a result, a portion near the surface of the base region having a high impurity concentration is removed, so that the surface impurity concentration of the base region is substantially reduced.

Sixth Step As shown in FIG.
is formed, and then a phosphorus-doped oxide film 10 serving as a passivation film is deposited.

Seventh Step As shown in FIG. 1(g), an open lower b for the base electrode and an open lower b for the emitter electrode are formed in the films 9 and 10 so that a part of the base region and a part of the emitter region are exposed. Forms lower e.

8th step As shown in FIG. 1 (hl), a base electrode 8b and an emitter electrode 8e are formed through the open lower b and 7e, and a collector electrode 8C is formed on the high concentration N-type semiconductor layer (N+ layer) lb. Form the adhesion.

The results of comparing the characteristics of the transistor manufactured by the above method and the conventional transistor are shown in FIGS. 3 to 5. Here, curves X and Y indicate the characteristics of transistors according to the method of this embodiment and the conventional method, respectively.

FIG. 3 shows the relationship between the collector-emitter breakdown voltage vsag and the DC current increase rate hFB.

As can be seen from this figure, the breakdown voltage (curve X
) is larger than the conventional one (curve Y), and the withstand voltage is improved. This is because the portion of the base region near the surface where the impurity concentration is high is removed by etching, so that the substantial impurity concentration of the base region is reduced and the depletion region is extended widely.

FIG. 4 shows the relationship between the base-emitter voltage change (ΔVBE) measured by the ΔV'Bg method (transient thermal resistance measurement method) corresponding to the collector-base applied voltage boil.

The ΔVBE method is a method of investigating transistor destruction caused by secondary breakdown between the collector and emitter, and since this secondary breakdown is thought to be caused by a local temperature rise, it is necessary to detect this temperature rise. This is used to detect secondary breakdown. ΔVBE detects this temperature rise as a change in base-emitter voltage JVBB.
It is the law. Looking at this FIG.
BB (curve X) is smaller than ΔVBB (music MY) of the conventional example.

In other words, this means that the temperature increase rate of the transistor according to this embodiment is smaller than that of the conventional example, which means that secondary breakdown is less likely to occur.

This is because by lowering the concentration of the emitter side surface 5b, where current tends to concentrate and become high temperature, the current does not locally concentrate there and the current flows uniformly within the emitter center 5a. It is.

Figure 5 shows the DC current amplification gh corresponding to the collector current Ic.
It shows the relationship of FE. As can be seen from this figure, the transistor according to this embodiment (curve X) has improved hFE compared to the conventional transistor (curve Y). This means that the impurity concentration in the base region is 1! compared to the impurity concentration in the emitter region! hFE is improved because the difference in acceleration is larger than before, and therefore the structure generates more acceleration electric field, and the sides of the emitter region are low concentration and the reactive current flowing there is effectively small. That's what I did.

The present invention is not limited to the above embodiment; for example, the first conductive screen may be of P type and the 24th conductive type may be of N type. In addition, in this example, POCl is used as an impurity evaporation source for diffusion.
Although 3 was used, for example, P2O, (phosphorus pentoxide) may be used.

〔Effect of the invention〕

According to the present invention, the impurity concentration in the base region can be finally lowered without reducing the amount of impurity diffused in the diffusion process, and the concentration near the side surfaces of the second region bonded to the base region can be lowered. This has the effect of improving the current amplification factor and making it possible to manufacture a semiconductor device with improved breakdown strength.

[Brief explanation of drawings]

Fig. 1 is a process sectional view for explaining one embodiment of the present invention, Fig. 2 is a process sectional view for explaining a conventional example, and Figs. 3 to 5 are characteristics of this embodiment and the conventional example. This is a graph showing a comparison. 1a...First semiconductor layer agent Patent attorney Noriyuki Chika (and one other person) Figure 1 (C) Figure 1 Figure 1 Figure 2 (a) Figure 2

Claims (1)

[Claims] Diffusing impurities of a second conductivity type into one main surface of the first semiconductor layer of the first conductivity type to form a first region of the second conductivity type, and etching away a part of the surface of the first region. a step of forming a recess with a predetermined depth; and a step of introducing an impurity of a first conductivity type into the first region from the inner wall of the recess to form a second impurity of the first conductivity type.
A method for manufacturing a semiconductor device, comprising the steps of forming a region and removing the one main surface by lapping to a depth of the bottom surface of the recess.