JPS6340324A - Manufacture of semiconductor element of high breakdown strength - Google Patents

Abstract

PURPOSE:To eliminate a defect caused on the other surface when photoetching is applied, by conducting etching in the state wherein an insulating film having a etching speed smaller than that of an etching material to be etched on the main surface is formed beforehand on the rear surface. CONSTITUTION:A silicon oxide film 9 is formed on both surfaces of a silicon wafer which is prepared by forming a P-type base region 2 and a P-type emitter region 3 on the opposite surfaces of an N-type base region 1 respectively. Next, a silicon nitride film 10 is formed on the film 9 on the rear side. Then, a resist 11 is formed selectively on the film 9 on the main surface of the wafer. Thereafter, an opening corresponding to an opening of the resist 11 is formed in the film 9 by etching. Then, an N-type emitter region 4 is formed by diffusing phosphorus through the opening.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device having diffusion regions on both sides of a wafer, such as a gate turn-or-thyristor. in order to! ! ! It is related to the method of sending.

[Conventional technology]

FIG. 2 is a cross-sectional view showing a conventional gate turn-off thyristor (hereinafter abbreviated as GTO) disclosed in, for example, Japanese Patent Application Laid-Open No. 58-12360. Type base area, 3 is p type emitter area,
4 is a large number of n-type emitter regions separated into strips;
5 is an insulating film that protects the junction between the n-type emitter region 4 and the p-type base area 2; 6, 7.8 are the n-type emitter region 4, the p-type paste material region 2, and the p-type emitter, respectively. A cathode electrode, a gate electrode, and an anode electrode are formed by making ohmic contact with the distribution region 3 using a material such as aluminum.

In such a high breakdown voltage GTO of a mesa-shaped element, a breakdown voltage of around 4000V has been conventionally obtained due to the two-stage bevel structure. In addition, in order to increase the breakdown voltage, by making the n-type base region 1 thick and having high resistivity (low impurity concentration),
The avalanche voltage is increased.

By the way, in the conventional high voltage GTO as mentioned above, 1
The chip has a large chip area, and even if a defect occurs at one location during photoetching in a collection of n-type emitter seed regions 4 separated into strips, it becomes a defective element. In order to prevent defects during photoetching,
Using proven technology for semiconductor integrated circuits, it is essential to work without a set of bins. However, in the case of mesa-type devices, impurities are diffused from both sides of the wafer while controlling the thickness of the n-type base region 1, and when photoetching one main surface, the other main surface is captured. Therefore, the entire surface was masked with resist or the like.

[Problem that the invention seeks to solve]

However, this method of using resist as a photoetching protective film has the following problems in actual manufacturing.

<1) The problem is that the resist coating process using an automatic resist coater fails and the resist wraps around to the opposite side of the wafer. In addition, defects such as scratches caused by the belt when conveying the wafer by the belt, and scratches caused by the vacuum chuck that occurs when the 9eva is fixed in a vacuum and spun to make the resist film uniform.

(2) Scratches caused by the belt during the development process when the wafer is conveyed by the belt while the resist film is soft;
Defects such as scratches caused by the vacuum chuck that occur when the vacuum wafer is fixed and the developer is sprayed in a mist form.

In order to solve the problems (1) and (2), there is a method of photoengraving only one main surface and applying a thick layer of resist with a brush to the other main surface before selective etching.However, productivity is poor.

This invention was made to solve the above-mentioned problems, and it eliminates the defects that occur on the other main surface during the photoetching process of one main surface, and makes it possible to produce semiconductor devices of good quality with high productivity. The object of the present invention is to obtain a method for manufacturing a high-voltage semiconductor device that can be manufactured.

When photo-etching is applied to the main surface, an insulating film having an etching rate lower than that of the material to be etched on the one main surface is formed on the other main surface in advance, and then the etching is performed.

[Effect]

Due to the difference in etching speed with respect to the material to be etched, even after the etching of the material to be etched is completed, the insulating film on the other main surface remains and acts as a mask against etching.

〔Example〕

FIG. 1 is a process sectional view showing an embodiment of the present invention.

Similar to the conventional example, a silicon wafer having a p-type space region 2 and a p-type emitter region 3 formed on both sides of an n-type base region 1 is treated with wet oxygen gas at a temperature of 1100° C., and then subjected to thermal oxidation. A silicon oxide film S was formed on both sides (FIG. 1(a)). Next, CvD (Chemica Vapor Depo) is deposited on the oxide film 9 on the back side.
A silicon functionalized film 10 was formed by a chemical vapor deposition (chemical vapor deposition) method (FIG. 1(b)). This nitride film 1
0 is produced by the reaction of silane gas and ammonia gas at normal pressure or reduced pressure with a precipitation temperature of 500 to 900°C.The nitride film injected onto the surface side is either dry etched in Freon gas or Remove by etching with hot phosphoric acid.

Next, a resist is applied to the entire surface of the oxide film 3 on the surface of the sea urchin, and then a part of the resist film 11 is removed by photolithography (FIG. 1(C)). After that, the wafer is immersed in an etching solution containing hydrofluoric acid, and the resist film 1 is applied to the oxide film 9.
An opening corresponding to opening No. 1 is formed. According to experiments, in an etching solution containing hydrofluoric acid and ammonium fluoride solution mixed at a ratio of 1=6, the etching rate of the oxide film 9 was 1000A in 7 minutes, whereas the etching rate of the nitride film 9 was was 20^/min. In this example, the oxide film 9 had a thickness of 10000 Å and the etching time was about 10 minutes, whereas the nitride film 10 had a thickness of 700 Å.
In case A, the etching time was about 35 minutes (1), and a sufficient masking effect was obtained for etching the oxide film 9. After forming an opening in the oxide film 9 in this manner, n-type impurities such as phosphorus were diffused through the opening to form an n-type emitter row region 4 (FIG. 1(d)).

In the conventional example shown in Figure 2, two steps of silicon etching are then performed using a 7-nitric acid-based etching solution.
In this embodiment, if silicon etching is performed with the nitride film 10 formed, the nitride M10 has a masking effect against this etching solution, and there is no need to provide another mask on one side.

Finally, since it is necessary to make ohmic contact between the p-carving area 3 and the anode electrode 8, the nitride film 10 and the oxide film 9 are removed by etching. It also has a masking effect against diffusion.

In the above example, the nitride film 10 was formed on the surface opposite to the main surface to be photoetched, but the etching rate is slow and the same effect can be obtained by using not only a nitride film but also an alumina film, etc. It will be done.

Furthermore, in the above embodiment, the nitride film 10 is formed on the oxide film 9t, but the nitride film 10 may be formed directly on the p-type emitter region 3, which is different from the above embodiment. It has a similar effect.

〔Effect of the invention〕

As described above, according to the present invention, defects in the photo-etching process can be eliminated by forming an edge film that acts as a mask against the etching solution on the main surface of the wafer opposite to the side to be photo-etched. This can improve the manufacturing yield of high-voltage semiconductor devices. Moreover, there is no need to form a resist film or correct it by brush painting each time, which simplifies the work and improves productivity.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional example. 1m@@@f1 type base persimmon area, 2. ..., p-type base region, 311...p-type emitter region, 9...oxide film, 10, 11@-nitride film, 11 - fist...resist film. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 1 Figure 2 Procedural amendment (voluntary) Dear Commissioner of the Patent Office (,”
, ', +/ 1, Indication of incident Patent application No. 61-183824 2
, Title of the invention: Process for manufacturing high-voltage semiconductor devices 3, Relationship with the amended case Patent applicant address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo. Name (601) Representative Moriya Shiki 4, Mitsubishi Electric Corporation Address Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (7375) Masuo Oiwa, patent attorney (contact information 03) (
21313421 Patent Department), 25, Column 6 of Detailed Description of the Invention in the Specification Subject to Amendment, page 6, line 2 of the Specification of Contents of the Amendment, instead of "to generate."

Claims (1)

[Claims] A method for manufacturing a high-voltage semiconductor element having at least two pn junctions formed by forming semiconductor regions of a conductivity type opposite to that of the semiconductor substrate from both main surfaces of a high-resistivity semiconductor substrate. When photo-etching, an insulating film is formed on the other main surface in advance with a lower etching rate than the material to be etched on the one main surface, and etching is performed with this insulating film covering the other main surface. A method of manufacturing a high-voltage semiconductor device, characterized by performing the following steps.