JPH0462922A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0462922A
JPH0462922A JP17270790A JP17270790A JPH0462922A JP H0462922 A JPH0462922 A JP H0462922A JP 17270790 A JP17270790 A JP 17270790A JP 17270790 A JP17270790 A JP 17270790A JP H0462922 A JPH0462922 A JP H0462922A
Authority
JP
Japan
Prior art keywords
oxide film
treatment
solvent
pretreatment
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17270790A
Other languages
Japanese (ja)
Inventor
Chiharu Kato
千晴 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP17270790A priority Critical patent/JPH0462922A/en
Publication of JPH0462922A publication Critical patent/JPH0462922A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To inhibit the growth of a natural oxide film and to obtain the high break- down strength characteristics of a semiconductor device by a method wherein an oxide film on the surface of a substrate is removed with an HF solution and thereafter, a surface treatment is performed using a ketone solvent, a carboxylic acid solvent or a phosphoric acid solvent or the mixed solvent of these solvents and an HF solvent and after that, a rinsing and a drying are performed. CONSTITUTION:An n<+> drain layer 12 is formed on the surface on one side of an n- high-resistance silicon semiconductor substrate 11, which has a resistivity of 3.5 to 5.5OMEGAcm and the face (100), and thereafter, a normal oxidation pretreatment is performed and an oxidation by buroing hydrogen is performed for 60 minutes at 1100 deg.C in an HCl atmosphere to form a field oxide film 13. One part of this film 13 is etched to form an opening. Then, a BPG film 14 is deposited, a heat treatment is performed for one hour at 1200 deg.C in a diffusion furnace installed in an atmosphere of N2/O2=100/1 and p-type base layers 15 are formed. The diffusion depth of the layers 15 is 3mum and the surface concentration of the layers 15 is 0.5 is 0.5 to 1X10<19>/cm<3>. After that, the whole surface is washed out with an HF treating liquid and a pretreatment is performed on the exposed substrate surface.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体装置の製造方法に係り、とくにpn接
合の逆方向リーク電流を低減するための半導体基板の表
面処理方法に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, and in particular, a method of surface treatment of a semiconductor substrate to reduce reverse leakage current of a pn junction. Regarding.

(従来の技術) 半導体基板表面にpn接合を有する半導体装置、特に高
耐圧を要する絶縁ゲート型半導体装置においては、pn
接合の逆方向リーク電流の低減が重要である。pn接合
の逆方向リーク電流特性は、多くの場合理論値通りには
ならず、電圧と共に増大する電流成分が含まれる。これ
はpn接合の逆方向リーク電流が、拡散電流と発生−再
結合電流の他、表面再結合電流を含み、素子の表面状態
に強く依存するためである。したがってリーク電流は表
面処理の違いに大きく依存し、表面に形成された酸化膜
に取り込まれる欠陥や、熱処理によってSi基板に取り
込まれる欠陥等の抑制がリク電流低減にとって重要であ
ることが従来より指摘されている。
(Prior art) In semiconductor devices having a pn junction on the surface of a semiconductor substrate, especially insulated gate type semiconductor devices that require high breakdown voltage, pn
Reducing the junction's reverse leakage current is important. In many cases, the reverse leakage current characteristics of a pn junction do not match the theoretical value, and include a current component that increases with voltage. This is because the reverse leakage current of the pn junction includes a surface recombination current in addition to a diffusion current and a generation-recombination current, and is strongly dependent on the surface state of the element. Therefore, it has been pointed out that leakage current largely depends on differences in surface treatment, and that it is important to suppress defects that are introduced into the oxide film formed on the surface and defects that are introduced into the Si substrate through heat treatment in order to reduce leakage current. has been done.

従来の露出したpn接合面の処理方法は、HF系の処理
液で処理した後水洗して乾燥する方法、塩酸・過酸化水
素水の混液処理(SC−2処理)第四アンモニウム塩基
・過酸化水素水の混液処理(NC−2処理)或いは硫酸
・過酸化水素水の混液処理(SH処理)等の酸化剤系処
理を行った後水洗乾燥する方法、等が用いられている。
Conventional methods for treating exposed p-n junction surfaces include treating with an HF-based treatment solution, washing with water, and drying, mixed hydrochloric acid/hydrogen peroxide treatment (SC-2 treatment), and quaternary ammonium base/peroxide treatment. A method of carrying out an oxidizing agent treatment such as a mixture treatment of hydrogen water (NC-2 treatment) or a mixture treatment of sulfuric acid and hydrogen peroxide solution (SH treatment) followed by washing with water and drying is used.

しかしながら、これらの処理をした場合、基板表面には
余りきれいてない自然酸化膜が生成される。
However, when these treatments are performed, a native oxide film that is not very clean is formed on the substrate surface.

第8図(a) 〜(d)は、pn接合を有するSi基板
の表面状態の変化によるチャネル変動の様子を示してい
る。n型シリコン基板1に酸化膜2が形成され、この酸
化膜2の開口部からの不純物ドープによりp型層3が形
成された状態が第8図(a)である。このとき酸化膜2
が正イオンで汚染されていると、図のようにチャネル4
が形成される。
FIGS. 8(a) to 8(d) show channel fluctuations due to changes in the surface state of a Si substrate having a pn junction. FIG. 8(a) shows a state in which an oxide film 2 is formed on an n-type silicon substrate 1, and a p-type layer 3 is formed by doping impurities from the opening of this oxide film 2. At this time, oxide film 2
is contaminated with positive ions, channel 4 as shown in the figure.
is formed.

この酸化膜2が除去されると、第8図(b)のようにチ
ャネル4は小さくなる。ところで通常、酸化膜除去には
HF系処理液で用いられるが、HF処理を行うと、基板
表面には第8図(C)のようにF−イオンが吸着し、第
8図(C)のように逆のチャネル5が形成される。そし
てこの吸着イオンを酸化剤系の処理液を用いて脱着させ
る処理を行うと、第8図(d)に示すようにその後形成
される自然酸化膜6は金属イオン等により汚染されたも
のとなり、チャネル7が形成される。酸化剤系の処理液
により処理した場合、形成される自然酸化膜中の金属は
、Na+が1012atIIl/cm2Fe+が5×1
011at刊/cm2程度にも達することがある。
When this oxide film 2 is removed, the channel 4 becomes smaller as shown in FIG. 8(b). Incidentally, an HF-based treatment solution is normally used to remove the oxide film, but when HF treatment is performed, F- ions are adsorbed to the substrate surface as shown in Figure 8 (C). Thus, a reverse channel 5 is formed. When the adsorbed ions are desorbed using an oxidizing agent-based treatment liquid, the natural oxide film 6 that is subsequently formed becomes contaminated with metal ions, etc., as shown in FIG. 8(d). A channel 7 is formed. When treated with an oxidizing agent-based treatment solution, the metal in the natural oxide film formed has Na+ of 1012atIIl/cm2Fe+ of 5×1
It can reach as much as 011at/cm2.

上述した欠陥の多い自然酸化膜の生成は、電極反応的な
面から見ると、次のように表される。
The formation of the above-described native oxide film with many defects can be expressed as follows from the viewpoint of electrode reaction.

S i +2HF十(2−n)e” as i F2+2H+十n e−−(1)2S i 
F−3i  (p) +S i F4     ・・・
(2)S i (p) +2H20→SiO2+2H2
・・・(3)自然酸化膜は、SiF2の分解から生成さ
れる5i(p)と水との反応により容易に形成されるが
、この5i(p)が多孔性で実表面積が大きいため、各
種不純物の捕獲や吸着が容易に起こる。
S i +2HF ten(2-n)e" as i F2+2H+ten e--(1)2S i
F-3i (p) +S i F4...
(2) S i (p) +2H20→SiO2+2H2
...(3) A natural oxide film is easily formed by the reaction of 5i(p) produced from the decomposition of SiF2 with water, but since this 5i(p) is porous and has a large actual surface area, Capture and adsorption of various impurities occurs easily.

このような自然酸化膜により基板表面のpn接合の逆方
向リーク電流の増大や、絶縁ゲート構造を形成した場合
のゲート絶縁膜の膜質劣化が生じる。
Such a natural oxide film causes an increase in reverse leakage current of the pn junction on the substrate surface and deterioration of the quality of the gate insulating film when an insulated gate structure is formed.

HF系処理液で処理したシリコン基板表面は、第8図(
C)に示したようにF−イオンの吸着があり、これが1
017atm / cm 2程度になる。この吸着界面
に例えば、過酸化水素等の処理液が近付くと、上記(2
)〜(3)式の反応が表面近傍で生じ、自然酸化膜が形
成されて、リーク電流が増大する。その様子を第10図
に示しである。同様の傾向は、HF処理後の水洗処理だ
けでも認められる。その様子は第9図に示す通りである
。これら第9図および第10図から、逆方向リーク電流
の増大が自然酸化膜厚の増大とほぼ対応しているこが分
かる。特に、ペリフェリ長が5〜10mにもなるゲート
電極を持つ素子のゲート酸化膜形成前の前処理や、高耐
圧を要するpn接合面を被覆するパシベーション膜形成
前の前処理に、上述した従来の方法を用いると、pn接
合の耐圧低下、ゲート耐圧低下等によって所望の高耐圧
特性が得られなくなる。
The surface of the silicon substrate treated with the HF-based treatment liquid is shown in Figure 8 (
As shown in C), there is adsorption of F- ions, and this
It will be about 0.17 atm/cm2. For example, when a treatment liquid such as hydrogen peroxide approaches this adsorption interface, the above (2)
) to (3) reactions occur near the surface, a natural oxide film is formed, and leakage current increases. The situation is shown in FIG. A similar tendency is observed only in the water washing treatment after the HF treatment. The situation is as shown in FIG. It can be seen from these FIGS. 9 and 10 that the increase in the reverse leakage current almost corresponds to the increase in the natural oxide film thickness. In particular, the above-mentioned conventional method is suitable for pretreatment before forming a gate oxide film for devices with gate electrodes with a periphery length of 5 to 10 m, and for pretreatment before forming a passivation film covering a pn junction surface that requires a high breakdown voltage. If this method is used, desired high breakdown voltage characteristics cannot be obtained due to a reduction in the breakdown voltage of the pn junction, a reduction in the gate breakdown voltage, etc.

(発明が解決しようとする課題) 以上のように従来の表面処理法では、シリコン基板表面
に多孔質で余りきれいでない自然酸化膜か生成され、こ
れがpn接合の逆方向リーク電流を増大させる原因とな
っている。
(Problems to be Solved by the Invention) As described above, in the conventional surface treatment method, a porous and not very clean natural oxide film is generated on the surface of the silicon substrate, which is the cause of increasing the reverse leakage current of the pn junction. It has become.

本発明は、その様な自然酸化膜の成長を抑制し、もって
逆方向リーク電流の小さいpn接合を持つ半導体装置の
製造方法を提供することを目的としている。
An object of the present invention is to provide a method for manufacturing a semiconductor device having a pn junction with a small reverse leakage current by suppressing the growth of such a natural oxide film.

[発明の構成] (課題を解決するための手段) 本発明は、半導体基板表面の酸化膜をHF系の溶液で除
去した後、ケトン系溶剤、カルボン酸系溶剤もしくはリ
ン酸系溶剤またはこれらとHF系溶剤の混合溶剤により
表面処理を行い、その後水洗乾燥させるという工程を用
いることを特徴とする。
[Structure of the Invention] (Means for Solving the Problems) The present invention provides that after removing an oxide film on the surface of a semiconductor substrate with an HF-based solution, a ketone-based solvent, a carboxylic acid-based solvent, a phosphoric acid-based solvent, or a combination thereof is used. It is characterized by using a process of performing surface treatment with a mixed solvent of HF-based solvents, followed by washing with water and drying.

(作用) 本発明の処理法を用いると、自然酸化膜の成長が抑制さ
れ、高耐圧特性を持った半導体装置を得ることができる
(Function) When the processing method of the present invention is used, the growth of a native oxide film is suppressed, and a semiconductor device having high breakdown voltage characteristics can be obtained.

(実施例) 以下、本発明の詳細な説明する。(Example) The present invention will be explained in detail below.

第1図(a)〜(d)は、本発明の一実施例による縦型
の絶縁ゲート型MO8FETの製造工程を示す。比抵抗
3.5〜5,5Ωcm、(100)面の高抵抗n型シリ
コン半導体基板11の一方の面にn型ドレイン層12を
形成した後、通常の酸化前処理を施し、HCfi雰囲気
中で1100℃。
FIGS. 1(a) to 1(d) show the manufacturing process of a vertical insulated gate MO8FET according to an embodiment of the present invention. After forming an n-type drain layer 12 on one side of a high-resistance n-type silicon semiconductor substrate 11 with a specific resistance of 3.5 to 5.5 Ωcm and a (100) plane, a normal oxidation pretreatment is performed and the substrate is heated in an HCfi atmosphere. 1100℃.

60分の水素燃焼酸化を行ってフィールド酸化膜13を
形成する。このフィールド酸化膜13を一部エッチング
して開口を形成する((a))。ついでBSG膜14を
堆積し、N2102 =100 /1の雰囲気に設定さ
れた拡散炉で1200’C,1時間の熱処理を行って、
p型ベース層15を形成する((b))。p型ベース層
15は、拡散深さ3μm、表面濃度0.5〜1×1o1
9/eII+3である。
A field oxide film 13 is formed by hydrogen combustion oxidation for 60 minutes. This field oxide film 13 is partially etched to form an opening ((a)). Next, a BSG film 14 was deposited and heat treated at 1200'C for 1 hour in a diffusion furnace set to an atmosphere of N2102 = 100/1.
A p-type base layer 15 is formed ((b)). The p-type base layer 15 has a diffusion depth of 3 μm and a surface concentration of 0.5 to 1×1o1.
9/eII+3.

その後全面をHF処理液によりウォッシュ・アウトし、
露出した基板面に前処理を施す((c))。
After that, wash out the entire surface with HF treatment solution,
Pretreatment is performed on the exposed substrate surface ((c)).

具体的な前処理とその効果については、後述する。Specific preprocessing and its effects will be described later.

その後、通常の工程にしたがって、ゲート酸化膜16を
形成して多結晶シリコン膜によるゲート電極17を形成
し、ゲート電極17をマスクとしてn型ソース層18を
拡散形成する。そして全面をCVD酸化膜19で覆って
、これにコンタクト孔を開けてソース電極20を形成し
、裏面にはドレイン電極21を形成して、MOSFET
が完成する((d))。
Thereafter, a gate oxide film 16 is formed, a gate electrode 17 made of a polycrystalline silicon film is formed, and an n-type source layer 18 is diffused using the gate electrode 17 as a mask, according to a normal process. Then, the entire surface is covered with a CVD oxide film 19, a contact hole is made in this to form a source electrode 20, and a drain electrode 21 is formed on the back surface to form a MOSFET.
is completed ((d)).

第2図は、第1図(C)での前処理にカルボン酸系処理
液としてCH3CO0Hを用いた処理を行ない、その後
10分の水洗処理をした場合の、pn接合逆方向リーク
電流を測定した結果である。
Figure 2 shows the measurement of the p-n junction reverse leakage current when CH3CO0H was used as the carboxylic acid treatment liquid for the pretreatment in Figure 1 (C), followed by 10 minutes of water washing. This is the result.

自然酸化膜は2〜5人と薄く、リーク電流はこの前処理
で全く増大していない。
The natural oxide film is as thin as 2 to 5 thick, and the leakage current has not increased at all with this pretreatment.

比較のため、酸化剤系処理液を用いたS(、−2処理を
行なった場合、およびNC−2処理を行なった場合の結
果をそれぞれ第6図および第7図に示す。これらの従来
の前処理法を用いた場合の結果に比べて、カルボン酸系
処理液を用いることにより、自然酸化膜の成長が抑制さ
れ、リーク電流が大きく低減されることが明らかである
For comparison, the results of S(-2 treatment using an oxidizing agent-based treatment liquid and NC-2 treatment) are shown in Figures 6 and 7, respectively. It is clear that the growth of a native oxide film is suppressed and the leakage current is significantly reduced by using the carboxylic acid treatment liquid, compared to the results obtained when the pretreatment method is used.

第3図は、カルボン酸系処理液に代ってリン酸系処理液
を用いて前処理を行なった場合である。
FIG. 3 shows the case where pretreatment was performed using a phosphoric acid treatment liquid instead of a carboxylic acid treatment liquid.

リン酸処理後の水洗処理は10分である。この場合も同
様に自然酸化膜の成長は少く、逆方向り一り電流も低減
されている。
The water washing treatment after the phosphoric acid treatment is 10 minutes. In this case as well, the growth of the native oxide film is small, and the current in the reverse direction is also reduced.

第4図はさらにケトン系処理液として、(CH3)2C
0を用いた前処理を行なった場合である。(CH3)2
C0処理後の水洗処理1分と10分のデータを示してい
る。この場合も同様の効果が得られている。
Figure 4 further shows (CH3)2C as a ketone-based treatment liquid.
This is a case where preprocessing using 0 is performed. (CH3)2
Data for 1 minute and 10 minutes of water washing treatment after C0 treatment are shown. Similar effects were obtained in this case as well.

第5図は、CH,C0OHと希HFの混合液を用いた前
処理を行なった場合である。この様にHFを混合しても
、効果が得られる。データは示さないが、リン酸処理、
ケトン系処理の場合にHFを混合しても、同様の良好な
結果が得られる。
FIG. 5 shows the case where pretreatment was performed using a mixed solution of CH, COOH and dilute HF. Even if HF is mixed in this way, an effect can be obtained. Although data not shown, phosphoric acid treatment,
Similar good results can be obtained by mixing HF in ketone-based treatments.

以上のような前処理を経て完成された縦型MO8FET
は、リーク電流が少いだけでなく、従来の前処理を行な
った場合に比べてゲート・ソース間の耐圧が高くなり、
またしきい値の安定性にも優れていることが確認された
Vertical MO8FET completed after the above pre-processing
not only has less leakage current, but also has a higher breakdown voltage between the gate and source than when conventional pretreatment is performed.
It was also confirmed that the threshold stability was excellent.

本発明は上記実施例に限られない。実施例では縦型MO
3FETを説明したが、他の絶縁ゲート構造を持つ素子
、例えば絶縁ゲートサイリスタやI GBTは勿論、絶
縁ゲート構造を持たない素子であっても、有効である。
The present invention is not limited to the above embodiments. In the example, vertical MO
Although a 3FET has been described, other elements having an insulated gate structure, such as insulated gate thyristors and IGBTs, as well as elements without an insulated gate structure, are also effective.

[発明の効果] 以上述べたように本発明によれば、pn接合面の前処理
工程の改良により、pn接合の逆方向リーク電流の低減
を図った半導体装置を得ることができる。
[Effects of the Invention] As described above, according to the present invention, by improving the pretreatment process of the pn junction surface, it is possible to obtain a semiconductor device in which the reverse leakage current of the pn junction is reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は本発明の実施例の縦型MO3F
ETの製造工程を示す図、 第2図はそのゲート酸化膜形成前の CH,C0OHを用いた前処理による逆方向リーク電流
特性を示す図、 第3図は同じ<H3PO4を用いた前処理による逆方向
リーク電流特性を示す図、 第4図は同じ<  (CH3)2 cOを用いた前処理
による逆方向リーク電流特性を示す図、第5図は同じく
希HF/ (CH3)COOHを用いた前処理による逆
方向リーク電流特性を示す図、 第6図は従来の5C−2処理を行なった場合の逆方向リ
ーク電流特性を示す図、 第7図は従来のNC−2処理を行なった場合の逆方向リ
ーク電流特性を示す図、 第8図(a)〜(d)は、表面状態によるチャネル形成
の様子を説明するための図、 第9図は従来の前処理によるリーク電流および自然酸化
膜成長の様子を示す図、 第10図は同じ〈従来の他の前処理によるリーク電流お
よび自然酸化膜成長の様子を示す図である。 11・・・高抵抗n型シリコン基板(n型ベース層)、
]2・・・n型ドレイン層、13・・・フィールド酸化
膜、14・・・BSG膜、15・・・n型ベース層、1
6・・・ゲート酸化膜、17・・・ゲート電極、18・
・・n型ソース層、19・・・CVD酸化膜、20・・
・ソース電極、21・・・ドレイン電極。 出願人代理人 弁理士 鈴江武彦 [yrl ] M; m!、 −r+ [4u ?[v
rl]ソ専6−/市9y F 一 第 図 (水洗1/′rf) 5分 01If 第 図 (水洗1竹) (2分)  (5分) 第10図 (10竹)
FIGS. 1(a) to (d) are vertical MO3Fs according to embodiments of the present invention.
Figure 2 is a diagram showing the manufacturing process of ET. Figure 2 is a diagram showing the reverse leakage current characteristics due to pretreatment using CH and COOH before the formation of the gate oxide film. Figure 3 is a diagram showing the reverse leakage current characteristics due to pretreatment using the same <H3PO4. Figure 4 is a diagram showing the reverse leakage current characteristics. Figure 4 is a diagram showing the reverse leakage current characteristics after pretreatment using the same <(CH3)2 cO. Figure 5 is a diagram showing the reverse leakage current characteristics when the same dilute HF/(CH3)COOH was used. Figure 6 shows the reverse leakage current characteristics when the conventional 5C-2 treatment is performed. Figure 7 shows the reverse leakage current characteristics when the conventional NC-2 treatment is performed. 8(a) to 8(d) are diagrams for explaining the state of channel formation depending on the surface condition. FIG. 9 is a diagram showing the reverse leakage current characteristics due to conventional pretreatment and FIG. 10 is a diagram showing the state of film growth, and FIG. 10 is a diagram showing the state of leakage current and natural oxide film growth by another conventional pretreatment. 11... High resistance n-type silicon substrate (n-type base layer),
]2...n-type drain layer, 13...field oxide film, 14...BSG film, 15...n-type base layer, 1
6... Gate oxide film, 17... Gate electrode, 18.
...N-type source layer, 19...CVD oxide film, 20...
- Source electrode, 21... drain electrode. Applicant's agent Patent attorney Takehiko Suzue [yrl] M; m! , −r+ [4u? [v
rl] Sosen 6-/City 9y F 1st figure (Washing 1/'rf) 5 minutes 01If Fig. 1 (Water washing 1 bamboo) (2 minutes) (5 minutes) Fig. 10 (10 bamboos)

Claims (1)

【特許請求の範囲】  半導体基板表面にpn接合を有する半導体装置を製造
する方法であって、 基板のpn接合面上の酸化膜をHF系溶液で除去する工
程と、 露出したpn接合面上をケトン系溶剤、カルボン酸系溶
剤もしくはリン酸系溶剤またはこれらとHFとの混合溶
剤により表面処理する工程と、その後基板を水洗乾燥す
る工程と、 を有することを特徴とする半導体装置の製造方法。
[Claims] A method for manufacturing a semiconductor device having a pn junction on the surface of a semiconductor substrate, comprising: removing an oxide film on the pn junction surface of the substrate with an HF solution; A method for manufacturing a semiconductor device, comprising the steps of surface treating with a ketone solvent, a carboxylic acid solvent, a phosphoric acid solvent, or a mixed solvent of these and HF, and then washing and drying the substrate.
JP17270790A 1990-07-02 1990-07-02 Manufacture of semiconductor device Pending JPH0462922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17270790A JPH0462922A (en) 1990-07-02 1990-07-02 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17270790A JPH0462922A (en) 1990-07-02 1990-07-02 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0462922A true JPH0462922A (en) 1992-02-27

Family

ID=15946852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17270790A Pending JPH0462922A (en) 1990-07-02 1990-07-02 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0462922A (en)

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