JPS60208854A - Manufacture of semiconductor solid circuit element - Google Patents
Manufacture of semiconductor solid circuit elementInfo
- Publication number
- JPS60208854A JPS60208854A JP6516184A JP6516184A JPS60208854A JP S60208854 A JPS60208854 A JP S60208854A JP 6516184 A JP6516184 A JP 6516184A JP 6516184 A JP6516184 A JP 6516184A JP S60208854 A JPS60208854 A JP S60208854A
- Authority
- JP
- Japan
- Prior art keywords
- film
- single crystal
- spinel
- thermal strain
- circuit element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、各能動層用の単結晶シリコン膜。[Detailed description of the invention] [Industrial application field] This invention uses a single crystal silicon film for each active layer.
単結晶電極、単結晶絶縁膜を順次積層して半導体、６μ
体回路素子を形成する半導体立体回路素子の製姑方法に
関する。Semiconductor, 6μ, by sequentially stacking a single crystal electrode and a single crystal insulating film
The present invention relates to a method for manufacturing a semiconductor three-dimensional circuit element for forming a three-dimensional circuit element.
一般に、半導体薄膜、電極！配線用薄膜および両縁用薄
膜を交互に積層して立体的回路素子を形濃し、回路の高
密度化、高集積度化を図ることが行々われでいるが、特
性の優れた半導体立体回路素子を得ろために、従来前記
素子を溝成する各材料を単結晶状態のまま積層すること
が試みられている。In general, semiconductor thin films, electrodes! Thin films for wiring and thin films for both edges are laminated alternately to form three-dimensional circuit elements, thereby increasing the density and integration of circuits. In order to obtain a circuit element, attempts have been made to laminate the materials forming the grooves of the element in a single crystal state.
たとえば、ＭＯＳ）ランジスタを製造する場合、第１図
に示すように、最下層の単結晶シリコン膜に相当するシ
リコン基板（１）に不純物を拡散して能動領域であるソ
ース領域（２）、ドレイン領域（３ンを形成し、基板（
１）上にゲート絶縁膜として単結晶スピネル膜（４）を
形成したのち、基板（１）とスピネル膜（４）との界面
にシリコン酸化膜（５）を形成してスピネル膜（４）と
シリコン酸化膜（５）との２重絶縁膜（６）を形成する
。For example, when manufacturing a MOS (MOS) transistor, as shown in Figure 1, impurities are diffused into a silicon substrate (1) corresponding to the bottom single-crystal silicon film to form a source region (2) which is an active region, a drain region (2) which is an active region, and a drain region (2) which is an active region. area (3) and the substrate (
1) After forming a single crystal spinel film (4) on top as a gate insulating film, a silicon oxide film (5) is formed at the interface between the substrate (1) and the spinel film (4), and the spinel film (4) A double insulating film (6) with a silicon oxide film (5) is formed.
そして、選択エツチングにより２重絶縁膜（６）にコン
タクトホール（７）を形成し、スピネル膜（４）上およ
びコンタクトホール（７）内に電極！配線用薄膜である
単結晶シリコン薄膜を形成するとともに、前記シリコン
薄膜に不純物を高濃度に導入してレーザアニール等を施
こし、前記シリコン薄膜を低抵抗化し、前記シリコン薄
膜を所定形状に選択エツチングして電極配線パターン（
８）を形成したのち、ス１ピネル膜（４）上およびパタ
ーン（８）上に居間絶縁膜叫しての単結晶スピネル膜（
９）を形成し、さらにス、ピーネル膜（９）上に次の能
動層用の単結晶シリコン膜（１０を形成し、以下前記の
工程を繰り返してＭＯＳトランジスクを製造する。Then, a contact hole (7) is formed in the double insulating film (6) by selective etching, and an electrode is formed on the spinel film (4) and in the contact hole (7). A single-crystal silicon thin film, which is a thin film for wiring, is formed, impurities are introduced into the silicon thin film at a high concentration, laser annealing or the like is performed to lower the resistance of the silicon thin film, and the silicon thin film is selectively etched into a predetermined shape. and the electrode wiring pattern (
8), a single crystal spinel film (4) and a single crystal spinel film (8) as a living room insulation film is formed on the spinel film (4) and the pattern (8).
9) is formed, and then a single crystal silicon film (10) for the next active layer is formed on the spinel film (9), and the above steps are repeated to manufacture a MOS transistor.
ところが、シリコン、酸化シリコンおよびスピネル膜の
熱膨張率が異なる−こめ、スピネル膜１４）。However, silicon, silicon oxide, and spinel films have different coefficients of thermal expansion.
４（９）の形成工程における熱によりとくにスピネ、ル
、−膜’、４） ｅ （９）に熱歪が生じ易く、歪によ
る割れが発１生、′、シ、半導体立体回路素子のセナ歩
留が低下する）尭電う欠点がある。The heat in the forming process of 4(9) tends to cause thermal strain, especially in the spinel, l, - film', 4) e (9), and cracks due to strain occur. The disadvantage is that the yield decreases).
この発明は、前記の点に留意してうされたものであり、
単結晶スピネル膜に熱歪緩和用溝を形成し、前記スピネ
ル膜形成時の熱歪を緩和して歪による割れ等の発生を防
止することを目的とする。This invention has been made with the above points in mind,
The purpose of this invention is to form grooves for alleviating thermal strain in a single crystal spinel film, thereby alleviating thermal strain during formation of the spinel film and preventing the occurrence of cracks and the like due to strain.
この発明は、単結晶シリコン膜、単結晶電極。 This invention relates to a single crystal silicon film and a single crystal electrode.
単結晶絶縁膜を順次積層して形成する半導体立体回路素
子の製造方法において、前記単結晶絶縁膜として単結晶
スピネル膜を形成する工程と、前記シリコン膜に形成さ
れた能動領域および該領域上に形成される単結晶電極を
囲むように前記スピネル膜に熱歪緩和用溝を形成する工
程とを含むことを一特徴とする半導体立体回路素子の製
造方法である１コ
〔発明の効果〕
したがって、この発明の半導体立体回路素子の製造方法
によると、単結晶絶縁膜として単結晶スピネル膜を形成
し、能動領域および該領域上に形成される単結晶電極を
囲むように前記スピネル膜に゛熱歪緩和用溝を形成する
ことにより、前記スピネル膜形成時の熱歪を緩和して歪
による割れ等の発生を防止することができ、半導体立体
回路素子の歩留の向上を図ることができ乙。In a method for manufacturing a semiconductor three-dimensional circuit element formed by sequentially stacking single crystal insulating films, the steps include forming a single crystal spinel film as the single crystal insulating film, and forming an active region formed in the silicon film and on the region. A method for manufacturing a semiconductor three-dimensional circuit element, which is characterized in that it includes a step of forming a thermal strain relaxation groove in the spinel film so as to surround the single crystal electrode to be formed. [Effects of the Invention] Therefore, According to the method for manufacturing a semiconductor three-dimensional circuit element of the present invention, a single-crystal spinel film is formed as a single-crystal insulating film, and the spinel film is subjected to thermal strain so as to surround an active region and a single-crystal electrode formed on the region. By forming the relaxation groove, it is possible to alleviate the thermal strain during the formation of the spinel film and prevent the occurrence of cracks, etc. due to the strain, and it is possible to improve the yield of semiconductor three-dimensional circuit elements.
つぎに、この発明を、その１実施例を示した第２図以下
の図面とともに詳細に説明する。Next, this invention will be explained in detail with reference to the drawings from FIG. 2 onwards showing one embodiment thereof.
まず、最下層の単結晶シリコン膜に相当するシリコン基
板αη上に開口Ｑりを有するシリコン酸化膜からなる拡
散マスク０３を形成し、基板（ｌ］）の開口０功に露出
する部分に不純物を拡散して能動領域であるソース領域
０４）、ドレイン領域０υを形成し、マスク０３を除去
したのち、第３図に示すようＫ 、ＣＶＤ法により基板
（ｌ◇上に単結晶絶縁膜として厚さ５００Ａの単結晶ス
ピネル膜００を形成し、ｗｅＬＱ２法によリスピネル膜
ＯＱを介して基板（１１）を酸化し、基板（１１）とス
ピネル膜ＯＱとの界面に厚さ５００Ａのシリコン！化膜
αηを形成してスピネル膜０・どシリコン酸化１１ηと
の２重絶縁膜α８）を形成し、選択エツチングに、μす
、２重絶縁１摸α８）にコンククトホールＯ！Ｊを形鱒
スるとともに９選択エツチングにより能動領域および後
述の電極配線パターンを囲むように熱歪緩和用溝（イ）
を形成する。First, a diffusion mask 03 made of a silicon oxide film having an opening Q is formed on a silicon substrate αη corresponding to the single-crystal silicon film in the bottom layer, and an impurity is doped in the portion of the substrate (l) that is exposed through the opening 0. After diffusing to form a source region 04) and a drain region 0υ, which are active regions, and removing the mask 03, as shown in FIG. A 500A single crystal spinel film 00 is formed, and the substrate (11) is oxidized via the spinel film OQ by the weLQ2 method, and a 500A thick silicon film αη is formed at the interface between the substrate (11) and the spinel film OQ. A double insulating film α8) with a spinel film 0 and silicon oxide 11η is formed by selective etching. A thermal strain relief groove (A) is formed by shaping J and surrounding the active area and the electrode wiring pattern (described later) by 9-selective etching.
form.
ツキに、第４図に示すように、スピネル膜００上および
コンククトホー、ル０呻内に単結晶電極である単結晶シ
リコン薄膜を形成するとともに、前記シリコン酸化に不
純物を高濃度に導入してレーザアー、１１−ル等を施こ
し、前記シリコン薄膜を低抵抗化し、前記シリコン薄膜
を所定形状に選択エツチングして電極配線パターンＱ１
）を形成したのち、スピネｒＬ［α０上、パクーンＱυ
上および溝（イ）内に層間絶縁膜としての単結晶スピネ
ル膜（イ）を形成し、選択エツチングによりスピネル膜
（イ）て下層の前記能動領域およびパターンＯＤを囲み
、かっ溝（イ）とずれるように熱歪緩和用溝＠を形成し
、さらにスピネル膜（２）上および溝（ハ）内に次の能
動層用の単結晶シリコン膜を°形成し、以下前記の工程
を繰り返して積層構造のＭＯＳ ）ランジスクを製造す
る。Finally, as shown in FIG. 4, a single-crystal silicon thin film, which is a single-crystal electrode, is formed on the spinel film 00 and in the concrete holes, and a laser beam is applied by introducing impurities into the silicon oxide at a high concentration. , 11-ru etc. to lower the resistance of the silicon thin film, and selectively etching the silicon thin film into a predetermined shape to form an electrode wiring pattern Q1.
), then spiner L [on α0, Pakun Qυ
A single crystal spinel film (A) as an interlayer insulating film is formed on the upper layer and in the groove (A), and by selective etching, the spinel film (A) surrounds the active region and pattern OD of the lower layer, and the groove (A) is formed. Grooves for thermal strain relief are formed so as to be offset from each other, and then a single crystal silicon film for the next active layer is formed on the spinel film (2) and in the groove (c), and the above steps are repeated to stack the layers. MOS structure) Manufacture a run disk.
し−二がって、前記実施例によると、溝翰、（ハ）を形
成したため、スピネル膜ａｅ ｔ 働の形成時の熱歪を
緩和して歪による割れ等の発生を防止すること］でき、
半導体立体回路素子の歩留の向上を図乙ｌｈｉとができ
るとともに特性の良好１半導体立体回將１素子を提供す
ることができる。Therefore, according to the above embodiment, since the grooves (c) are formed, it is possible to alleviate the thermal strain during the formation of the spinel film and prevent the occurrence of cracks due to strain. ,
The yield of semiconductor three-dimensional circuit elements can be improved, and one semiconductor three-dimensional circuit element with good characteristics can be provided.
さらに、能動領域およびパ少−ンＱυを囲むよって溝（
４）、＠を形成し、しかも両溝（ホ）、（至）をずらしAdditionally, a groove (
4), form @, and shift both grooves (e) and (to)
第１図は従来の半導体立体回路素子の断面図、第２図１
いし第４図はこの発明の半導体立体回路素子の製造方法
の１実施例を示し、それぞれ製造論程を示す断面図であ
る。
ａη・・・シリコン基板、Ｑ４） 、 Ｑ！ｅ・ソース
領域、トレイン領域、Ｑ（！ 、 ＠・・単結晶スピネ
ル膜、（イ）、（ハ）・・溝、Ｃυ・・・電極配線パク
ーン。
特許出願人 工業技術院長 川 １）裕部「 １ ■
第 ３１Ｘｌ
第 ４ 図Figure 1 is a cross-sectional view of a conventional semiconductor three-dimensional circuit element, Figure 2
FIG. 4 shows one embodiment of the method for manufacturing a semiconductor three-dimensional circuit element of the present invention, and is a sectional view showing the manufacturing process. aη...Silicon substrate, Q4), Q! e・Source region, train region, Q(!, @...single crystal spinel film, (a), (c)...groove, Cυ...electrode wiring pattern. Patent applicant Kawa, Director of the Agency of Industrial Science and Technology 1) Yube 1 ■ 31Xl Fig. 4
Claims (1)
次積層して形成する半導体立体回路素子の製造方法にお
いて、前記単結晶絶縁膜として単結晶スピネル膜を形成
する工程と、前記シリコン膜に形成された能動領域およ
び該領域上に形成される単結晶電極を囲むように前記ス
ピネル膜に熱歪緩和用溝を形成する工程とを含むことを
特徴とする半導体立体回路素子の製造方法。(2) A method for manufacturing a semiconductor three-dimensional circuit element formed by sequentially laminating a single crystal silicon film, a single crystal sleeping electrode, and a single crystal insulating film, including the steps of forming a single crystal spinel film as the single crystal insulating film; 1. A method for manufacturing a semiconductor three-dimensional circuit element, comprising the step of forming a thermal strain relaxation groove in the spinel film so as to surround an active region formed in the active region and a single crystal electrode formed on the region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6516184A JPS60208854A (en) | 1984-04-03 | 1984-04-03 | Manufacture of semiconductor solid circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6516184A JPS60208854A (en) | 1984-04-03 | 1984-04-03 | Manufacture of semiconductor solid circuit element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60208854A true JPS60208854A (en) | 1985-10-21 |
| JPH0133944B2 JPH0133944B2 (en) | 1989-07-17 |
Family
ID=13278877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6516184A Granted JPS60208854A (en) | 1984-04-03 | 1984-04-03 | Manufacture of semiconductor solid circuit element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60208854A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5165576A (en) * | 1974-12-04 | 1976-06-07 | Hitachi Ltd | HANDOTAISHUSEKIKAIROSOCHINO SEIHO |
| JPS5821854A (en) * | 1981-07-31 | 1983-02-08 | Sanyo Electric Co Ltd | Semiconductor circuit element |
-
1984
- 1984-04-03 JP JP6516184A patent/JPS60208854A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5165576A (en) * | 1974-12-04 | 1976-06-07 | Hitachi Ltd | HANDOTAISHUSEKIKAIROSOCHINO SEIHO |
| JPS5821854A (en) * | 1981-07-31 | 1983-02-08 | Sanyo Electric Co Ltd | Semiconductor circuit element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0133944B2 (en) | 1989-07-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |