JPH01290255A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a short circuit between a gate electrode and a capacitor electrode and the increase in a leakage current effectively by a method wherein a base film is provided to the outside of a contact hole on an insulating film under a lower capacitor electrode. CONSTITUTION:A semiconductor memory has such a laminated type capacitor cell structure that a capacitor is laminated on a MOS transistor through the intermediary of an insulating film 6, and lower capacitor electrodes 71 and 72 are in contact with a source diffusion layer 51 or a drain diffusion layer 52 of the MOS transistor through the intermediary of a contact hole bored in the insulating film 6. And, a base film is provided to the outside of the contact hole on the insulating film 6 under the lower capacitor electrodes 71 and 72. The base film, for instance, of the same conductive film as the lower capacitor electrodes 71 and 72 are pattern-formed concurrently with the electrodes 71 and 72 to be a part of the electrodes 71 and 72. By these processes, even if pinholes occur in the insulating film 6 at various treatments performed before the formation of the capacitor, a short circuit and an increase in a leakage current caused by the pinholes can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to a semiconductor memory device, and more particularly to the structure and manufacturing method of a dynamic RAM (DRAM) having a stacked capacitor cell structure.

(Prior Art) As DRAMs continue to become more highly integrated, the area of capacitors decreases, causing serious problems such as erroneous reading of memory contents and data destruction due to radiation. In order to solve these problems, proposals have been made to provide capacitors with various structures. One of them is the multilayer capacitor.
It has a cell structure. In this method, a MOS transistor is first formed on an isolated semiconductor substrate, then an insulating film is placed over the MOS transistor, a contact hole is formed in the MOS transistor, and a lower capacitor electrode is formed to contact the source or drain diffusion layer of the MO3I-transistor. Then, an upper capacitor electrode is further formed via a capacitor insulating film to constitute a memory cell.

In this way, in a stacked capacitor cell.

Since a capacitor is formed on a MOS transistor through an interlayer insulating film, the surface of the interlayer insulating film thereunder is usually made as smooth as possible in order to facilitate processing of the lower capacitor. As a specific method, for example, when a CVDSiO2 film is used as the first interlayer insulating film, there is a method of converting the second surface into phosphorous glass by performing heat treatment for about 300 minutes in POCR3 gas at about 900°C. As a result, the VDSi02 film surface partially flows and becomes smooth. Then, by etching the phosphorus glass film on the surface for about 1 minute with a hydrofluoric acid-based etching solution, a smooth surface shape can be obtained. After obtaining a smooth surface shape, a contact hole is opened in the CV D Si O 2 film, and a lower capacitor electrode, a capacitor insulating film, and an upper capacitor electrode are sequentially formed.

However, such a conventional method causes the following secondary problem. First, when the CVD 5iOz film, which is an interlayer insulating film, is made into phosphor glass and fluidized, the surface is then removed using a hydrofluoric acid-based etching solution such as buffered hydrofluoric acid such as ammonium fluoride using about 1000 people. At this time, the weak parts of the 5i02 film are deeply etched and pinholes are generated. Then, when the contact hole is opened and the capacitor is laminated after this.

This causes a short circuit accident and an increase in leakage current between the gate electrode of the MOS transistor that has already been formed and the lower capacitor electrode. Second, CVD5i0 as an interlayer insulating film
After forming a contact hole in the two films and before forming a capacitor electrode, a dilute hydrofluoric acid treatment is performed to remove a natural oxide film formed on the surface of the substrate exposed to the contact hole.

At this time as well, the weak portions of the CVD5i02 film are deeply etched to form pinholes. This also causes a short-circuit accident between the capacitor electrode and the gate electrode of the MOS transistor and an increase in leakage current.

(Problem to be solved by the invention) As described above, the DR of the conventional stacked capacitor cell structure
In the AM manufacturing method, a short-circuit accident between the gate electrode of a MOS transistor and a capacitor stacked on the MOS transistor is likely to occur, reducing the yield and reliability of the product. There was a problem.

The present invention is a multilayer capacitor that solves these problems.
An object of the present invention is to provide a DRAM with a cell structure and a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) A DRAM according to the present invention has a capacitor stacked on a MOS transistor with an insulating film interposed therebetween.

The base is a stacked capacitor cell structure in which the lower capacitor electrode contacts the source or drain diffusion layer of the MOS transistor through a contact hole made in the insulating film. It is characterized by having a base film on the outside of the contact hole. For example, the base film is patterned using the same conductive film as the lower capacitor electrode at the same time as the lower capacitor electrode, and becomes a part of the lower capacitor electrode. Alternatively, an insulating film different from the above-mentioned insulating film is used as the base film.

The first method for manufacturing the DRAM of the present invention is as follows.

The substrate on which the MOS transistor is formed is covered with a first insulating film, and before contact holes are formed in this, a first conductive film that will become a part of the lower capacitor electrode is laminated, and these first insulating films and A contact hole is opened in the laminated film of the first conductor film, and a second conductor film is formed to form the remainder of the lower capacitor electrode in contact with the source or drain diffusion layer of the MOS transistor. Then, the first and second conductor films are simultaneously patterned to form a lower capacitor electrode, and an upper capacitor electrode is formed thereon by a third conductor film with a capacitor insulating film interposed therebetween.

Thereafter, the entire surface is covered with a second insulating film, and a contact hole is opened to form a bit line that contacts the drain or source diffusion layer of the MOS transistor.

A second method of the present invention is to cover a substrate on which a 2M0S transistor is formed with a first insulating film, and then, before forming a contact hole thereon, further layer a second insulating film,
A contact hole is formed in the laminated film of the insulating film and the first insulating film to form a lower capacitor electrode that contacts the source or drain diffusion layer of the MOS transistor. Then, an upper capacitor electrode is formed on the lower capacitor electrode with a capacitor insulating film interposed therebetween. Thereafter, the entire surface is covered with a third insulating film, and a contact hole is opened to form a bit line that contacts the drain or source diffusion layer of the MOS transistor.

(effect) In the stacked capacitor cell structure of the present invention.

Since the capacitor has a base film separate from the original insulating film as an interlayer insulating film under the capacitor, even if pinholes are formed in the insulating film due to various treatments before forming the capacitor, short circuits and leakage current increases due to this. can be prevented. In particular, if the same conductive film as the lower capacitor electrode is used as the base film and formed in the same pattern as the lower capacitor electrode, the lower capacitor electrode will be substantially thicker. Therefore, by forming the upper capacitor electrode so as to face the upper surface and side surfaces of the lower capacitor electrode, the area on the side surfaces can be increased and a large capacitance can be obtained.

Further, according to the first method of the present invention, after forming a first insulating film as a living room insulating film on a substrate on which a MOS transistor is formed, and before forming a contact hole in a moss, a part of a capacitor electrode is formed. The first conductive film is overlaid. Therefore, this first conductor film prevents the interlayer insulating film from being etched by the dilute hydrofluoric acid treatment after the contact hole is formed. As a result.

It is possible to prevent short-circuit accidents between the capacitor electrode and the gate electrode of the MOS transistor and an increase in leakage current. Furthermore, according to this first method, since the lower capacitor electrode is formed thickly by a laminated film of two layers of conductor films, when this is patterned, the area of the capacitor formed on the side surface becomes large, and a large cell capacitance can be obtained. I can do it.

According to the second method, the second insulating film is deposited after forming the first insulating film, which becomes an interlayer insulating film, and before forming the contact hole. Even if a pinhole is formed in the second insulating film, it is filled with the second insulating film, thereby preventing a short-circuit accident between the capacitor electrode and the gate electrode of the MOS transistor. In particular, if the first insulating film and the second insulating film are made of different materials, etching of the first insulating film can be effectively prevented by dilute hydrofluoric acid treatment after forming the contact hole. For example, such an effect can be expected by using a CV D Si O2 film as the first insulating film and a CVSi3N4 film as the second insulating film.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of the DRAM cell structure according to an embodiment of the present invention. Second
Figures (a) to (f) are cross-sectional views showing the DRAM cell manufacturing process according to the first method for obtaining this structure. This DRA
The M cell will be explained according to the manufacturing process as shown in FIG. 2(a).

An element isolation oxide film 2 is formed on a p-type silicon substrate 1 by, for example, selective oxidation. Next, as shown in FIG. 2(b), a gate oxide film 3 is thermally oxidized to form a gate oxide film 3 of about 150 layers, and a first layer polycrystalline silicon film is deposited and patterned to form a gate electrode 4 (4).

4□) is formed, and n-type i5+, 52, which is a source and drain diffusion layer, is formed by ion implantation of impurities. Thereby, a MoS transistor of the memory cell is obtained.

As shown in FIG. 2, the gate electrodes 4 are continuously arranged in one direction of the memory cell array and serve as word lines. After this, as shown in FIG. 2(C), a VDSi02S (first insulating film) 6, which will become an insulating film between WJ:1, is deposited on the entire surface.
Next, a second layer polycrystalline silicon film 71 is deposited on the entire surface as a first conductive film to become a part of the lower capacitor electrode by about 3,000 layers. Thereafter, as shown in FIG. 2(d), a contact hole is opened to bring the capacitor electrode into contact with the n-type layer 5, and a dilute hydrofluoric acid treatment is performed to form the second conductive film that will become the remainder of the lower capacitor electrode. Then, a third layer polycrystalline silicon film 72 is deposited over the entire surface. And these polycrystalline silicon films 7, . 72 laminated films are buttered and the second
As shown in Figure (e), a lower capacitor electrode 7 is formed. Thereafter, as shown in FIG. 2(f), a capacitor insulating film 8 is formed on the surface of the lower capacitor electrode 7 by thermal oxidation.
A fourth conductor film as a third conductor film for forming a capacitor.
A layered polycrystalline silicon film is deposited and patterned to form an upper capacitor electrode 9 so as to cover the lower capacitor electrode 7. Finally, the entire surface is covered with a CV D Si 02 film 10 (second insulating film), a contact hole is made in this, and a dilute hydrofluoric acid treatment is performed to form a bit line 11 in contact with the n-type layer 52. do.

According to this embodiment, before opening a contact hole in the CVD5 i 02 film 6, which is an interlayer insulating film on a substrate on which a MOS transistor is formed, a polycrystalline silicon film 71, which will become a part of a capacitor electrode, is formed in advance. is forming. Therefore, during the dilute hydrofluoric acid treatment after opening the contact hole, this polycrystalline silicon film 7 serves as a mask to prevent etching of the CVDSiO2 film 6, thereby preventing the generation of pinholes. As a result, a highly reliable DRAM can be obtained.

In addition, a two-layer polycrystalline silicon film 7 is formed on the lower capacitor electrode.
．． , 72 laminated films are used, but due to their thickness, the area of the capacitor on the side surface can be increased when patterned, and a large capacitor capacity can be obtained. For example, if the thickness of two layers of polycrystalline silicon films is the same, the side surface area can be twice that of a single layer.
Overall, the cell capacity can be increased by about 1.3 to 1.4 times.

FIGS. 3(a) to 3(f) show D of the embodiment according to the second method.
FIG. 3 is a cross-sectional view showing the manufacturing process of a RAM cell. Figure 3 (a
), an element isolation oxide film 22 is formed on a p-type silicon substrate 21, a gate electrode 24 is formed via a gate insulating film 23 as shown in FIG. 3(b), and impurity ions are implanted. An n-type layer 25, which is a source and drain diffusion layer, is formed by the following steps. Thereafter, as shown in FIG. 3(c), a CVD5i02 film (first insulating film) 26 is deposited on the entire surface. The CVSiO2 film 26 is then heat treated in a 200 g gas atmosphere and etched for about 1 minute with a buffered hydrofluoric acid solution to slightly etch the surface of the CVSiO2 film 26 and make one surface smooth. Next, as shown in FIG. 3(d), a CVD5 t3N4 film (second insulating film) 27 is deposited over the entire surface by about 200 people. Thereafter, the laminated film of the 5i02 film 26 and the Si3N4 film 27 is selectively etched to form a contact hole for the n-type layer 251 as shown in FIG. 3(e). After performing dilute hydrofluoric acid treatment, as shown in FIG. 3(f), a lower capacitor electrode 28 is formed using a second layer polycrystalline silicon film, and a capacitor insulating film 29 is formed using thermal oxidation. An upper capacitor electrode 30 is formed using a layered polycrystalline silicon film.

Finally, the entire surface is covered with a CV D Si O2 film (third insulating film) 31, contact holes are made, and bit lines 32 are provided.

According to this embodiment, the CVD5i02 film 26 serves as an interlayer insulating film covering the substrate on which the MOS transistor is formed.
The surface is further CVDed before forming contact holes in the
5 i3 Covered with N4 film 27. Therefore, it is possible to prevent the generation of pinholes in the interlayer insulating film due to planarization treatment or hydrofluoric acid treatment after contact hole formation, and it is possible to obtain a DRAM having a stacked capacitor cell structure with high reliability and high yield.

In the embodiment shown in FIG. 3, the first insulating film is CVD5i0
2 films, and the second insulating film to protect it is CVD.
The reason for using the 5i3N4 film is that unnecessary etching of the interlayer insulating film can be effectively prevented by combining different materials with different etching characteristics. Combinations of other insulating film materials can also be appropriately selected. Also, these first. The effects of the present invention can also be obtained when the same type of material is used for the second insulating film. In other words, even if pinholes are formed by flattening the first insulating film, by depositing a second insulating film made of the same material before forming the contact hole, the problem caused by the pinholes can be eliminated. This is because short circuit accidents and increases in leakage current can be prevented.

[Effects of the Invention] As described above, according to the present invention, short-circuit accidents and increases in leakage current between the gate electrode of a MOS transistor and the strip capacitor electrode laminated thereon can be effectively prevented, thereby improving reliability. In addition, a DRAM having a stacked capacitor structure with improved yield can be obtained. Furthermore, if a conductor film is used as the base film provided under the lower capacitor electrode and is patterned in the same manner as the lower capacitor electrode, it is possible to not only prevent the effects of pinholes but also effectively increase the capacitor capacitance. possible and useful.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of the DRAM structure according to an embodiment of the present invention. FIGS. 2(a) to (f) are cross-sectional views showing the memory cell manufacturing process, and FIGS. 3(a) to (f) are cross-sectional views showing the memory cell manufacturing process of the example according to the second method. be. DESCRIPTION OF SYMBOLS 1... P-type silicon helicon substrate, 2... Element isolation oxide film, 3... Gate insulating film, 4... Gate electrode. 5...n-type layer (source, drain diffusion layer). 6...CV D Si O2 film (first insulating film). 71...First conductor film (second layer polycrystalline silicon film). 73...Second conductor film (third layer polycrystalline silicon film). 7... Lower capacitor electrode, 8... Capacitor insulating film. 9... Upper capacitor electrode (third conductor film, fourth layer polycrystalline silicon film), 10... CVD5i02 film (second layer)
(insulating film), 11...bit line, 21...p-type silicon substrate, 22... element isolation oxide film. 23... Gate insulating film, 24... Gate electrode. 25...n-type layer (source, drain diffusion layer). 26...CVD5i02 film (first insulating film). 27-CV D Si 3 N 4 film (Second Destruction 1!
film). 28... Lower capacitor electrode (second layer polycrystalline silicon film), 29... Capacitor insulating film, 30... Upper capacitor electrode (third layer polycrystalline silicon film). 31-CV D Si O2 film (third insulation 1). 32...Bit line. Applicant's agent Patent attorney Takehiko Suzue

Claims (6)

[Claims] (1) A MOS transistor formed on a semiconductor substrate,
A memory cell is constructed of a capacitor stacked on a substrate on which this MOS transistor is formed via an insulating film, and a lower capacitor electrode contacts the source or drain diffusion layer of the MOS transistor through a contact hole formed in the insulating film. 1. A semiconductor memory device comprising: a base film on the outside of the contact hole on the insulating film under the lower capacitor electrode. (2) The semiconductor memory device according to claim 1, wherein the base film is a conductive film, and is patterned simultaneously with the lower capacitor electrode to become a part of the lower capacitor electrode. (3) The semiconductor memory device according to claim 1, wherein the base film is an insulating film made of a different material from the insulating film. (4) A method for manufacturing a semiconductor memory device in which a memory cell is configured by a MOS transistor and a capacitor, which includes a step of forming a MOS transistor on a semiconductor substrate on which an element isolation region is formed, and a step of forming a MOS transistor on the substrate on which the MOS transistor is formed. A process of covering with a first insulating film and then laminating a first conductive film that will become a part of the lower capacitor electrode, and forming a contact hole in the laminated film of the first insulating film and the first conductive film. Then, a step of depositing a second conductor film that contacts the source or drain diffusion layer of the MOS transistor and becomes the remainder of the lower capacitor electrode, and simultaneously patterning the first and second conductor films to form the lower capacitor electrode. forming an upper capacitor electrode made of a third conductive film on the surface of the formed lower capacitor electrode via a capacitor insulating film; and forming a second insulating film on the substrate on which the upper capacitor electrode is formed. 1. A method of manufacturing a semiconductor memory device, comprising the steps of: covering the semiconductor memory device with a MOS transistor and forming a contact hole therein to form a bit line in contact with a drain or source diffusion layer of a MOS transistor. (5) A method for manufacturing a semiconductor memory device in which a memory cell is configured by a MOS transistor and a capacitor, which includes the steps of forming a MOS transistor on a semiconductor substrate on which an element isolation region is formed, and forming a semiconductor memory device on the substrate on which the MOS transistor is formed. A process of covering with a first insulating film and then laminating a second insulating film, and forming a contact hole in the laminated film of the first and second insulating films to contact the source or drain diffusion layer of the MOS transistor. forming a lower capacitor electrode on the surface of the formed lower capacitor electrode via a capacitor insulating film; and covering the substrate on which the upper capacitor electrode is formed with a third insulating film. A method of manufacturing a semiconductor memory device, comprising the steps of: forming a contact hole therein to form a bit line in contact with a drain or source diffusion layer of a MOS transistor. (6) The method of manufacturing a semiconductor memory device according to claim 5, wherein the second insulating film is made of a material different from that of the first insulating film.