JPH0260162A - Semiconductor memory - Google Patents

Abstract

PURPOSE:The stop of a contact part of a bit wire with a lead-out electrode is made small so as to prevent the disconnection due to the step by a method wherein the lead-out electrode is formed thoroughly surrounding a flat insulating film provided between a pair of gate electrodes. CONSTITUTION:A bit wire 16 formed of aluminum or the like is connected to the part of a lead-out electrode 11b which covers the upside of a flat insulating film 17b, where the lead-out electrode 11b surrounds the flat lead-out electrode 11b provided between a pair of gate electrodes 4 and 5. Therefore, the contract part of the electrode 11b with the bit wire 16 is made higher in level by the thickness of the film 17b, so that the step of the contact part of the bit wire 16 made smaller. And, the thicker the film 17b is made, the smaller the step of the contact part of the bit wire 16 becomes. By these processes, the disconnection caused by the step of a bit wire can be prevented.

Description

[Detailed description of the invention] The present invention will be described in the following order.

A. Industrial field of application B0 Overview of the invention C0 Prior art [Fig. 6] D1 Problem to be solved by the invention E0 Means for solving the problem F3 Effect G. Embodiment ``Fig. Figure 5 H1 Effects of the Invention (A, Industrial Application Field) The present invention relates to a semiconductor memory, in particular, a semiconductor memory in which a memory cell is composed of a capacitive element and a switching transistor, and the capacitive element is connected to a lower electrode facing each other with a dielectric film interposed therebetween. Electricity is formed between the semiconductor region shared by the pair of switching transistors and the bit line through a lead-out electrode between the gate electrodes of the pair of switching transistors. The present invention relates to a semiconductor memory having physical connections.

(B. Summary of the Invention) The present invention provides the above-mentioned semiconductor memory for reducing the level difference between the bit lines, especially the level difference at the connection portion via the extraction electrode with the semiconductor region shared by a pair of switching transistors. It is characterized in that the electrode is formed so as to completely surround a flattened insulating film provided between the gate electrodes of a pair of switching transistors.

(C, Prior Art) [Figure 6] As one type of dynamic RAM, a lower electrode made of polycrystalline silicon and an upper electrode made of polycrystalline silicon are placed opposite to each other on a semiconductor substrate with a dielectric film in between. There is a laminated capacitor type that consists of a capacitive element for information storage, such as the Sem1conductor W.
orld 1988.2 (Press Journal) 3
The structure is introduced in ``The Future of 4M and 16M DRAMs - Stacked Capacitors and Channel Capacitors''. This type of multilayer capacitor is more resistant to soft errors than the trench type capacitor, in which a trench is dug in the semiconductor substrate and a capacitive element for information storage is formed there, and the area of the diffusion layer formed in the semiconductor substrate is small. It has the advantage of being easy to use, and development in this regard is very active.

? Figure S6 is a sectional view showing a typical example of a stacked volumetric dynamic RAM.

In the drawing, 1 is a p-type semiconductor substrate, 2 is a field insulating film formed by selective oxidation, 3 is a gate oxide film, and 4 is a p-type semiconductor substrate.
5 is a first layer polycrystalline silicon film, 5 is a high melting point metal (for example, tungsten) silicide film, and the high melting point silicide film 5 and the first layer polycrystalline silicon film 4 form a word line called polycide. (gate electrode). 6
7 and 8 are n-type scattering layers formed on the surface of the semiconductor substrate 1, and are arranged side by side. - Forms the source and drain of a pair of switching transistors. Among them, the diffusion layer 8 is a central diffusion layer shared by a pair of switching transistors and is connected to a bit line, and the diffusion layers 7. There is.

9 is an interlayer insulating film covering the switching transistor, l
Note: Oa and 10b are contact holes that expose the surface of the diffusion layer 7.8 selectively formed in the interlayer insulating film 9, lla and llb are the second polycrystalline silicon layers,
lla constitutes the lower electrode of the capacitive element for information storage, and fl
b constitutes an extraction electrode and a contact hole lOa.

It is connected to the diffusion layer 7.8 through 10b.

12 is a dielectric film formed on the surface of the lower electrode 11a;
In the drawing, it is shown as a thick solid line, but for example, SiO□ film and 5i
It has a three-layer structure of Njli and SiO□. Reference numeral 13 denotes an upper electrode facing the lower electrode 11a with the dielectric film 12 interposed therebetween, and is made of a third polycrystalline silicon layer. 1
4 is an interlayer insulating film on the upper side 'N, pole 1 and upper layer 3, and 15 is the above-mentioned extraction electrode f formed on the interlayer insulating film 14.
A contact hole 16 exposing the surface of lb is a bit line made of aluminum passing over the interlayer insulating film 14,
Extract the electrode 11 through the contact hole 15. b
It is connected to the.

(D. Problem to be Solved by the Invention) By the way, in such a conventional stacked capacitor type dynamic RAM, the distance between the interlayer insulators 11Q9 and 9 covering the gate electrode is narrow, and the step of the interlayer insulating film 9.9 is steep. The kneading upper side electrode 11a is
The capacitance per occupied area of the capacitive element composed of the dielectric film 12 and the upper electrode 13 can be increased. and,
Increasing the capacitance per occupied area of a capacitive element is essential for increasing memory integration and storage capacity. 1
However, the steeper the step in the interlayer insulating film 9.9, the steeper the step in the portion of the bit line 16 connected to the lead-out electrode 11b becomes, and the more likely breakage in the bit line 16 will occur. A problem arises.

The present invention has been made in view of the above circumstances, and it is possible to reduce the step difference at the contact portion between the bit line and the lead-out electrode.
One purpose is to reduce the capacitance per unit occupied area of the capacitive element without decreasing it, and another purpose is to go further and increase the capacitance per unit occupied area of the capacitive element. purpose.

(E. Means for Solving the Problems) In order to solve the above problems, the first semiconductor memory of the present invention has a take-out electrode that completely surrounds the flattened insulating film between the gate electrodes of a pair of switching transistors. It is characterized by being formed as follows.

A second semiconductor memory of the present invention is that in the first semiconductor memory described above, the lower electrode of the capacitive element is formed so as to surround the planarized insulating film, and the upper electrode is formed on the lower electrode. Features.

In the semiconductor memory i3 of the present invention, in the first type, the lower electrode of the capacitive element is formed so as to be folded back to the surface periphery through the side surface of the first electrode, and a part of the upper electrode is further lowered. It is characterized in that it overlaps the folded portion of the side electrode.

(F. Effect) According to the first semiconductor memory of the present invention, the bit line only needs to be connected to the portion located above the extraction electrode surrounding the planarized insulating film, so that the bit line is in contact with the extraction electrode. The step difference in the portion can be reduced by the thickness of the planarizing insulating film.

According to the second semiconductor memory of the present invention, since the lower electrode and the upper electrode face each other on the side surface of the planarized insulating film, the capacitance can be increased without increasing the area occupied by the capacitive element. It is possible to increase the amount.

According to the third semiconductor memory of the present invention, the peripheral edge part of the lower electrode passes through the side surface of the upper electrode and is further folded back onto the −F side electrode, and a part of the upper electrode overlaps with the folded part. The area facing the electrodes can be increased without increasing the occupied area, and the capacitance of the capacitive element can be increased.

(G. Embodiment) [FIGS. 1 to 5] Hereinafter, the semiconductor memory of the present invention will be described in detail according to the illustrated embodiment.

FIG. 1 is a sectional view showing one embodiment of the semiconductor memory of the present invention. This embodiment has parts in common with the conventional example shown in FIG. 6, and since the common parts have already been explained, they will not be explained in detail, but only the characteristic parts will be explained.

17a and 17b are flattening insulating films made of As5G or BPSG, etc.
1b. Then, lower side electric N7iAl
1a, the extraction electrode 11b is a flattened insulating film 17a,
It extends from the lower side of 17b along the side surface, and when it reaches the upper side, it is folded inward to flatten the insulation II! 21? a, 17b are completely covered from above.

That is, the lower electrode 11a and the extraction electrode ttb completely surround the planarization insulating films 17a and 17b.

Dielectric material of capacitive element! 212 is formed on the surface of a portion corresponding to the side surface of the planarizing insulating film 17 of the lower electrode Si11a surrounding the planarizing insulating film 17a, and on the surface of a portion corresponding to the top surface of the planarizing insulating film 17; It is formed to face the negative side electrode 11a with the dielectric film 12 interposed therebetween. Therefore, the upper type! 413 and the )° side electrode 13a facing each other with the dielectric film 12 interposed therebetween, the electrode facing area increases by the area of the side surface of the flattened insulating film 17a compared to the conventional capacitive element, with the same occupied area.

Therefore, it becomes possible to increase the electrostatic capacity without increasing the area occupied by the capacitive element. Then, the planarization insulating film 17a
The capacitance can be increased as the thickness of the film is increased.

Further, the bit line 16 made of aluminum or the like is connected to a portion of the extraction electrode ttb surrounding the planarizing insulating film 17b that covers the upper surface of the planarizing insulating film 17b.
(strictly speaking, the thickness of the flattening insulating film 17b plus the thickness of the lead-out electrode 11b) increases the height of the contact with the lead-out electrode 11b, which makes the step at the contact portion of the bit line 16 smaller than before. It can also be made smaller, making it less likely that breakage will occur. The thicker the planarization insulating film 17b is, the more the bit line 1
The step difference in the contact portion of No. 6 can be reduced.

FIGS. 2A to 2A are cross-sectional views showing the method of manufacturing the semiconductor memory shown in FIG. 1 in the order of steps, and the method of manufacturing the semiconductor memory will be explained with reference to these figures.

(A)-'l' = Field insulation 115I2 is formed by selectively oxidizing the conductor substrate 1, and gate oxidation [3 is formed by heating and oxidizing the surface of the element formation region of the semiconductor substrate 1, first layer 1] A polycrystalline silicon film 4 and a high melting point silicide film 5 are formed, this 1P24.5 is patterned to form a gate electrode (word line), and a side wall 6 made of silicon oxide is formed on the side surface of the gate electrode 4.5. After that, ions are implanted to form a diffusion layer 7.8 (by implanting impurity ions before forming the sidewall 6, a low impurity concentration region integrated with the diffusion layer 7.8 is also formed). ).

Next, interlayer insulation 11! (thickness of 1000 Å or more) 9 is formed, contact holes 10a and 10b are formed by selectively etching this, and then a second polycrystalline silicon layer 11 is formed by LP (low pressure) CVD. . FIG. 2(A) shows the state after the polycrystalline silicon layer 11 is formed. Until now, conventional static RAM
The same is true for manufacturing.

(B) Next, a silicon oxide film SiO Thermal
After flattening the surface, apply 5 on the surface.
00 to 1000 5i02 films are formed to obtain a flattened insulating film 17. FIG. 2(A) shows the state after the planarization insulating film 17 is formed.

(C) Next, a third polycrystalline silicon layer 11' is formed by low pressure CVD, and the resistance of slave 1-1' is reduced by ion implantation or pre-deposition of impurities. After that, on the surface of the polycrystalline silicon layer 11', a Sin film 1 having a thickness of 500 to 1000 nm is formed, which will serve as a stopper in the anisotropic etching process for later sidewall formation.
8, and then beep! - Form resists IIQ t 9 a and 19b to serve as a mask during etching to separate the line connection portion and the capacitive element portion.

FIG. 2(C) shows the state after the resist films 19a and 19b are formed.

(D) Next, using the resist rfA19a, 19b as a mask, anisotropic etching such as RIE is performed to form a 5in2
Membrane 18. The third layer [j of the polycrystalline silicon layer 11', the planarization insulating WA 17, and the second layer of the polycrystalline silicon layer 11 are etched, and then the resist films 19a and 19b are removed. FIG. 2(D) shows the state after removing the resist films 19a and 19b.

(E) Next, as shown in Figure 1), a polycrystalline silicon film (
Thickness too much - F) 20 by CVD 1. : Form more.

(F) Next, as shown in FIG. 2F, the entire polycrystalline silicon layer 20 is subjected to an anisotropic etching process by RIE or the like. Then, the polycrystalline silicon layer 20 remains as a sidewall on the side surfaces of the planarized insulating films 17a and 17b, and this sidewall 20 forms the lower electrodes 11a and 11a separated by the etching process shown in FIG. 2(D). ', and the extraction electrodes flb and 11'b, respectively. As a result, the flattening insulating films 17a, 17b are completely surrounded by the lower electrodes 11a, 11'b, 20 and the extraction electrodes 11b, 11'b, 20 in a box shape.

Hereinafter, for convenience, the box-shaped polycrystalline silicon including the lower electrodes 11a, 11'a and the sidewall 20 connecting these 11a and 11'a will be simply referred to as the lower electrode IIj11a. Extraction electrodes 11b, ll'b and l
The same applies to the sidewall 20 connecting lb and 11'b.

(G) Next, after removing the stopper Sin film 18, a dielectric film 12 is formed as shown in FIG. 2(G). The dielectric film 12 is, for example, S 102 /S i
It has a three-layer structure of N/S f O2.

(H) Next, a fourth polycrystalline silicon layer is formed to completely fill the space between the flattened insulating films i-17b and form a wiring film, and this layer is patterned to form an upper surface. Electrodes 13 are formed. FIG. 2 (H) shows the upper electrode 13.
The state after formation is shown.

(1) Next, an interlayer insulating film 14 is formed, and the interlayer insulating film 1
A contact hole 15 for connecting the bit line and the extraction electrode flb is formed in 4, and the portion of the dielectric film 12 exposed to the contact hole 15 is removed to expose the surface of the extraction electrode 11b. FIG. 2(1) shows a state in which the surface of the extraction electrode 11b is exposed.

Thereafter, a bit line 16 made of aluminum is formed so as to be in contact with the surface of the extraction electrode 11b through the contact hole 15, thereby obtaining a semiconductor memory as shown in FIG.

Incidentally, in the manufacturing method shown in FIG.

Dielectric 11rA1? During the anisotropic etching to form the sidealls 20 made of polycrystalline silicon on the side surfaces of a and 17b, an SiO,I layer 18 was formed as a stopper to prevent the polycrystalline silicon layer 11' from being etched. A manufacturing method that does not form such a stopper can also be considered as a modification.

FIGS. 3A to 3C are cross-sectional views showing such a manufacturing method in the order of steps.

(A) After formation of the third polycrystalline silicon layer 11', resist Il! is applied as shown in FIG. 3(A) without providing a stopper. 19a, form 1゛9b.

(B) Next, etching is performed using the resist films 19a and 19b as masks, and then the resist films 19a and 19b are removed to obtain the state shown in FIG. 3(B).

(C) Thereafter, a polycrystalline silicon layer 20 for sidewall formation is formed as shown in FIG.

The manufacturing method other than this is completely the same as the manufacturing method shown in FIG. According to the manufacturing method shown in FIG. 3, it is not necessary to attach a stopper and remove it later.
Also, during etching to remove the stopper, the interlayer insulating film 9
It has the advantage that there is no risk of corrosion. Instead, care should be taken to ensure that the thickness of the polycrystalline silicon layer 11' does not become less than a predetermined thickness due to etching for sidewall formation (for example, the thickness of the polycrystalline silicon layer 11'
It is necessary to take some consideration (such as forming the film thicker).

FIG. 4 is a sectional view showing a second embodiment of the semiconductor memory of the present invention.

This embodiment differs from the embodiment shown in FIG. 2 in that the extraction electrode 11b is formed so as to surround the flattening insulating film 17b, and the bit line 16 is formed so as to be in contact with the extraction electrode 11b on its upper surface. have in common. Therefore, the height at which the bit line 16 makes contact with the output voltage 111b is increased by approximately the thickness of the flattened insulating film 17b, and the step difference at the contact portion can be made smaller than before, making it difficult to cause step breakage, etc. In that respect, it is the first
This is common to the embodiment shown in the figure.

Incidentally, this embodiment differs from the embodiment shown in FIG. 1 in that the sensitive element does not have a flattening insulating film.

That is, in this embodiment, the lower electrode 11a of the capacitive element has a shape that is folded back by an appropriate amount from the lower side of the upper electrode 13 to the upper surface via the side surface. A portion of the upper electrode 13 overlaps the portion of the lower electrode 11a that is folded back onto the upper surface of the upper electrode 13 through the side surface of the upper electrode 13. Therefore, the upper electrode 11a and the upper mold 1il can be connected without increasing the area occupied by the capacitive element.
The area facing i13 (of course facing through the dielectric film 12) can be increased, and the capacitance can be increased.

FIGS. 5A to 5F are cross-sectional views showing the method for manufacturing the semiconductor memory shown in FIG. 4 in order of steps.

(A) Z2 In the same way as shown in Figures (A) to (C),
The process is continued until resist films 19a and 19b are formed on SiO□@18 forming a stopper on the surface of the polycrystalline silicon layer 11'. FIG. 5(A) shows the resist film 1.
The state after formation of 9a and 19b is shown.

(B) Next, the polycrystalline silicon layer 11', flattening insulating film 17, etc. are etched using the resists 11Q19a, 19b as masks, and then the resist films 19a, 19b are etched.
Remove 9b. FIG. 5(B) shows a resist film 19a,
The state after removing 19b is shown.

(C) Next, side walls made of polycrystalline silicon are formed on the side surfaces of the planarized insulating films 17a and 17b, and then the 5in2 film 18 serving as a stopper is removed. FIG. 5(C) shows the state after the SiO□ film 18 has been removed. Up to this point, there is no difference from the manufacturing method shown in FIG.

(D) Next, a resist film 19 is formed to completely cover the upper surface of the extraction electrode 11b and to cover the peripheral edge of the upper surface of 1H11a in the lower mold. Then, by etching the upper portion (ll'a) of the lower electrode 11a using this resist Iv; 119 as a mask, the surface of the planarized insulating film 17b is exposed. Then, by wet etching using, for example, hydrofluoric acid HF, the flattened insulating film 17a is completely removed so as to hollow it out. Then, a cavity surrounded by the lower electrode 11a is created. FIG. 5(D) shows the state after this wet etching.

(E) Next, as shown in (E) of the same figure, an interlayer insulating film 12 is formed by oxidation and CvD.

(F) Next, as shown in FIG.
D and then patterned.

After that, the semiconductor memory shown in FIG. 4 can be obtained by forming interlayer insulation @14, forming contact holes 15, and forming bit lines 16 in the same way as in the manufacturing method shown in FIG. 2. .

(H, Effects of the Invention) As described above, in the first semiconductor memory of the present invention, the take-out electrode passes through the planarized insulating film formed between the gate electrodes from the back side of the film to the side surface thereof. It is characterized by being formed so as to be surrounded so as to reach. Therefore, the step difference at the contact portion of the bit line with the lead-out electrode can be reduced by the thickness of the planarizing insulating film.

A second semiconductor memory of the present invention is that in the first semiconductor memory described above, the lower electrode of the capacitive element is formed so as to surround the planarized insulating film, and the upper electrode is formed on the lower electrode. This is a characteristic feature.

Therefore, according to the second semiconductor memory of the present invention, since the opposing portion of the lower electrode and the upper electrode can be formed also on the side surface of the planarized insulating film, the area occupied by the capacitive element t can be prevented from increasing. The capacitance can be increased without any increase in capacitance.

A third aspect of the semiconductor memory of the present invention is - in the first aspect, the lower electrode of the capacitive element is formed so as to be folded back over the peripheral edge through the side surface of the upper electrode, and further a part of the upper electrode is formed. It is characterized by overlapping the folded part of the lower electrode. Therefore, according to the third semiconductor memory of the present invention, the peripheral edge of the lower electrode is further folded back onto the upper electrode through the side surface of the upper electrode, and the -
Since the portions overlap, the area facing the electrodes can be increased without increasing the occupied area, and the capacitance per unit occupied area of the capacitive element can be increased.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a first embodiment of the semiconductor memory of the present invention, FIGS. 2(A) to (1) are cross-sectional views showing the manufacturing method of the semiconductor memory shown in FIG. 1 in order of steps, and FIG. (A) to (C) are cross-sectional views showing another manufacturing method in the order of steps; FIG. 4 is a cross-sectional view showing a second embodiment of the semiconductor memory of the present invention;
Figures (A) to (F) are cross-sectional views showing the manufacturing method of the semiconductor memory shown in Figure 4 in order of steps, and Figure 6 is a cross-sectional view showing a conventional example of the semiconductor memory. 1 a, 1 b, 2 fist, 7a. - Lower electrode, - Extraction electrode, flattening insulating film, 13... Upper electrode, bit line, 7b... Flattening insulating film. Explanation of symbols 4.5...Gate electrode, 8...Semiconductor region shared by a pair of switching transistors, qF Dimensional manufacturing 7i Nagisairo Koji 1 car V@ side view cross section of conventional example Figure 6~

Claims (3)

[Claims] (1) A memory cell is constituted by a capacitive element and a switching transistor, and the capacitive element is formed by a lower electrode and an upper electrode facing each other with a dielectric film in between so as to overlap with the gate electrode of the switching transistor, and the pair of switching transistors In a semiconductor memory in which a semiconductor region shared by the pair of switching transistors and a bit line are electrically connected via a lead-out electrode between gate electrodes of the transistors, the lead-out electrode is provided between the gate electrodes. A semiconductor memory characterized in that it is formed by surrounding a flattened insulating film from the back side to the front side of the same. (2) The lower electrode of the capacitive element is formed by surrounding a flattened insulating film from the back surface to the side surface to the front surface, and the upper electrode of the capacitive element is formed on the lower electrode. Semiconductor memory according to claim (1) characterized in (3) The lower electrode of the capacitive element is folded back to the peripheral surface through the side surface of the upper electrode, and a part of the upper electrode covers the folded part of the lower electrode. The semiconductor memory according to claim (1), characterized in that