JPS60206049A - Semiconductor ic having multilayer interconnection - Google Patents

Abstract

PURPOSE:To obtain the titled device having the multilayer interconnection of good design efficiency by a method wherein the first and second wiring layers are provided on a semiconductor substrate via insulation layer, and the first electrode layer is divided into the first region for wiring circuit elements and the second region for cross-wiring the second electrode layer; then, through holes for connection of both the electrode layers are provided at fixed positions. CONSTITUTION:The first and second electrode layers 13, and 15 are provided on the semiconductor substrate 11 via insulation layers 12 and 14. The first electrode layer 13 is divided into the first region 16 for wiring circuit elements and the second region 17 for cross-wiring the second electrode layers 15. The electrode layer 13 of the region 17 is extended and the electrode layers 15 are extended, resulting in the orthogonal arrangement of both. The through holes to connect the first electrode layer 13 of the second region 17 to the second electrode layers 15 are provided by suitable alienation by bending the second electrode layers 15 along the first electrode layer 13 of the second region 17. This manner enables the production of the titled device having the multilayer interconnection of good design efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having multilayer wiring.

(b) Prior Art Recently, in order to improve the degree of integration of semiconductor integrated circuits, a multilayer wiring structure has been adopted to provide flexibility to the wiring and to increase the degree of integration of circuit elements. For such a multilayer wiring structure, polyimide was used as an interlayer insulating film1.
No. 871 is known.

Figure 1 shows an integrated circuit incorporating a conventional two-channel amplifier circuit.
The arrangement of the C pattern is shown. Power supply (Vac) lines are placed on the left and right in the center of the pellet, and the three
A ground (GND) line is placed around the sides.

There are 1 channel and 2 channels on the upper and lower sides of the power supply line, respectively.
Circuit elements such as transistors, resistors, diodes, etc., which form the channel amplifier circuit, are formed on a semiconductor substrate (1).

Then, a first insulating film (2) made of silicon oxide is formed on the substrate.
) A first electrode layer (3) made of vapor-deposited aluminum is formed on top of the first electrode layer (3) to connect circuit elements to form an amplifier circuit for each channel. A power supply line and a ground line indicated by diagonal lines are also formed of the first electrode layer (3). Next, the second insulating film (4) for interlayer insulation is applied to the first insulating film M(2).
A second electrode layer (5) is formed from vapor-deposited aluminum thereon. The second electrode layer (5) is A-+A, B-
) Overlapping with the first electrode layer (3) so as to be connected to the first electrode layer (3) via through holes such as B, c-+c, D→D and E→E to constitute a predetermined circuit. It is provided. In particular, semiconductor integrated circuits with built-in two-channel amplifier circuits are often connected to BTL to increase power, and often require detection signals from other channels such as thermal protection circuits, overvoltage detection circuits, ASO protection circuits, etc. . Therefore, secondly, it is necessary to cross between the polar layers (5), and in this case, the first! C cross wiring is performed using the pole layer (3). As shown in FIG. 2, this cross wiring structure is such that one second electrode layer (5) is tunneled by the first electrode layer (3), and the other second electrode layer (5) is tunneled by the second insulating film (4). )
is insulated by

However, in the multilayer wiring structure to be pasted, basically the first electrode layer (3) is used to connect each circuit element as much as possible, and wiring is done almost on the entire surface.
The basic design rule is to wire those that cannot be wired using the second electrode layer (5). Therefore, when cross-wiring the second electrode layer (5), it is necessary to secure a space for the tunnel in the first electrode layer (3) in advance, which complicates the design and requires less space for the tunnel. Therefore, there may be cases where the chip area must be increased.

(c) Purpose of the Invention The present invention has been made in view of the point in time, and an object of the present invention is to realize a semiconductor integrated circuit having multilayer wiring with high design efficiency.

B) Structure of the Invention The semiconductor integrated circuit of the present invention comprises a semiconductor substrate on which desired circuit elements are formed, a first electrode layer wired on a first insulating layer provided on the surface of the substrate, and the first insulating layer. In a semiconductor integrated circuit having a multilayer wiring including a second electrode layer wired on a second insulating layer covering the first electrode layer, the first electrode layer is a first region where the circuit elements are wired. The second electrode layer is divided into a second region in which cross wiring of the pole layer is performed, and the first electrode layer arranged parallel to the second region and the second electrode layer extending parallel are arranged so as to be orthogonal to each other. The through-holes in the first electrode layer and the second electrode layer in the second region are formed so that the second electrode layer is bent along the first electrode layer in the second region and provided with an appropriate distance between them. has been done.

(E) Embodiment An embodiment of a semiconductor integrated circuit having multilayer wiring according to the present invention will be described with reference to FIGS. 3 to 5. Figure 3 is 2
It shows the arrangement of an IC pattern incorporating a channel amplifier circuit.

A plurality of island regions are provided on the semiconductor substrate (11), and circuit elements such as transistors, resistors, diodes, etc. are integrated therein. Each circuit element incorporates what is necessary to form a two-channel amplifier circuit.

The first electrode layer (13) is a feature of the present invention;
6) and a second region a force. The first region (10 connects the circuit elements to each other to form a two-channel amplifier circuit), and the second region αη connects the second electrode layer (151) to the cross wiring.Specifically, the central part of the pellet The power supply (Vcc) line is arranged in a bifurcated manner on the left and right, forming the power supply line for each channel.Ground (GND) lines are arranged around the three sides of the bellet. The area surrounded by the power supply line and the ground line becomes a first area α6), and connects the amplifier circuit of each channel.The second area αn is formed in the area surrounded by the power line. Therefore, the first region (16), which occupies most of the area of the bellet, is used as a region for connecting circuit elements to form each channel amplifier circuit, and the second region (17) is used as a region for connecting circuit elements to form each channel amplifier circuit.
! It is good to have the minimum area necessary for cross wiring of the pole layer (151).In other words, it is good to have the minimum area necessary for cross wiring of the pole layer (151). are placed in parallel at regular intervals.

The second electrode layer 05) serves as an interlayer insulating material made of polyimide or the like (extends over the second insulating film 0, and is connected to the first electrode layer via a through hole).

A two-channel amplifier circuit requires a thermal protection circuit, an overvoltage detection circuit, an ASO protection circuit, etc. that input detection signals from other channels by using a BTL connection. Therefore, a connection beyond Hennel is required as shown in FIG. The AHA wiring is connected to the first through hole at point A.
After making contact with the electrode layer 3), the second electrode layer 05) is extended in the vertical direction orthogonal to the power supply line to the second area aη of the first electrode layer, where a through-hole is inserted. It is connected to one line for cross wiring in the second region Q71, routed to the right, and connected to the second electrode layer (19) in the vertical direction from point A through a through hole at the point where it intersects with the second electrode layer (19). Cage→D is on a straight line in the vertical direction, so it is directly connected without cross wiring.

The feature of the present invention is that the first electrode layer Q3 of the second region (Iη) used for cross wiring extends in parallel, and the second electrode layer (151) also extends in parallel, and the two are orthogonal to each other. As a result, the second electrode layer (15) can be completely connected except on the second area aD (there is no risk of mutual cross wiring), and it is sufficient to extend the second electrode layer (151) in the vertical direction, making the design extremely easy. As for the cross wiring, it is sufficient to connect it through a through hole at the point where the first electrode layer α9 of the second region (Iη) intersects the second electrode layer (151), and It is only necessary to extend the number of one electrode layer (13) in parallel as required for the cross wiring, and the second region C1
The design of the first electrode layer (13) in 7) is also extremely easy. An even more important point is that any wiring route can always be connected over the shortest distance. This eliminates the need to bend and take a detour around the second electrode layer (wiring can be realized with a minimum area).

Furthermore, the most distinctive feature of the present invention is the position where the through holes are formed. To explain with reference to FIG. 5, the solid line with diagonal lines indicates the first electrode layer (13) of the second region (17),
The dotted line indicates the second electrode layer a51. In the above explanation, a through hole was formed at the intersection of the first electrode layer (13+) and the second electrode layer α9.
51 must be expanded. Specifically 12.5μ
In the first electrode layer (131) with a width of m, a square extension part of 45 μm on a side is provided in the through hole α, and the through hole is formed in a square shape of 12.5 μm on a side, and on top of that, a square extension part of 45 μm on a side is provided. A second electrode layer a8I having a square-shaped extension part (1 (+1) is provided. Therefore, in the present invention, the through holes agJ are appropriately distributed to overlap the extension part α9αj of the first electrode layer αJ and the second electrode layer α9. In Fig. 5, the intermediate first electrode layer (131) and the second electrode layer (131) are arranged to extend rightward from the intersection of the pole layers α9 and through holes 0a.
is formed. In this intermediate first electrode layer α3), the portion where the extended portion u9 (+9) of the first electrode layer Q31 on both sides protrudes is recessed and extends to the right, and the first electrode layer α3) on both sides does not exist. An extended portion (191) of the intermediate first electrode layer (13) is formed in the second region αn.The second electrode layer Q51 extends to the corresponding extended portion (8) of the first electrode layer (8). The intermediate second electrode layer a9 is connected to the intermediate first electrode layer (the first electrode layer α & The extension part (19) is connected via a through hole.

FIG. 4 is a cross-sectional view taken along the line ■-iv in FIG. The mark a is the second electrode layer.

As is clear from FIG. 4, a step occurs in the second insulating film Q4) due to the first electrode layer αJ. When photo-etching the second electrode layer α9, there is a high possibility that the step portion will also be exposed and the second electrode layer Q51 will remain as a bridge.

In particular, when the first electrode layer 0 and the second electrode layer a9 are extended in parallel, short circuits due to bridges are likely to occur. In the present invention, since the second electrode layer a9 and the first electrode layer a9 used for cross wiring are disposed perpendicularly, there is no occurrence of such a bridge, and the second electrode layer tts+ is placed in the direction of the first electrode layer α. It can be placed regardless of the pattern, and wiring density can be improved.

(f) Effects of the Invention According to the present invention, since the space for the cross wiring of the second electrode layer α9 is secured in the second region α7) of the first electrode layer a, the second electrode layer In the first region 6) of a3, only connections between circuit elements need be made, and there is an advantage that the design can be done without worrying about the space for cross wiring.

As a result, the design of the first electrode layer 0 and the second electrode layer a9 can be speeded up, and since it is sufficient to secure the minimum area of the second region an, there is no need to increase the chip area so much. Furthermore, since cross wiring is actively performed in the second region (L″r), two-layer wiring can always be performed with the shortest distance.

Furthermore, by providing through holes at appropriate intervals, the distance between the first electrode layer (13+) on the second region surface is adjusted to the through holes (
It is not necessary to design according to the extension part (11) for 1 gJ, and it can be designed according to the first electrode layer αJ and the second region (17>
area can be reduced. Normally, no circuit elements are provided under the second area (171), so the packaging density of circuit elements can be greatly improved by reducing the size of the second area.

[Brief explanation of the drawing]

FIG. 1 is a top view illustrating a semiconductor integrated circuit having conventional multilayer wiring, FIG. 2 is a cross-sectional view illustrating general loss wiring, and FIG. 3 is a top view illustrating a semiconductor integrated circuit having multilayer wiring according to the present invention. The top view for explanation, Figure 4 is IV-IV of Figure 3.
The line sectional view and FIG. 5 are top views illustrating through-hole connections between the first electrode layer and the second electrode layer in the second region according to the present invention. (11) is a semiconductor substrate, a2 is a first insulating film, (131
& house first electrode layer, I is second insulating film, (15) is second electrode layer, (161 is first region, (17) is second region, (1
81 is a through hole, (1!J is an extension part. Applicant: Sanyo Electric Co., Ltd. and 1 other representative: Patent attorney Shizuka Sano Fuei Figure 4)

Claims (1)

[Claims] (1) A semiconductor substrate on which a desired circuit element is formed, a first electrode layer wired on a first insulating layer provided on the surface of the substrate, and a second insulating layer covering the first insulating layer. In a semiconductor integrated circuit having a multilayer wiring, the first electrode layer is connected to a first region where the circuit elements are wired, and a cross wiring between the second electrode layer and the second electrode layer is provided. The first electrode layer extending in parallel with the first electrode layer arranged in parallel to the second region is arranged so as to directly parallel the second electrode layer, and the first electrode layer in the second region is The electrode layer and the second t!
1. A semiconductor integrated circuit having multilayer wiring, characterized in that through holes in the layers are provided by bending the second electrode layer along the first electrode layer in the second region and appropriately spacing the second electrode layer.