JPS60206048A - Semiconductor ic having multilayer interconnection - Google Patents

Abstract

PURPOSE:To obtain the titled device having the multilayer interconnection of good efficiency by a method wherein the first electrode layer on an insulation layer on a semiconductor substrate is divided into the first and second regions, and the second electrode layer extending each in parallel with the first electrode layer arranged in parallel in the second region is arranged so as to be orthogonal to the first electrode layer via insulation layer. CONSTITUTION:The first electrode layer 13 is provided on the insulation film 12 on the semiconductor substrate 11 and divided into the first region 16 for connection of circuit elements with one another and the second region 17 for cross-wiring the second electrode layer 15 on an insulation film 14. The first electrode layers 13 in the second region 17 are extended in parallel, and the second electrode layers also in parallel, thus making both be orthogonal to each other. This enables the second electrode layers 15 to eliminate the possibility of mutual cross wiring in the part other than the second region 17: it is sufficient that the second electrode layers 15 are extended vertically, and the design becomes facilitated. Cross wirings are connected through through-holes at points of intersection of the electrode layers 15 with the electrode layers 13. This enables the production of the titled device having the multilayer interconnection of good design efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having multilayer wiring.

(b) Prior Art Recently, in order to improve the degree of integration of semiconductor integrated circuits, a multilayer wiring structure has been adopted, and the wiring has a lexicality of 7 to increase the degree of integration of circuit elements. Such a multilayer wiring structure uses polyimide as an interlayer insulating film.
No. 871 is known.

Figure 1 shows an integrated circuit incorporating a conventional two-channel amplifier circuit.
The arrangement of the C pattern is shown. Power supply (VCC) lines are arranged on the left and right in the center of the pellet, and the three
A ground (GND) line is placed around the sides.

There are 1 channel and 2 channels on the upper and lower sides of the power supply line, respectively.
Circuit elements such as transistors, resistors, diodes, etc., which form the channel amplifier circuit, are formed on a semiconductor substrate (1). A first insulating film (2) made of disposed silicon on the substrate is covered with a 111L made of vapor-deposited aluminum.
A pole 11 (3) is formed and connections are made between circuit elements to form an amplifier circuit for each channel. A power supply line and a ground line indicated by diagonal lines are also formed of the first electrode layer (3). Next, a second insulating film (4) for glabellar insulation is provided on the first insulating film (2), and a second electrode layer (5) is provided on top of the first insulating film (2).
) is made of vapor-deposited aluminum. Like the second electrode layer i, it is provided so as to overlap with the first electrode layer (3) so as to be connected to the first electrode layer (3) via a through hole to form a predetermined circuit. In particular, semiconductor integrated circuits with built-in two-channel amplifier circuits are often connected to BTL to increase their power (there are cases where detection signals from other channels are required, such as thermal protection circuits, overvoltage detection circuits, ASO protection circuits, etc.). Therefore, it is necessary to cross the second electrode layer (5), and in this case, the first electrode layer (3) is used for cross wiring.This cross wiring structure is as shown in Figure 2. The second electrode layer (5) is the first electrode layer (3
), and the other second electrode layer (5) is tunneled by the second
It is insulated by an insulating film (4).

However, in such a multilayer wiring structure, basically, each circuit element is connected using the first electrode layer (3) as much as possible, and the wiring is wired almost over the entire surface.
The basic design rule is to wire those that cannot be wired using the second electrode layer (5). Therefore, when cross-wiring the second electrode layer (5), it is necessary to secure a space for the tunnel in the first electrode layer (3) in advance. There may be cases where it is necessary to increase the chip area.

(c) Purpose of the Invention It is an object of the present invention to realize a semiconductor integrated circuit having multilayer wiring with high design efficiency.

B) Structure of the Invention The semiconductor integrated circuit of the present invention comprises a semiconductor substrate on which desired circuit elements are formed, a first electrode layer wired on a first insulating layer provided on the surface of the substrate, and the first insulating layer. In a semiconductor integrated circuit having a multilayer wiring including a second electrode layer wired on a second insulating film covering the first electrode layer and a first region where the circuit element is wired and a second electrode layer wired on a second insulating film covering the The second electrode layer is divided into a second region where cross wiring is performed, and the first electrode layer arranged parallel to the second region and the second electrode layer extending parallel to each other are arranged so as to be orthogonal to each other. It is configured.

(E) Embodiment An embodiment of a semiconductor integrated circuit having multilayer wiring according to the present invention will be described with reference to FIGS. 3 and 4. FIG. 3 shows the arrangement of an IC pattern incorporating a two-channel amplifier circuit.

A plurality of island regions are provided on the semiconductor substrate Ql), and circuit elements such as transistors, resistors, diodes, etc. are integrated therein. Each of the circuit elements incorporates what is necessary to form a two-channel amplifier circuit.

The first 1ilC pole layer 9 is a feature of the present invention, and is located on the side of the first insulating film u covering the surface of the substrate 00.
16) and a second region α7). The first region αe connects the circuit elements to form a two-channel amplifier circuit, and the second region Q7) connects the cross wiring of the second electrode layer US. Specifically, the power supply (VCC) line is arranged in the center of the bellet in a bifurcated manner on the left and right, and ground ( GND) line is placed. The area surrounded by the power supply line and the ground line is a first area (16), and the amplifier circuits of the respective channels are connected. The second region aη is formed in a portion surrounded by the power supply line. Therefore, the first area (17), which occupies most of the area of the bellet, is used as an area for connecting with circuit elements to form each channel amplifier circuit, and the second area (17) is used as a second electrode layer. (It is sufficient to have the minimum area necessary to perform the cross wiring in 1).In other words, in the second area η, the multiple lines necessary for the cross wiring, which extend in the left and right direction like the power supply lines, are required. They are placed in parallel at regular intervals.

The second electrode layer Q9 extends over the second insulating film α which serves as an interlayer insulating material made of polyimide or the like, and is connected to the first electrode layer (13) via a through hole. A thermal protection circuit, an overvoltage detection circuit, an ASO protection circuit, etc. are required to input detection signals from other channels by connecting and using them.Therefore, as shown in Fig. 3, A→A, B-+B, c- +c, D-+D
A connection beyond channels such as 1B-+E is required.

The A-+A wiring contacts the first electrode layer α through a through hole at point A, and then connects the second electrode layer (one wire extends vertically perpendicular to the power supply line to the first electrode layer α). Second
The second electrode layer α5) is extended to the top of the area aη, connected to one line for cross wiring in the second area (17) via a through hole, and routed rightward to the second electrode layer α5) in the vertical direction from point A. Connect the wires to each other via a through hole at the point where they intersect. Since Naori-+D is on a straight line in the vertical direction, it is directly connected without cross wiring.

The greatest feature of the present invention is the second area (1
7) The first electrode layer α■ is extended in parallel to form the second electrode layer αυ.
The points also extend parallel to each other and are made to intersect at right angles. As a result, there is no possibility that the second electrode layer α9 will cross wiring with each other except on the second region αη, and it is sufficient to extend the second electrode layer Q5) in the vertical direction, making the design extremely easy. Also, regarding cross wiring, see the second section.
It is sufficient to connect via a through hole at the point where the electrode layer haze and the first electrode layer 0 of the second region (17) intersect, and the first electrode layer α of the second region (17>) is necessary for cross wiring. The design of the first electrode layer a4 in the second region αD is extremely easy.An important point is that any wiring route can always be connected at the shortest distance. Therefore, there is no need to bend and take a detour around the second electrode layer a9, and the wiring can be realized with a minimum area.

FIG. 4 is a cross-sectional view taken along the line RV-IV in FIG. 3, where aυ is the semiconductor substrate, a is the first insulating film, (2) is the first electrode layer,
The second insulating film, QS, is the second electrode layer. As is clear from FIG. 4, a step occurs in the second insulating film αa due to the rise of the first electrode layer a. This step is the second electrode/m f1
When photo-etching 51, there is a high possibility that the step portion will also be exposed and the second electrode layer aω will remain as a bridge. In particular, when the first electrode layer α and the second electrode layer u are extended in parallel, short circuits due to bridges are likely to occur. In the present invention, the second electrode layer Uω and the first electrode Wt (13
) are arranged perpendicularly to each other, there is no occurrence of such bridges, and the wiring can be arranged regardless of the pattern of the second electrode layer (151 is the first electrode layer α3), thereby improving the wiring packaging density.

(F) Effects of the Invention According to the present invention, space for the cross wiring of the second electrode layer a is secured in the second region αη of the first electrode layer (a). In the first region α6) of No. 13, only connections between circuit elements need be made, and design can be performed without worrying about the space for cross wiring of the second electrode layer α4.

Further, since the first electrode layer 03) and the second electrode layer (151) of the second region (17) extend in directions perpendicular to each other, the design of both electrode layers Ht151 is simplified and the design speed can be increased.

Furthermore, the first electrode layer (131 and the second electrode layer α) in the second region Uη
5) are orthogonally crossed, so there is no bridge caused by the step difference in the two-layer wiring, so both electrode layers (I31α
9 can be improved, and the chip area can be reduced.

[Brief explanation of drawings]

FIG. 1 is a top view illustrating a semiconductor integrated circuit having conventional multilayer wiring, FIG. 2 is a cross-sectional view illustrating general loss wiring, and FIG. 3 is a top view illustrating a semiconductor integrated circuit having multilayer wiring according to the present invention. The top view for explanation, Figure 4 is IV-IV of Figure 3.
FIG. 7aυ is a semiconductor substrate, (121 is a first insulating film, U□□□ is a first electrode layer,
an insulating film, (1 impeded second electrode layer, α0 is the first region,
(17) is the second area. Applicant Sanyo Electric Co., Ltd. and one other agent Patent attorney Shizuo Sano

Claims (1)

[Claims] (1) A semiconductor substrate on which a desired circuit element is formed, a first electrode layer wired on a first insulating film provided on the surface of the substrate, and a second insulating film covering the first insulating layer. In a semiconductor integrated circuit having a multilayer wiring including a second electrode layer wired in the semiconductor integrated circuit, the first electrode layer is cross-wired between a first region where the circuit elements are wired and the second electrode layer. Second
1. A semiconductor integrated circuit having multilayer wiring, characterized in that the first electrode layer is divided into regions, and the first electrode layer arranged parallel to the second region and the second electrode layer extending parallel to each other are arranged orthogonally to each other.