JPH0630357B2 - Semiconductor integrated circuit having multilayer wiring - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having multi-layer wiring.

(B) Conventional technology Recently, in order to improve the degree of integration of semiconductor integrated circuits, a multilayer wiring structure has been adopted, and wiring is provided with flexibility to achieve high integration of circuit elements. As such a multilayer wiring structure, polyimide is used as an interlayer insulating film.
The 871 publication is known.

FIG. 1 shows an I incorporating a conventional 2-channel amplifier circuit.
The arrangement of the C pattern is shown. A power supply ( _Vcc ) line is arranged on the left and right in the center of the pellet, and a ground (GND) line is arranged around the three sides of the pellet. On the upper and lower sides of the power supply line, transistors and resistors formed by 1-channel and 2-channel amplifier circuits, respectively,
A circuit element such as a diode is formed on the semiconductor substrate (1). And a first insulating film made of silicon oxide on the substrate
A first electrode layer (3) made of vapor-deposited aluminum is formed on (2) to connect circuit elements to form an amplifier circuit for each channel. The power supply line and the ground line indicated by diagonal lines are also formed of the first electrode layer (3). Subsequently, a second insulating film (4) for interlayer insulation is provided on the first insulating film (2), and a second electrode layer (5) is formed on the first insulating film (5) by vapor deposition aluminum. The second electrode layer (5) is A → A ′, B → B ′, C →
C ', D → D' and E → E 'are connected to the first electrode layer (3) through the through holes so as to form a predetermined circuit so as to overlap the first electrode layer (3). Has been. In particular, in a semiconductor integrated circuit having a built-in 2-channel amplifier circuit, BTL connection is often used for powering up, and a detection signal from another channel such as a thermal protection circuit, an overvoltage detection circuit, or an ASO protection circuit is often required. . Therefore, it is necessary to cross the second electrode layers (5) as well, and in this case, the first electrode layer (3) is used for cross wiring. In this cross wiring structure, as shown in FIG. 2, one second electrode layer (5) is tunneled by the first electrode layer (3) and the other second electrode layer (5) is tunneled.
The electrode layer (5) is insulated by the second insulating film (4).

However, in such a multi-layer wiring structure, basically, as much as possible, the first electrode layer (3) is used to connect the circuit elements, and the wiring is almost entirely over the first electrode layer (3). The basic design rule is to wire those that cannot be wired in the second electrode layer (5). Therefore, when performing the cross wiring of the second electrode layer (5), it is necessary to secure a space for the tunnel in the first electrode layer (3) in advance, which complicates the design and the space for the tunnel. There are cases where the chip area must be increased.

(C) Object of the Invention The present invention has been made in view of this point, and an object of the present invention is to realize a semiconductor integrated circuit having multilayer wiring with good design efficiency.

(D) Structure of the Invention A semiconductor integrated circuit of the present invention comprises a semiconductor substrate on which desired circuit elements are formed, a first electrode layer wired on a first insulating layer provided on the surface of the substrate, and the first insulating layer. In a semiconductor integrated circuit having a multi-layer wiring including a second electrode layer wired on a second insulating layer covering the layer, a first region for wiring the circuit element to the first electrode layer And a second region for cross-wiring of the second electrode layer, the first electrode layer arranged in parallel with the second region and the second electrode layer extending in parallel are arranged so as to be orthogonal to each other. Then, the through holes of the first electrode layer and the second electrode layer in the second region are formed by bending the second electrode layer along the first electrode layer in the second region and appropriately providing it with difficulty. It is configured.

(E) Example An example of a semiconductor integrated circuit having multi-layer wiring according to the present invention will be described with reference to FIGS. Figure 3 is 2
The layout of an IC pattern incorporating a channel amplifier circuit is shown.

A plurality of island regions are provided on the semiconductor substrate (11) to form circuit elements such as transistors, resistors and diodes in an integrated manner. The circuit elements each incorporate what is required to form a two channel amplifier circuit.

The first electrode layer (13) is a feature of the present invention.
1) A first region (16) and a second region on the first insulating film (12) covering the surface.
It is divided into regions (17). The first region (16) connects the circuit elements to each other to form a two-channel amplifier circuit, and the second region (17) connects the cross wiring of the second electrode layer (15). Specifically, a power supply (V _cc ) line is bifurcated left and right in the center of the pellet to form a power supply line for each channel. A ground (GND) line is arranged around the three sides of the pellet. The portion surrounded by the power supply line and the ground line becomes the first region (16), and the amplifier circuits of the respective channels are connected. The second region (17) is formed in a portion surrounded by the power line. Therefore, in the first region (16) which occupies most of the area of the pellet, it is used as a region for connecting circuit elements to form each channel amplifier circuit,
In the second region (17), it is sufficient that the second region (17) has a minimum area required for cross wiring of the second electrode layer (15). That is, in the second region (17), a plurality of lines required for the cross wiring extending in the left-right direction are provided in parallel with each other at regular intervals, like the power supply line.

The second electrode layer (15) extends on the second insulating film (14) made of polyimide or the like and acting as an interlayer insulating material, and is connected to the first electrode layer (13) through a through hole. The two-channel amplifier circuit requires a thermal protection circuit, an overvoltage detection circuit, an ASO protection circuit, etc. for inputting a detection signal from another channel by using the BTL connection. Therefore, the third
As shown in the figure, A → A ′, B → B ′, C → C ′, D →
Connections across channels such as D ', E->E' are required. The wiring of A → A ′ contacts the first electrode layer (13) through the through hole at the point A, and then extends the second electrode layer (15) in the vertical direction orthogonal to the power supply line (first electrode layer (13)). 13) It extends to above the second area (17), where it is connected to one line for cross wiring of the second area (17) through a through hole and is routed to the right direction, and from the point A ′ in the vertical direction. Second electrode layer (1
It is connected via a through hole at the point where it intersects with 5).
B → B ′, C → C ′ and E → E ′ are similarly wired.
Since D → D ′ is on a straight line in the vertical direction, it is directly connected without cross wiring.

The feature of the present invention is that the first of the second region (17) used for the cross wiring is used.
The point is that the electrode layers (13) extend in parallel, the second electrode layers (15) also extend in parallel, and the two are made orthogonal to each other. As a result, the second electrode layer (15) is completely free from the possibility of cross wiring other than on the second region (17), and it is sufficient to extend the second electrode layer (15) in the vertical direction, which is extremely easy to design. Becomes Regarding the cross wiring, it is sufficient to make a connection through the through hole at the point where the second electrode layer (15) and the first electrode layer (13) of the second region (17) intersect, and the crossing of the second region (17) is sufficient. First
It is only necessary to extend the electrode layers (13) in parallel for the number of cross wirings, and the design of the first electrode layer (13) in the second region (17) is extremely easy. More importantly, any wiring route can always be connected with the shortest distance. Thereby, the second electrode layer (1
Wiring can be realized in the minimum area without the need to bend and detour 5).

Further, the most characteristic point of the present invention is the position where the through hole is formed. Explaining with reference to FIG. 5, the shaded solid line shows the first electrode layer (13) of the second region (17), and the dotted line shows the second electrode layer (15). In the above description, the through hole is formed at the intersection of the first electrode layer (13) and the second electrode layer (15). However, in forming the through hole, the first electrode layer 13 and the second electrode layer 15 must be expanded. Specifically, in the first electrode layer (13) having a width of 12.5 μm, the through hole (18) is provided with a square-shaped expanded portion (19) having a side of 45 μm, and the through hole (18) has a side of 12.5 μm.
The second electrode layer (15) is formed in a square shape of μm and has a square-shaped expansion portion (19) having a side length of 35 μm.
Therefore, in the present invention, the through holes (18) are appropriately dispersed to form the first
The extended portions (19) and (19) of the electrode layer (13) and the second electrode layer (15) are arranged so as not to overlap each other. In FIG. 5, the intermediate first electrode layer (13) extends rightward from the intersection of the second electrode layers (15) to form a through hole (18). This intermediate first electrode layer
(13) extends rightward by recessing the protruding portions (19) and (19) of the first electrode layers (13) on both sides and extending to the right.
An extension (19) of the intermediate first electrode layer (13) is formed in the second region (17) where 3) does not exist. The second electrode layer (15) extends to the corresponding extended portion (19) of the first electrode layer (13) to extend through holes.
The intermediate second electrode layer (15) is connected through (18), and the extended portion (1) of the first electrode layer (13) is bent 90 ° along the intermediate first electrode layer (13) and extended. 19) is connected via a through hole (18).

4 is a sectional view taken along the line IV-IV in FIG. 3, where (11) is a semiconductor substrate, (12) is a first insulating film, (13) is a first electrode layer, and (14) is a second electrode layer. The insulating film, (15), is the second electrode layer. As is clear from FIG. 4, a step due to the first electrode layer (13) is formed in the second insulating film (14). This step is also exposed when the second electrode layer (15) is photo-etched, so that the second electrode layer (15) is exposed.
Is likely to remain as a bridge. Especially the first electrode layer (1
When 3) and the second electrode layer (15) extend in parallel, a short circuit due to a bridge is likely to occur. In the present invention, since the second electrode layer (15) and the first electrode layer (13) used for the cross wiring are arranged orthogonally to each other, such a bridge does not occur at all, and the second electrode layer (15) is It can be arranged regardless of the pattern of the one-electrode layer (13), and the mounting density of wiring can be improved.

(F) Effect of the Invention According to the present invention, the space for the cross wiring of the second electrode layer (15) is secured in the second region (17) of the first electrode layer (13). In the first region (16) of the electrode layer (13), only the connection between the circuit elements needs to be made, and there is an advantage that it can be designed without worrying about the space of the cross wiring. As a result, the first electrode layer (1
3) and the design of the second electrode layer (15) can be speeded up, and it is sufficient to secure the minimum area of the second region (17), so that the chip area need not be expanded so much. Further the second area (17)
Since the cross wiring is positively performed, the two-layer wiring can be always performed in the shortest distance.

Further, by providing the through holes appropriately separated, the distance between the first electrode layers (13) in the second region (17) is set to the through holes (18).
No need to design for extension (19) for
It can be designed according to the electrode layer (13) and the area of the second region (17) can be reduced. Usually, since no circuit element is provided under the second area (17), the packaging density of the circuit elements can be greatly improved by reducing the size of the second area (17).

[Brief description of drawings]

FIG. 1 is a top view illustrating a conventional semiconductor integrated circuit having multi-layer wiring, FIG. 2 is a cross-sectional view illustrating a general cross wiring, and FIG. 3 is a semiconductor integrated circuit having multi-layer wiring according to the present invention. 4 is a sectional view taken along line IV-IV in FIG. 3, and FIG. 5 is an upper surface for explaining through-hole connection between the first electrode layer and the second electrode layer in the second region according to the present invention. It is a figure. (11) is a semiconductor substrate, (12) is a first insulating film, (13) is a first electrode layer, (14) is a second insulating film, (15) is a second electrode layer, and (16) is a second electrode layer. 1 area, (17) second area, (18) through hole, (19)
Is an extension.

Claims (1)

[Claims] 1. A semiconductor substrate on which a desired circuit element is formed, a first electrode layer wired on a first insulating film provided on the surface of the substrate, and a second insulating layer covering the first electrode layer. In a semiconductor integrated circuit having a multilayer wiring including a second electrode layer wired on a film, a surface of the semiconductor substrate is crossed with a first region for arranging a circuit element. It is divided into a second region, the first electrode layer interconnects the circuit elements in the first region, and extends substantially parallel to each other in the second region for interlayer connection. Forming a plurality of connection lines having an extended portion, the second electrode layer extends so as to be orthogonal to the connection line of the second region, and the cross wiring is formed by interlayer connection at the extended portion, When the plurality of electrodes are close to each other, the second electrode layer and the connection line are orthogonal to each other. The extension part of the connection line that cannot be installed in the part is installed in the part separated from the orthogonal part, and the corresponding second electrode layer is bent from the orthogonal part and extends in parallel with the connection line. Therefore, the semiconductor integrated circuit is connected to the separated extended portion.