JP2944295B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device in consideration of a wiring shape of a multilayer wiring.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit device, a metal wiring having a width of several tens to several hundreds of micrometers is used for a power supply wiring for supplying a power supply potential and a ground potential in order to reduce wiring resistance and current density. Used. In recent years, as the capacity of semiconductor integrated circuit devices has increased, the chip size has increased, and high density has been required to suppress the increase, and a multilayer wiring process has been introduced. This is a process of providing another metal wiring on a conventional metal wiring via an insulating film.

[0003] Accordingly, in the case of a thick wiring such as a power supply wiring, a structure in which the first-layer metal wiring and the second-layer metal wiring are overlapped to reduce the horizontal dimension and the chip size. Can be. For example, conventionally, 100 μm
The 50 μm dimension can be reduced by overlapping two layers of the 50 μm width wiring with the portion where the m width wiring is provided.

[0004]

However, cracks are likely to occur in an insulating film between two metal wiring layers in a region where thick wirings overlap in the conventional semiconductor integrated circuit device having a multilayer wiring structure. There was a problem. FIG.
2A is a plan view of this conventional multilayer wiring structure, and FIG.
FIG. 2B is a sectional view taken along the line BB ′ of FIG. The upper metal wiring 11 and the lower metal wiring 12 overlap with an insulating film 14 interposed therebetween.

In a semiconductor integrated circuit device having such a multilayer wiring structure, when the ambient temperature rises, a thermal stress acts on the interface between the metal wiring having a different coefficient of thermal expansion and the insulating film. This force increases as the metal wiring width increases and the contact area between the metal wiring and the insulating film increases, and eventually, the insulating film cracks. In order to prevent the occurrence of cracks, a thick metal wiring may be divided into a plurality of metal wirings by slitting the wirings to reduce the wiring width per wiring and the contact area with the insulating film.

FIG. 3A is a plan view showing a multilayer wiring structure showing a state in which slits are inserted and divided in this manner.
FIG. 3B is a cross-sectional view taken along the line CC ′ of FIG. In FIG. 3, a slit is formed in a metal wiring
Five wirings 21a to 21e and 22a to 22 having a width of about μm
e to reduce the contact area with the interlayer insulating film. However, with such a wiring structure, current may concentrate on a specific wiring. For example, as shown in FIG.
The current flowing only in e increases, causing a potential drop, floating, and the like, resulting in deterioration of operating characteristics.

In order to prevent this, a configuration is conceivable in which divided wirings are connected near a branch point as shown in FIG.
However, only at that portion, the contact area with the insulating film increases, and cracks are likely to occur. Further, in such a structure, when there are many branch points, the divided wiring is connected each time, so that the effect of dividing the wiring is almost lost.
May be The present invention has been made in view of the above considerations, and its purpose is to prevent a crack from occurring in an interlayer insulating film while minimizing an increase in wiring resistance and to prevent current from concentrating on a specific wiring. To provide a semiconductor integrated circuit device.

[0008]

In order to achieve the above object, a semiconductor integrated circuit device according to the present invention is formed by stacking a first metal wiring and a second metal wiring on a semiconductor substrate with an insulating film interposed therebetween. In the semiconductor integrated circuit device, a slit is formed in each of the first and second metal wirings in a direction in which a current flows, and the wiring is divided into a plurality of wirings. The slits of the wiring are formed so as to be shifted from each other so that the positions formed with the insulating film interposed therebetween do not coincide with each other, and the divided wiring of the first metal wiring is formed of the divided wiring of the second metal wiring. Of these, it is configured to be connected to two adjacent metal wirings. The divided wiring of the first metal wiring and the divided wiring of the second metal wiring are connected by a plurality of connection holes. Also, in the semiconductor integrated circuit device of the present invention, the first metal wiring and the second metal wiring are formed so as to overlap with each other with the insulating film interposed therebetween, and the wiring width is reduced so that the positions of the two wirings do not overlap with each other. a plurality of divided first metal wiring and the second metal wiring as well as divided into wiring slits in the direction of is connected via a number of connection holes.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to the drawings. FIG. 1A is a plan view showing an embodiment of a semiconductor integrated circuit device according to the present invention, and FIG.
It is sectional drawing. A slit having a width of 2 to 3 μm is formed in a thick wiring having a width of 100 μm. Thus, the wiring is divided into wirings having a width of 17 to 18 μm. The contact area between the metal wirings 1 and 2 and the insulating film 4 is reduced, thereby preventing the occurrence of cracks.

The slits of the upper metal wiring 1 and the slits of the lower metal wiring 2 are formed at shifted positions so as not to overlap each other. The upper metal wiring 1 and the lower metal wiring 2 are connected by a contact hole 3 and all the divided metal wirings are connected. With such a configuration, even in a structure in which the wiring branches off in the middle, the current is always distributed to all of the divided wirings, so that deterioration of the operation characteristics due to potential drop or floating can be prevented.

[0011]

As described above, according to the present invention, the first metal wiring and the second metal wiring on the semiconductor substrate are formed with the insulating film interposed therebetween, and the first and second metal wirings are formed on the first and second metal wirings. A slit is formed to divide the wiring into a plurality of wirings, and the slits of the first metal wiring and the slits of the second metal wiring are formed so as to be displaced so as not to coincide with each other, and the divided wiring of the first metal wiring Are connected to two metal wirings adjacent to each other among the divided wirings of the second metal wiring, whereby cracks occur in the interlayer insulating film while minimizing an increase in wiring resistance. In addition, since current is not concentrated on a specific wiring, the operation of the semiconductor integrated circuit device can be prevented from deteriorating.

[Brief description of the drawings]

FIG. 1A is a plan view showing an embodiment of a semiconductor integrated circuit device according to the present invention, and FIG. 1B is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 2A is a plan view showing a metal wiring structure in a conventional semiconductor integrated circuit device, and FIG. 2B is a cross-sectional view taken along the line BB 'of FIG.

FIG. 3A is a plan view showing another metal wiring structure in a conventional semiconductor integrated circuit device, and FIG.
It is C 'sectional drawing.

FIG. 4 is a plan view showing a shape of a metal wiring in FIG. 3;

FIG. 5 is a plan view showing another shape of the metal wiring in FIG. 3;

[Explanation of symbols]

1,1a-1e, 11,21,21a-21e, 31a
... 31e ... upper layer metal wiring 2, 2a-2e, 12, 22 ... lower layer metal wiring 3 ... contact hole 4, 14, 24 ... insulating film

Claims (3)

(57) [Claims] 1. A first metal wiring and a second metal wiring on a semiconductor substrate are formed on top of each other with an insulating film interposed therebetween, and a slit is formed in a direction in which a current flows through each of the first and second metal wirings. In the semiconductor integrated circuit device which is inserted and divided into a plurality of wirings, positions of the slits of the first metal wiring and the slits of the second metal wiring formed so as not to coincide with each other with the insulating film interposed therebetween. And wherein the divided wirings of the first metal wiring are connected to two adjacent metal wirings among the divided wirings of the second metal wiring. A semiconductor integrated circuit device characterized by the above-mentioned. 2. The semiconductor integrated circuit according to claim 1, wherein the connection between the divided wiring of the first metal wiring and the divided wiring of the second metal wiring is performed by a plurality of connection holes. apparatus. 3. A method in which a first metal wiring and a second metal wiring are formed with an insulating film interposed therebetween, and the wiring width is reduced so that the two wirings do not overlap each other.
A semiconductor integrated circuit device, wherein the first metal wiring and the second metal wiring which are divided into a plurality of wirings by inserting slits in the direction are connected through a large number of connection holes.