JP2002270643A - Semiconductor chip and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip for which the pitch of external electrode terminals can be made fine, the density of the external electrode terminals can be increased, and a semiconductor device provided with the semiconductor chip. SOLUTION: First external electrode terminals 118 are formed on the integrated circuit 12 of a semiconductor chip 1, and second external electrode terminals 117 are formed on the periphery of the integrated circuit 12. Solder bump electrodes 15 are placed on the first external electrode terminals 118. The second external electrode terminals 117 are formed with the size thereof being smaller than the size of the first external electrode terminals 118 and is arranged, so that the pitch thereof is smaller than the pitch of the first external electrode terminals. Stud bump electrodes 13 are placed on the second external electrode terminals 117, and the semiconductor chip 1 is placed on a wiring board so as to construct a semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor chip and a semiconductor device, and more particularly to a semiconductor chip having external electrode terminals (pads) and a semiconductor device having the semiconductor chip mounted on a wiring board.

[0002]

2. Description of the Related Art A semiconductor chip 100 incorporated in a semiconductor device shown in FIG.
An external electrode terminal (bonding pad) 103 is provided in a peripheral region of the integrated circuit
It has. A plurality of external electrode terminals 103 are arranged at a predetermined interval over almost the entire periphery of the single crystal silicon substrate 101.

[0003] As shown in FIG.
03 is provided with a stud bump electrode 104. The stud bump electrodes 104 electrically and mechanically connect the external electrode terminals 103 of the semiconductor chip 100 and the terminals of a wiring board (not shown) on the wiring board. And build a semiconductor device. The stud bump electrode 104 is formed by bonding one end of a bonding wire to the external electrode terminal 101 using a wire bonding device, and cutting the wire while pulling up the other end of the bonding wire.

In this type of semiconductor device, the stud bump electrodes 104 are formed from small-diameter bonding wires, and the arrangement intervals of the stud bump electrodes 104 can be reduced. As a result, the arrangement intervals of the external electrode terminals 103 can be reduced. It can be formed at a fine pitch of about 50 μm to 70 μm.

On the other hand, a semiconductor chip 200 incorporated in the semiconductor device shown in FIG.
01 is provided with an integrated circuit 202 on the main surface thereof.
External electrode terminals (bump electrode pads) 203 are provided on the entire surface including the upper surface 2 and its peripheral region. The external electrode terminals 203 are arranged in a matrix at predetermined intervals.

[0006] As shown in FIG.
03 is provided with a solder bump electrode 204. The solder bump electrode 204 is connected to the semiconductor chip 2
The semiconductor device 200 is electrically and mechanically connected between the external electrode terminals 203 and the terminals of a wiring board (not shown), and the semiconductor chip 200 is mounted on the wiring board by a flip-chip method to construct a semiconductor device. It is supposed to. The solder bump electrode 204 is made of, for example, Pb-Sn
It is formed by a screen printing method or a plating method using a solder bump electrode, a Sn-Ag solder bump electrode containing no Pb, and the like.

In this type of semiconductor device, the entire area of the main surface of the single crystal silicon substrate 201 can be effectively used. For example, a large number of solder bump electrodes 204 are arranged at a high density with an arrangement interval of 150 μm to 250 μm. can do.

[0008]

However, in the semiconductor chip 100 shown in FIGS. 6A and 6B, when the stud bump electrodes 104 are bonded, damage is caused below the external electrode terminals 103. The electrode terminal 103 cannot be provided on the integrated circuit 102, on a wiring for connection of the integrated circuit 102, or the like. That is, the arrangement region of the external electrode terminals 103 is the single crystal silicon substrate 101.
Is limited to the peripheral area of the integrated circuit 102 on the main surface, and the fine pitch of the external electrode terminals 103 can be achieved, but it is difficult to arrange the external electrode terminals 103 at high density.

On the other hand, in the semiconductor chip 200 shown in FIG. 7A and FIG.
As the area occupied by the 04 increases and promotes higher density,
There is a possibility that a short circuit occurs between adjacent solder bump electrodes 204. That is, the external electrode terminal 203 is the external electrode terminal 1 of the semiconductor chip 100 shown in FIGS. 6A and 6B.
Since the arrangement interval cannot be reduced so as to be equal to that of the external electrode terminal 203, the density of the external electrode terminals 203 can be increased.
It is difficult to arrange the external electrode terminals 203 at a fine pitch.

The present invention has been made to solve the above problems. Accordingly, an object of the present invention is to provide a semiconductor chip capable of increasing the density of external electrode terminals while achieving fine pitch of the external electrode terminals.

It is a further object of the present invention to provide a semiconductor chip capable of realizing a higher circuit operating speed while achieving the above object.

It is a further object of the present invention to provide a semiconductor chip which can improve the noise resistance while achieving the above object.

It is a further object of the present invention to provide a semiconductor chip which can easily realize a wiring structure while achieving the above object.

It is still another object of the present invention to provide a semiconductor device having a semiconductor chip capable of increasing the density of external electrode terminals while achieving fine pitch of the external electrode terminals.

[0015]

In order to solve the above problems, a first feature of the present invention is that a plurality of first external electrode terminals are provided at predetermined intervals on a circuit on a main surface of a semiconductor substrate; A plurality of semiconductor substrates are arranged around the circuit on the main surface of the semiconductor substrate.
And a second external electrode terminal having a smaller terminal size and a smaller arrangement interval than the external electrode terminal. Here, the “first external electrode terminal”
Is preferably used as an electrode pad on which a solder bump electrode is formed. "Solder bump electrode"
A solder bump electrode containing Pb as a main constituent element;
At least a Pb-free solder bump electrode containing no b is included. The “solder bump electrode” can be formed on the first external electrode terminal by a screen printing method, a plating method, or the like. On the other hand, the "second external electrode terminal" is preferably used as an electrode pad on which a stud bump electrode is formed. "Stud bump electrode" includes Au
At least a stud bump electrode, a Cu or Cu alloy stud bump electrode, etc. are included. The "stud bump electrode" can be formed by bonding one end of the wire onto the second external electrode terminal using a wire bonding apparatus, and cutting while pulling up the other end.
The tip of the "stud bump electrode", that is, the other cut end of the wire, has a relatively sharp shape, and the overall shape of the "stud bump electrode" is shaped like a "stud" Is preferably performed. The “first external electrode terminal” is provided at the center of the main surface of the semiconductor substrate,
The “second external electrode terminal” is arranged on the periphery of the main surface of the semiconductor substrate. Conversely, the “first external electrode terminal” is provided at the periphery of the semiconductor substrate main surface, and the “second external electrode terminal” is provided at the center of the semiconductor substrate main surface. ing.

In the semiconductor chip according to the first aspect of the present invention having such a configuration, the first external electrode terminals are provided on the entire area of the circuit on the main surface of the semiconductor substrate. Since the electrode terminals can be arranged at a high density and the second external electrode terminals are arranged at a small arrangement size and at a small arrangement interval on the periphery of the circuit on the main surface of the semiconductor substrate, the second external electrode terminals are arranged. Can be set to a fine pitch.

Further, in the semiconductor chip according to the first aspect of the present invention, the input signal, the output signal, the input / output signal, the power supply, and the like are distributed to the first external electrode terminal and the second external electrode terminal. Since the connection can be performed, it is possible to reduce the number of wirings and the number of layers of such wirings that bypass the first external electrode terminals. Therefore, the wiring structure of the semiconductor chip including the first external electrode terminals and the second external electrode terminals can be easily realized. In addition, as a result of simplifying the wiring structure of the semiconductor chip, it is possible to improve the manufacturing yield in manufacturing the semiconductor chip.

Further, in the semiconductor chip according to the first feature of the present invention, the first external electrode terminal can be formed of the same conductive material in the same wiring layer as the second external electrode terminal. In the step of forming the second external electrode terminal, the first external electrode terminal can be formed at the same time, and the rewiring process can be eliminated. Therefore, in the semiconductor chip according to the first aspect of the present invention, the wiring structure can be easily realized and the number of rewirings can be reduced, so that the resistance and capacitance added to the wiring can be reduced. It is possible to realize a high-speed circuit operation. Further, since the wiring structure can be easily realized, the production yield of the semiconductor chip can be improved.

A second feature of the present invention is that the semiconductor chip according to the first feature of the present invention is a semiconductor chip in which the first external electrode terminal is used at least as an external electrode terminal for power supply voltage. Here, the “power supply voltage” is used to mean an operation power supply voltage of a circuit of a semiconductor chip or a reference power supply voltage.

In the semiconductor chip according to the second aspect of the present invention, the size of the first external electrode terminal is large, and the voltage drop of the power supply voltage supplied through the first external electrode terminal is reduced. (Resistance value of the power supply path) can be reduced, so that a stable circuit operation resistant to noise can be realized.

A third feature of the present invention is that a plurality of first external electrode terminals are provided at predetermined intervals on a circuit on the main surface of the semiconductor substrate, and a plurality of first external electrode terminals are provided around the circuit on the main surface of the semiconductor substrate, The terminal size is smaller than the first external electrode terminal,
A semiconductor chip including a second external electrode terminal having a small arrangement interval, a first internal electrode terminal corresponding to the first external electrode terminal, and a second internal electrode corresponding to the second external electrode terminal Terminal, a solder bump electrode between the first external electrode terminal and the first internal electrode terminal, and a stud bump between the second external electrode terminal and the second internal electrode terminal And a semiconductor device including the electrodes.
Here, “first external electrode terminal”, “second external electrode terminal”, “solder bump electrode”, “stud bump electrode”
Definitions of terms such as "first external electrode terminal" of the semiconductor chip according to the first feature of the present invention are the same as those of the first embodiment. The term “wiring board” is used to mean a board on which at least a semiconductor chip can be mounted and which is used as a part of a sealing body. This "wiring board"
A resin substrate (for example, a printed wiring board), a resin tape substrate, a ceramic substrate, a silicon carbide substrate, a glass substrate, and the like are used at least. The term "first internal electrode terminal" is used to mean a terminal for electrically and mechanically connecting the first external electrode terminal of the semiconductor chip with a solder bump electrode interposed therebetween. Similarly, "second
Is used to mean a terminal for electrically and mechanically connecting a second external electrode terminal of a semiconductor chip with a stud bump electrode interposed therebetween. The “wiring board” is separately provided with external electrode terminals that are electrically connected to a mounting board, an electronic device, or the like, and that mount a semiconductor device.

In the semiconductor device according to the third aspect of the present invention thus configured, the same effect as that obtained in the semiconductor chip according to the first aspect of the present invention can be obtained.

[0023]

Next, a semiconductor chip and a semiconductor device according to the present invention will be described with reference to the drawings according to embodiments of the present invention. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. In addition, it is needless to say that dimensional relationships and ratios are different between drawings.

(First Embodiment) Structure of semiconductor chip: As shown in FIG.
The semiconductor chip 1 according to the embodiment has a semiconductor substrate 11
A plurality of first external electrode terminals 118 disposed on the main surface of the integrated circuit 12 at predetermined intervals and a plurality of first external electrode terminals disposed on the periphery of the integrated circuit 12 on the main surface of the semiconductor substrate 11; The second external electrode terminal 117 having a smaller terminal size and a smaller arrangement interval than the terminal 118 is constructed.

The integrated circuit 12 is provided in most of the central portion of the semiconductor substrate 11 in the semiconductor chip 1 according to the first embodiment of the present invention. Integrated circuit 12
Is mainly composed of, for example, a logic circuit, a storage circuit, and the like, and is used herein to include an input circuit, an output circuit, or an input / output circuit as an interface circuit.

As shown in FIG. 2, the semiconductor substrate 11 is formed of a single crystal silicon substrate, and a large number of transistors 121 are provided on the main surface of the semiconductor substrate 11. In the semiconductor chip 1 according to the first embodiment of the present invention, an insulated gate field effect transistor is used as the transistor 121, but the present invention is not limited to this, and the transistor 121 is a bipolar transistor or the like. You may. Further, although not shown, the integrated circuit 12 is provided with elements such as a resistance element and a capacitance element that are essential for constructing a circuit.

On the main surface of the semiconductor substrate 11, an element isolation insulating film 111 surrounding the transistors 121 and the like and electrically isolating the transistors 121 and the like from each other is provided. On the element isolation insulating film 111, first-layer wirings 113A to 113D for connecting the transistors 121, between circuits, and the like are provided with an interlayer insulating film 112 interposed therebetween. The first-layer wirings 113A to 113D
Are electrically connected to an electrode (a source region or a drain region or the like) of the transistor 121 through a connection hole (not numbered) formed in the interlayer insulating film 112. The first-layer wirings 113A to 113D are all disposed in the same wiring layer, and are, for example, Al alloy (Al-S
i, Al-Cu, Al-Cu-Si) film, Cu film and the like.

Further, the first-layer wirings 113A to 113A
Second wiring layers 115A to 115C are arranged on D with an interlayer insulating film 114 interposed therebetween.
A to 115C with an interlayer insulating film 116 interposed therebetween.
The external electrode terminal 118 and the second external electrode terminal 117 are provided. Second-layer wirings 115A to 115C
Are electrically connected to the first-layer wirings 113A to 113D through connection holes (not numbered) formed in the interlayer insulating film 114. Second layer wiring 115A-1
15C is formed of, for example, an Al alloy film similarly to the first-layer wirings 113A to 113D.

The first external electrode terminal 118 and the second external electrode terminal 117 are both formed of the same wiring material in the same wiring layer as the third layer wiring.
For example, the first external electrode terminal 118 and the second external electrode terminal 117 are connected to the A lines in the same manner as the first-layer wirings 113A to 113D and the second-layer wirings 115A to 115C.
It is formed of a 1 alloy film, a Cu film, or the like.

The first external electrode terminal 118 shown in FIG.
The wiring is connected to each of the second-layer wirings 115B and 115C through a connection hole formed in the interlayer insulating film 116, and a power supply voltage is supplied to each of the second-layer wirings 115B and 115C. . In other words, of the multiple first external electrode terminals 118, some of the first external electrode terminals 118 are used as power supply voltage external electrode terminals. The power supply voltage is a circuit operating voltage of the integrated circuit 12, for example, a voltage of 3.3 V to 5 V, or a circuit reference voltage of the integrated circuit 12, for example, 0 V. The second-layer wiring 115B connected to the first external electrode terminal 118 supplies a power supply voltage to the transistor 121 through the first-layer wiring 113B, and the second-layer wiring 11B.
5C is the transistor 1 through the first-layer wiring 113D.
21 is supplied with a power supply voltage. The first external electrode terminals 118 are regularly arranged in a matrix in a substantially entire area on the integrated circuit 12. This first
Are arranged at relatively large intervals of 150 μm to 250 μm in the row direction and the column direction, respectively.

A final protective film 119 is formed on the first external electrode terminal 118, and the surface of the first external electrode terminal 118 exposed from an electrode opening (not shown) of the final protective film 119. A barrier metal film 131 is provided thereon. Although the barrier metal film 131 is not necessarily limited to this, for example, a Ni film on a Cr film,
A composite film in which each of the Pd films is sequentially laminated can be used practically.

The second external electrode terminal 117 shown in FIG.
Is formed through a connection hole formed in the interlayer insulating film 116.
It is connected to the wiring 115A of the second layer and mainly transmits an input signal to the wiring 115A of the second layer, or transmits an output signal from the wiring 115A of the second layer, or Input / output signals are transmitted to and from the wiring 115A. That is, of the many second external electrode terminals 117 provided, most of the second external electrode terminals 117 are used as input signal, output signal, or input / output signal external electrode terminals. ing. Second
Of the second layer connected to the external electrode terminal 117 of FIG.
5A is the transistor 1 through the first-layer wiring 113A.
The signal is transmitted between the second external electrode terminal 117 and the transistor 121. The second external electrode terminal 117 is connected to the integrated circuit 1
In substantially the entire region along the periphery of the semiconductor substrate 11 on the peripheral region of No. 2, they are regularly arranged in one row. The second external electrode terminal 117 is connected to the first external electrode terminal 118
The terminal size is smaller than the terminal size of (1), and they are arranged at relatively small intervals of 50 μm to 70 μm in the arrangement direction.

On the second external electrode terminal 117, a final protective film 119 is formed, and the surface of the second external electrode terminal 117 exposed from the electrode opening (not shown) of the final protective film 119. A barrier metal film 130 is provided thereon. The barrier metal film 130 is the barrier metal film 1
31 are formed in the same layer and are formed of the same conductive material.

Structure of Semiconductor Device: As shown in FIGS. 1 and 2, the semiconductor device 10 according to the first embodiment of the present invention includes the semiconductor chip 1 and a first external part of the semiconductor chip 1. A first internal electrode terminal 22 corresponding to the electrode terminal 118, and a second external electrode terminal 117 of the semiconductor chip 1;
A wiring board 2 having a second internal electrode terminal 21 corresponding to the above, a solder bump electrode 15 between a first external electrode terminal 118 and a first internal electrode terminal 22, and a second external electrode terminal It is configured to include at least the stud bump electrode 13 between the first internal electrode terminal 117 and the second internal electrode terminal 21.
Further, in the semiconductor device 10, the sealing body 4 that protects at least the integrated circuit 12 of the semiconductor chip 1 is provided between the semiconductor chip 1 and the wiring board 2. For this sealing body 4, for example, a polyimide resin dropped by a drop coating method and then cured can be practically used.

The wiring board 2 includes a wiring substrate 20, a first internal electrode terminal 22 and a second internal electrode terminal 21 on the surface of the wiring substrate 20 (on the lower surface in FIG. 2), Substrate 20
The external electrode terminals 25 and 26 on the back surface (on the upper surface in FIG. 2), the first internal electrode terminal 22 and the external electrode terminal 26
And a connection hole wiring 23 electrically connecting the second internal electrode terminal 21 and the external electrode terminal 25 to each other.

As the wiring base 20, for example, an epoxy resin substrate can be practically used. First internal electrode terminal 22, second internal electrode terminal 21, external electrode terminal 2
For example, a single film such as a Cu film and a Ni film, a composite film in which a Ni plating film is formed on a Cu film,
A composite film in which an Au plating film is formed on a film or a Ni film can be practically used. For the connection hole wirings 23 and 24, for example, a Cu film can be practically used. Although not shown in detail in FIG. 2, in addition to the first internal electrode terminal 22, the second internal electrode terminal 21, and the like, wirings are provided on the front surface and the rear surface of the wiring base 20, respectively. .
On the external electrode terminal 25, a solder bump electrode 30 for mounting on a mounting board or an electronic device (not shown) is provided.
A solder bump electrode 31 is provided on the upper side.

In the present invention, a resin tape substrate (for example, a polyimide resin tape substrate), a ceramic substrate, a silicon carbide substrate, a glass substrate, or the like can be used as the wiring substrate 2 of the semiconductor device 10.

First external electrode terminal 11 of semiconductor chip 1
8 and the first internal electrode terminal 22 of the wiring board 2 are solder bump electrodes 15 having, for example, Pb as a main composition element (for example, Pb-Sn or the like).
Base solders and solders of three or more bases are included. ), Pb
Pb-free solder (for example, a binary solder such as Sn-Ag or a ternary solder or more is included) or the like can be practically used. First external electrode terminal 1
18, the first internal electrode terminals 22 are set to have substantially the same terminal size. In the solder bump electrode 15 after the reflow processing (final structure), the first external electrode terminals 118 and the first The cross-sectional area orthogonal to the direction in which the current flows increases according to the size of each of the internal electrode terminals 22. That is, the solder bump electrode 1
Since the resistance value of the current path 5 is small, it is preferable to use the solder bump electrode 15 for supplying a power supply voltage having a large current capacity, supplying a clock signal for determining high-speed operation, and the like. The solder bump electrode 15 may be formed on the first external electrode terminal 118, or on the first internal electrode terminal 22, or on the first external electrode terminal 118 or the first external electrode terminal 118 by, for example, a screen printing method, a plating method, a ball mounting method, or the like. 1 internal electrode terminal 22
It can be formed on both of the above.

Second external electrode terminal 11 of semiconductor chip 1
The stud bump electrode 13 disposed between the first internal electrode terminal 7 and the second internal electrode terminal 21 of the wiring board 2 is made of, for example, Au, Cu,
A Cu alloy or the like can be used practically. The stud bump electrode 13 is bonded to the second external electrode terminal 117 of the semiconductor chip 1 (or the second internal electrode terminal 21 of the wiring board 2) by using a wire bonding apparatus, and the tip of the wire is bonded. It can be formed by raising and cutting the other end. Therefore,
The upper portion (the other end of the wire) of the stud bump electrode 13 is formed in a sharp shape.

In order to improve the electrical and mechanical connection reliability with the stud bump electrodes 13, the second
A solder bump electrode 14 made of, for example, Sn-Ag or the like is disposed on the internal electrode terminal 21 (on the lower surface in FIG. 2). Further, this solder bump electrode 14 is
The adjustment of the distance between the external electrode terminal 117 and the second internal electrode terminal 21 (the height adjustment of the stud bump electrode 13) is performed. For example, the first external electrode terminal 1
The solder bump electrode 15 provided between the first internal electrode terminal 22 and the first internal electrode terminal 22 is formed at a height of about 100 μm,
On the other hand, since the stud bump electrode 13 is formed with a height of about 60 μm, the solder bump electrode 14 reduces the difference between these heights, and the stud bump electrode 13 allows the second external electrode terminal 117 and the second The second internal electrode terminal 21 is securely connected electrically.

The stud bump electrode 13 is formed within a plane area equivalent to the terminal size of the second external electrode terminal 117 of the semiconductor chip 1.
Therefore, the cross-sectional area of the stud bump electrode 13 in the same direction is smaller than the cross-sectional area of the solder bump electrode 15 orthogonal to the current flowing direction.
Since Au or the like having a small resistance value is used for 3, the resistance value of the stud bump electrode 13 itself can be reduced.

In the semiconductor chip 1 according to the first embodiment of the present invention thus configured, the semiconductor substrate 1
Since the first external electrode terminals 118 are provided on the entire area of the integrated circuit 12 on the main surface of the first external electrode terminals 118, the first external electrode terminals 118 are provided.
Can be arranged at a high density, and the second external electrode terminals 117 are arranged on the periphery of the integrated circuit 12 on the main surface of the semiconductor substrate 11 with a small terminal size and a small arrangement interval. Of the external electrode terminals 117 can be set to a fine pitch.

Further, in the semiconductor chip 1 according to the first embodiment of the present invention, the first external electrode terminals 118
And the second external electrode terminal 117 to distribute the input signal,
Since connection of an output signal, an input / output signal, a power supply voltage, and the like can be performed, in particular, a lead-out wiring (for example, a third-layer wiring) bypassing the first external electrode terminal 118 and such a lead-out wiring Can be reduced. In other words, signals and power supply voltages of a circuit disposed in the central portion of the integrated circuit 12 are transmitted to and from the wiring board 2 using the first external electrode terminals 118, and are transmitted to the periphery of the inside of the integrated circuit 12. Signals and power supply voltages of a circuit (for example, an interface circuit) provided can be transmitted to and from the wiring board 2 using the second external electrode terminal 117.
Therefore, the wiring structure of the semiconductor chip 1 including the first external electrode terminals 118 and the second external electrode terminals 117 can be easily realized. In addition, as a result of simplifying the wiring structure of the semiconductor chip 1, the yield in manufacturing the semiconductor chip 1 can be improved.

Furthermore, in the semiconductor chip 1 according to the first embodiment of the present invention, the first external electrode terminals 118
Can be formed of the same conductive material in the same wiring layer as the second external electrode terminal 117. FIG. 7 above
In the semiconductor chip 200 shown in FIGS. 6A and 6B, the external electrode terminals 1 shown in FIGS.
03 is the same as the semiconductor chip 100 in which
In order to arrange the external electrode terminals 203 and wiring for electrically connecting the external electrode terminals 203 and the external electrode terminals 103, a rewiring process is added after the semiconductor chip 200 is manufactured. In the semiconductor chip 1 according to the first embodiment, the second external electrode terminals 11
7 at the same time as the first external electrode terminal 1
18 can be formed, so that the rewiring process can be eliminated. Therefore, in the semiconductor chip 1 according to the first embodiment of the present invention, the wiring structure can be easily realized, and the rewiring can be reduced, so that the resistance and capacitance added to the wiring can be reduced. The speed of the circuit operation of the integrated circuit 12 can be increased. Further, since the wiring structure can be easily realized, the production yield of the semiconductor chip 1 can be improved.

Furthermore, in the semiconductor chip 1 according to the first embodiment of the present invention, the first external electrode terminals 118
Of the power supply voltage supplied through the first external electrode terminal 118 (resistance value of the power supply path) can be reduced, so that the integrated circuit 12 is resistant to noise and operates stably. Can be realized.

Further, in the semiconductor device 10 according to the first embodiment of the present invention, the same effects as those obtained in the semiconductor chip 1 according to the first embodiment of the present invention can be obtained. .

(Second Embodiment) In the second embodiment of the present invention, the arrangement of the second external electrode terminals 117 of the semiconductor chip 1 according to the first embodiment of the present invention is changed. This is an example.

The semiconductor chip 1 according to the second embodiment of the present invention has a second external electrode terminal 11 as shown in FIG.
7 are arranged in two rows, and are arranged in a zigzag pattern in which the arrangement interval of the other row is shifted by half a pitch with respect to one row.
The second external electrode terminal 117 of the semiconductor chip 1 according to the first embodiment of the present invention is connected to the second external electrode terminal 117.
Similarly, the stud bump electrode 13 is provided (see FIG. 2). The first external electrode terminal 118 is provided with the solder bump electrode 15.

Although not shown, this semiconductor chip 1
The arrangement of the second internal electrode terminals 21 of the wiring board 2 on which the semiconductor chip 1 and the wiring board 2 are mounted is also staggered, and the semiconductor device 10 is constructed by the semiconductor chip 1 and the wiring board 2.
reference. ).

The semiconductor chip 1 according to the second embodiment of the present invention thus configured has the same effects as those obtained by the semiconductor chip 1 according to the first embodiment of the present invention. Obtainable. Further, in the semiconductor chip 1, since the second external electrode terminals 117 are arranged in a staggered manner, it is possible to provide a margin in the interval between the adjacent stud bump electrodes 13 and to prevent a short circuit between the stud bump electrodes 13 or the like. Can be prevented.

(Third Embodiment) A third embodiment of the present invention relates to a first external electrode terminal 118 and a second external electrode of the semiconductor chip 1 according to the first embodiment of the present invention. 14 illustrates an example in which the arrangement of the terminals 117 is changed.

In the semiconductor chip 1 according to the third embodiment of the present invention, as shown in FIG. 4, an integrated circuit 12 is divided into a first integrated circuit 12A and a second integrated circuit 12B, and is divided into right and left. And the divided first integrated circuit 12A
The first external electrode terminal 1 on the second integrated circuit 12B
18 are arranged. The semiconductor chip 1 according to the first embodiment of the present invention is provided on the first external electrode terminals 118.
The solder bump electrodes 15 are provided in the same manner as the first external electrode terminals 118 (see FIG. 2).

Further, in the semiconductor chip 1, a region between the first integrated circuit 12A and the second integrated circuit 12B,
That is, the second external electrode terminals 117 are arranged on the peripheral region of the integrated circuit 12. In the semiconductor chip 1 according to the third embodiment of the present invention, a plurality of the second external electrode terminals 117 are arranged in two rows in the left-right direction and in the vertical direction in FIG. The second external electrode terminal 117
Is practically up to about four rows. The second external electrode terminal 117 is provided with the stud bump electrode 13 similarly to the second external electrode terminal 117 of the semiconductor chip 1 according to the first embodiment of the present invention (see FIG. 2). See FIG. 2.) As a result, in the semiconductor chip 1 according to the third embodiment of the present invention, the second external electrode terminal 117 is provided at the center of the main surface of the semiconductor substrate 11, and the semiconductor substrate 11
The layout is such that the first external electrode terminals 118 are arranged in the periphery of the main surface of the first embodiment.

The semiconductor chip 1 according to the third embodiment of the present invention thus configured has the same effects as those obtained by the semiconductor chip 1 according to the first embodiment of the present invention. Obtainable.

In the semiconductor chip 1 according to the third embodiment of the present invention, like the second external electrode terminal 117 of the semiconductor chip 1 according to the second embodiment of the present invention, The arrangement of the two external electrode terminals 117 may be staggered.

Further, in the semiconductor chip 1 according to the third embodiment of the present invention, the integrated circuit 12 may be divided into four or more.

(Fourth Embodiment) A fourth embodiment of the present invention relates to an integrated circuit 12 of a semiconductor chip 1 according to the first embodiment of the present invention, particularly an interface circuit (input circuit, output circuit). Or an example in which the power supplied to an input / output circuit or the like is enhanced.

As shown in FIG. 5, a semiconductor chip 1 according to a fourth embodiment of the present invention has a first external electrode terminal 118 used as a power supply voltage external electrode terminal and an integrated circuit 12, especially an interface. The circuit is connected to a second external electrode terminal 117 for supplying a power supply voltage to the circuit by a wiring 118A to enhance the power supply of the interface circuit. The wiring 118A is formed of, for example, a third wiring layer of the same layer as each of the first external electrode terminal 118 and the second external electrode terminal 117. The third wiring layer is used in the sense that it is the uppermost wiring layer of the multilayer wiring structure. Basically, the wiring is not provided except for the first external electrode terminal 118 and the second external electrode terminal 117. Since they are not arranged, such wirings 118A can be arranged relatively easily.

The semiconductor chip 1 according to the fourth embodiment of the present invention thus configured has the same effects as those obtained by the semiconductor chip 1 according to the first embodiment of the present invention. As a result, the power supply of the interface circuit can be strengthened, and the reliability of the integrated circuit 12 in circuit operation can be improved.

(Other Embodiments) Although the present invention has been described with reference to the plurality of embodiments, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

For example, the semiconductor chip 1 according to the first embodiment is formed by a three-layer wiring structure, and the first external electrode terminal 118 and the second external electrode terminal 117 are formed by the third layer wiring. Although the case where the semiconductor chip is formed is described, the present invention relates to a semiconductor chip 1 employing a multilayer wiring structure of four or more layers.
It may be. In the case of such a multilayer wiring structure,
First external electrode terminal 118, second external electrode terminal 117
Can be formed in the uppermost wiring layer.

In the semiconductor device 10 according to the first embodiment, the solder bump electrodes 30 are provided on the external electrode terminals 25 of the wiring board 2 and the solder bump electrodes 31 are provided on the external electrode terminals 26, respectively. However, the present invention
The external electrode terminals 25 and 26 of the wiring board 2 are disposed on the same surface as the first internal electrode terminal 21 and the second internal electrode terminal 22, and each of the external electrode terminals 25 and 26 is mounted on a mounting board or the like through a bonding wire. May be connected.

As described above, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.

[0064]

According to the present invention, it is possible to provide a semiconductor chip capable of increasing the density of the external electrode terminals while achieving a fine pitch of the external electrode terminals.

Further, the present invention can provide a semiconductor chip capable of realizing a high circuit operation speed.

Further, the present invention can provide a semiconductor chip capable of improving noise resistance.

Further, the present invention can provide a semiconductor chip capable of easily realizing a wiring structure.

Further, according to the present invention, it is possible to provide a semiconductor device having a semiconductor chip capable of increasing the density of the external electrode terminals while achieving a fine pitch of the external electrode terminals.

[Brief description of the drawings]

FIG. 1 is a plan view of a main part of a semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is an enlarged sectional view of a main part of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a plan view of a main part of a semiconductor chip incorporated in a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a plan view of a main part of a semiconductor chip incorporated in a semiconductor device according to a third embodiment of the present invention.

FIG. 5 is a main part plan view of a semiconductor chip incorporated in a semiconductor device according to a fourth embodiment of the present invention.

6A is a plan view of a main part of a semiconductor chip according to the prior art of the present invention, and FIG. 6B is an enlarged sectional view of an external electrode terminal portion of the semiconductor chip shown in FIG.

7A is a plan view of a main part of a semiconductor chip according to the prior art of the present invention, and FIG. 7B is an enlarged sectional view of an external electrode terminal portion of the semiconductor chip shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Wiring board 20 Wiring base 21 Second internal electrode terminal 22 First internal electrode terminal 23, 24 Connection hole wiring 25, 26 External electrode terminal 4 Sealing body 10 Semiconductor device 11 Semiconductor substrate 117 Second External electrode terminal 118 First external electrode terminal 118A Wiring 12 Integrated circuit 12A First integrated circuit 12B Second integrated circuit 121 Transistor 130, 131 Barrier metal film 13 Stud bump electrode 14, 15 Solder bump electrode

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/92 604J F-term (Reference) 5F033 HH07 HH09 HH11 HH17 JJ01 JJ07 JJ09 JJ11 JJ17 KK01 KK09 KK11 MM08 MM13 NN06 NN07 VQ07U XX03 5F044 QQ02

Claims (5)

[Claims] A plurality of first external electrode terminals provided on a circuit on a main surface of the semiconductor substrate at predetermined intervals; and a plurality of first external electrode terminals provided on a periphery of the circuit on the main surface of the semiconductor substrate. A semiconductor chip comprising: a second external electrode terminal having a smaller terminal size and a smaller arrangement interval than the terminal. 2. The method according to claim 1, wherein a solder bump electrode is formed on the first external electrode terminal, and a stud bump electrode is formed on the second external electrode terminal. Item 2. A semiconductor chip according to item 1. 3. The semiconductor chip according to claim 2, wherein the first external electrode terminal is used at least as a power supply voltage external electrode terminal. 4. A first external electrode terminal is provided at a central portion or a peripheral portion of the semiconductor substrate main surface, and a second external electrode terminal is provided at a peripheral portion or a central portion of the semiconductor substrate main surface. The semiconductor chip according to claim 1, wherein: 5. A plurality of first external electrode terminals provided at predetermined intervals on a circuit on a semiconductor substrate main surface, and a plurality of first external electrode terminals provided on a periphery of the circuit on the semiconductor substrate main surface. A semiconductor chip including a second external electrode terminal having a terminal size smaller than the terminal and having a small arrangement interval; a first internal electrode terminal corresponding to the first external electrode terminal; A wiring board including a second internal electrode terminal corresponding to the external electrode terminal; a solder bump electrode between the first external electrode terminal and the first internal electrode terminal; and a second external electrode terminal And a stud bump electrode between the first and second internal electrode terminals.