JPS6020588A - Areal emission type light emitting diode - Google Patents

Abstract

PURPOSE:To obtain the titled diode capable of high-speed modulation and facile manufacture by burying the double hetero structure including an active layer and a clad layer by the second clad layer of high resistivity. CONSTITUTION:The double hetero structure is composed of the first clad layer 3a having the impurity concentration enough for confining of injected carriers, an active layer 2a and a semiconductor substrate 1. By the current injection part 51 of 20mum diameter, the current is narrowed and injected into the active layer 2a and the structure operates as the areal emission type light emitting diode in which the emitted light is took out through a light taking-out window 61. The leakage current which flows directly to the semiconductor substrate 1 instead of flowing from the current injection part 51 to the active layer 2a, which often becomes a problem in a buried-in structure, is sufficiently restrained by the second clad layer 4 consisting of the InP having a P type conductive type of high resistivity, a wide forbidden band gap and a large diffusion potential in a junction with the semiconductor substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in surface-emitting light emitting diodes suitable for use in fiber optic communications.

Although surface-emitting light-emitting diodes have the drawback of low output, they have features that semiconductor lasers do not have, such as high reliability + high stability of flA degree characteristics, and are non-coherent light sources and non-threshold operating elements.・A practical element for medium-distance optical transmission.

In particular, the high-speed modulation type device, which shortens the lifetime of carriers injected into the active layer and improves response speed, has a transmission speed of 100M.
It is also possible to construct an optical transmission system of b/s or higher, and a wide range of applications are expected.

Doping impurities at a high concentration is effective for shortening the lifetime of carriers injected into the active layer, and this method has conventionally been used to increase the response speed of surface-emitting light emitting diodes. However, if the impurity concentration in the active layer is increased beyond the injected carrier concentration, the majority carrier drift current in the lateral direction within the plane of the active layer increases, so that the electrical The influence of parasitic admittance, which has a slow response, becomes noticeable. moreover,
Many of the impurities used as dopants in the active layer are easily diffused, and often diffuse into the cladding layer of the same conductivity type during crystal growth, increasing its conductivity, making the effect of parasitic admittance even more pronounced. Therefore, conventional surface-emitting light emitting diodes in which the active layer is simply doped with impurities at a high concentration cannot eliminate the influence of parasitic admittance in the area surrounding the light emitting part due to its structure.
The disadvantage of this method is that it is difficult to perform high-speed modulation exceeding 00 Mb/s.

An object of the present invention is to eliminate the above-mentioned drawbacks, to provide a surface-emitting type light emitting diode that is capable of high-speed modulation and is easy to manufacture.

According to the present invention, an active layer and a first cladding layer having a conductivity type opposite to that of the semiconductor substrate are formed on the mesa of a semiconductor substrate having a mesa structure, and the active layer and the first cladding layer 4 are connected to the first cladding layer 4. A surface-emitting light emitting diode is obtained, which is embedded with a second cladding layer having the same conductivity type as the cladding layer and having a lower cine concentration than the first cladding layer.

Next, the present invention will be explained with reference to the drawings. The drawing represents a cross section of an embodiment according to the invention. This embodiment has a trapezoidal mesa structure, with a mesa upper part 1a and a flat part l.
b, active layers 2a and 2b and first cladding layers 3a and 3b epitaxially grown on a semiconductor substrate l consisting of a mesa side surface portion 1c;

It is composed of a second cladding layer 4, an electrode forming layer 5 including a current injection part 51, an n-side electrode 6 including a light extraction window 61, and a p-side electrode 7. The semiconductor substrate 1 has a (100) orientation and is made of InP doped with Sn 2X10 (''M) and has a thickness of approximately 100/'F#, and the active layers 2a and 2b are made of InP doped with Sn 7XIQ18a-'. ,74Ga
wAs O, 56P [Made from L44, thickness approximately 0.5pm
, the first cladding layers 3a and 3b contain Zn lXl0 3
The second cladding layer 4 is made of doped InP and has a thickness of about 0.5 μm. The second cladding layer 4 is made of Zn doped with 2×10"n-' and has a thickness of about 0.3 pm. The electrode forming layer 5 is made of S.
I n (184Ga
Made from o, 16A+s a, +56Pa64, thickness at flat part 1b approximately 3 μm, thickness at mesa upper part 1a approximately la
It is m. nll1l electrode 6 is A u -G e -N
The PIIIll electrode 7 is made of an Au-Zn alloy. The diameter of the upper mesa 1a is 25 μm
, the height of the mesa upper part 1a from the flat part 1b is 2 μm.

Further, the current injection part 51 is formed by selective diffusion of Zn,
It is located directly above the mesa upper part 1a and has a diameter of 2011 m.

In the +14 structure shown in this example, in liquid phase epitaxial growth of a thin film of 0.5μ7n or less on a substrate having a trapezoidal mesa structure, the growth form on the mesa side surface strongly depends on the degree of supercooling of the growing melt. By applying the properties of If it is made smaller than below, it will not grow into mesa Sentsuku part 1c and the mesa upper part 1
a and flat part 1b, respectively. on the other hand,
If the degree of supercooling of the melt is increased to 10° C. or higher in the liquid phase epitaxial growth of the second cladding layer 4, the second cladding layer 4 will grow without interruption over the entire mesa upper portion 1a and mesa side surface portion IC1 flat portion 1b. Furthermore, if the electrode forming layer 5 is grown to a thickness of about 3 μm on the flat portion 1b, the liquid phase epitaxial growth of a thick film with a growth layer thickness of 1 μm or more has the property of flattening the unevenness of the substrate. is flat, and the structure shown in the example is obtained.

In this embodiment, the double heterostructure has a first cladding layer 3a having a sufficient impurity concentration to confine injected carriers.
A current is constricted and injected into the active layer 2a by a current injection part 51 having a diameter of 20 μm, and the active layer 2a is composed of the semiconductor substrate 1, the active layer 2a, and the semiconductor substrate 1, and operates as a surface-emitting type light emitting diode which extracts light from the light extraction window 61. do. In addition, the side current that does not flow from the current injection part 51 to the active layer 2a but directly to the semiconductor substrate 1, which is often a problem in buried structures, has a high resistivity and a large forbidden band width, so that the junction diffusion potential with the semiconductor substrate 1 is high. is sufficiently suppressed by the second cladding layer 4 made of InP having a large P-type groove conductivity.

In high-speed pulse modulation of a surface-emitting light emitting diode, if the parasitic admittance value in the peripheral area is not sufficiently small compared to the emitter admittance and its time constant is not sufficiently small compared to the modulation pulse period, a significant pulse response will occur. This results in deterioration of characteristics. For example, in a surface-emitting light emitting diode in which an active layer, a first cladding layer, and a second cladding layer with layer structure parameters as shown in the example are formed on a flat substrate, a region within a diameter of 100 μm around the light emitting part is formed. The pn junction capacitance and the expansion resistance of the active layer and cladding layer are parasitic admittances, each of which has a value of 42PF 58
becomes Ω. On the other hand, the operating impedance of the current injection part is 26Ω for one forward current, and since the time constant of parasitic admittance is about 2.4ns, especially 10
Pulse modulation above 0 MVs results in significant degradation of response rise time. The present invention is achieved by electrically connecting in series a resistance that is sufficiently higher than the operating impedance of the current injection section between the light emitting section and the peripheral section. l) )i! 8
This is to reduce the high frequency components of the modulated current flowing to the side portions and to make the value of the parasitic admittance sufficiently smaller than the value of the admittance of the light emitting portion to prevent deterioration of the response. The value of this resistance is approximately 430Ω in the structure shown in the embodiment, which is a sufficiently large value compared to the operating impedance of the stain source injection portion. Therefore, a surface-emitting type light emitting diode capable of high-speed response and hardly affected by parasitic admittance in the peripheral area can be obtained.

Incidentally, the semiconductor material and composition need not be limited to the above-mentioned embodiments, and can be applied to di-V group compound semiconductors of any composition. Furthermore, the manufacturing method of the device does not have to be limited to one-time liquid phase epitaxial growth on a mesa-structured substrate as shown in the example. It may be done separately,
Moreover, the growth method is not limited to liquid phase epitaxial growth method.
A vapor phase epitaxial growth method, a molecular beam epitaxial growth method, or a combination thereof may be used. A buffer layer may be sandwiched between the semiconductor substrate and the active layer. Furthermore, the values of each layer thickness, impurity concentration, mesa structure diameter, mesa height, and current conductive entrance diameter may take any value.

Finally, to summarize the features of the present invention, by embedding a double heterostructure including an active layer and a cladding layer with a second cladding layer having high resistivity, carriers can be injected into the double heterostructure. It is an object of the present invention to provide a surface-emitting type light-emitting diode that provides sufficient confinement, suppresses leakage current, eliminates the influence of parasitic admittance in the peripheral area, and enables high-speed response.

[Brief explanation of the drawing]

The figure is a sectional view of one embodiment of the present invention. In the figure, ■ is the semiconductor substrate, 1a is the upper part of the mesa, lb is the flat part, 1c is the mesa side part, 2a and 2b are active layers, 3a and 3b are the first cladding layer, 4 is the second cladding layer, and 5 51 is an electrode forming layer, 51 is a current injection part, 6 is an NFT11 electrode, 61 is a light extraction window,
7 is a P-side electrode.

Claims (1)

[Claims] An active layer and a first cladding layer having a conductivity type opposite to that of the semiconductor substrate are formed above the mesa of a semiconductor substrate having a mesa structure, and the active layer and the first cladding layer have the same conductivity as the first cladding layer. What is claimed is: 1. A surface-emitting type light emitting diode, characterized in that the surface-emitting type light-emitting diode is embedded with a second cladding layer having a lower cine concentration than the first cladding layer.