JPS6132485A - Semiconductor light emitting element - Google Patents
Semiconductor light emitting elementInfo
- Publication number
- JPS6132485A JPS6132485A JP15362784A JP15362784A JPS6132485A JP S6132485 A JPS6132485 A JP S6132485A JP 15362784 A JP15362784 A JP 15362784A JP 15362784 A JP15362784 A JP 15362784A JP S6132485 A JPS6132485 A JP S6132485A
- Authority
- JP
- Japan
- Prior art keywords
- current
- layer
- stricture
- section
- current stricture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 2
- 208000031481 Pathologic Constriction Diseases 0.000 abstract 12
- 239000003990 capacitor Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000000903 blocking effect Effects 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000000605 extraction Methods 0.000 description 4
- 238000005253 cladding Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910001297 Zn alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/0004—Devices characterised by their operation
- H01L33/0008—Devices characterised by their operation having p-n or hi-lo junctions
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体発光素子に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor light emitting device.
(従来技術とその問題点)
半導体レーザ素子2発光ダイオードなどの半導体発光素
子は小消費電力で高出力・高速変調可能といった特徴を
有し、光フアイバ通信において広く実用に供されている
。このような小消費電力。(Prior art and its problems) Semiconductor light emitting devices such as semiconductor laser devices and light emitting diodes have the characteristics of being capable of high output and high speed modulation with low power consumption, and are widely used in optical fiber communications. Such small power consumption.
高出力・高速変調可能といった特徴を生じせしめるには
、何よりも活性層への効率的な電流挟置構造が必要であ
り、従来より多くの構造の検討がなされている。In order to produce features such as high output and high speed modulation, above all, an efficient current sandwiching structure to the active layer is required, and many structures have been studied in the past.
しかしながら、従来の電流挟置構造は、低周波域におい
ては十分であっても、高周波域においては不十分で、高
速変調特性を低下してしまうといった欠点を有していた
。即ち、活性層をストライプ状に埋め込み電流ブロック
層を活性層に近接させて構成し走埋め込み型半導体レー
ザ素子の場合半導体最上層の拡がシ抵抗が小さい為、半
導体最上層へ高周波′電流が漏れ、電流ブロック層のp
n接合容量が大きな接合容量となシ、高周波域の変調特
性が低下するといった欠点を有していた。又円形電流注
入部により電流を装置・注入する面発光型発光ダイオー
ドにおいても同様な寄生容量により高周波域の変調特性
が低下するといった欠点を有していた。一方、半導体最
上層への高周波電流の漏れを低減する為に、電流注入部
を除く部分の半導体最上層の上部に絶縁膜を形成するこ
とにより寄生容量を低減し、応答特性を改善した報告例
も知られているが、この構造では絶縁膜を部分的に半導
体最上層の上部に形成したことによる絶縁膜のエツジの
ストレスにより活性層の結晶品質の通電劣化が加速され
、実用に供するような半導体発光素子が得られないとい
った欠点を有してhた。However, although the conventional current sandwiching structure is sufficient in a low frequency range, it is insufficient in a high frequency range, and has the drawback of deteriorating high-speed modulation characteristics. In other words, in the case of a trench-embedded semiconductor laser device, in which the active layer is buried in a stripe pattern and a current blocking layer is placed close to the active layer, high-frequency current leaks into the top semiconductor layer because the spreading resistance of the top semiconductor layer is small. , p of the current blocking layer
If the n-junction capacitance is large, it has the disadvantage that the modulation characteristics in the high frequency range deteriorate. Further, surface-emitting light emitting diodes in which current is injected by a circular current injection part also have the drawback that the modulation characteristics in the high frequency range are degraded due to similar parasitic capacitance. On the other hand, in order to reduce leakage of high-frequency current to the top layer of the semiconductor, an insulating film is formed on the top of the semiconductor layer except for the current injection part, thereby reducing parasitic capacitance and improving response characteristics. is also known, but in this structure, the stress on the edges of the insulating film due to the fact that the insulating film is partially formed on top of the top semiconductor layer accelerates the deterioration of the crystal quality of the active layer due to current conduction, making it difficult to put it into practical use. However, it has the disadvantage that a semiconductor light emitting device cannot be obtained.
(第44回応用物理学会学術講演会講演予稿集25a−
P−8)
(発明の目的)
本発明の目的は上述の欠点を除去し、高速応答を可能に
した高信頼な半導体発光素子を提供することにある。(Proceedings of the 44th Japan Society of Applied Physics Academic Conference 25a-
P-8) (Objective of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks and provide a highly reliable semiconductor light emitting device that enables high-speed response.
(発明の構成)
本発明によシ得られる半導体発光素子は、発光に与かる
活性層を備え、この活性層上方に第一の電流挾窄部を有
する電流挾窄層、半導体バッファ層、及び前記第一の電
流挾窄部よりも電流狭窄面積が大きい第二の電流挾窄部
が順次形成され、少なくとも前記第二の電流挾窄部に接
する領域を除く部分の前記半導体バッファ層がI X
10” cm−”よりも低いキャリア濃度のP型溝電型
を有することを特做とする。(Structure of the Invention) A semiconductor light emitting device obtained according to the present invention includes an active layer that participates in light emission, a current confinement layer having a first current confinement portion above the active layer, a semiconductor buffer layer, and A second current confinement portion having a larger current confinement area than the first current confinement portion is sequentially formed, and at least a portion of the semiconductor buffer layer excluding a region in contact with the second current confinement portion is IX.
It is characterized by having a P-type trench electric type with a carrier concentration lower than 10"cm-".
(実施例) 次に図面を参照して本発明の詳細な説明する。(Example) Next, the present invention will be described in detail with reference to the drawings.
第1図は、本発明に基づく一実施例の断面を表わすもの
である。本実施例は、半導体基板1にエピタキシャル成
長された活性層2.クラッド層3゜第一の電流挾窄部4
1を含む電流狭窄層4.fi流注入部51を含む半導体
バッファ層5及び第二の電流挾窄部61を含む絶縁膜6
.光取出し窓71を含むn側電極7.p側電極8から構
成されている。半導体基板1は(It)0)方位を有し
、SnがI X 10”crn−’ドープされたInP
から成夛厚さi o Oam e活性層2はZnが7X
10 cm ドープされたIn0.74G”0.2
6A80.56P0.44から成シ厚さ0.5 fim
pクラッド層3はZnが1×10 crn ドープさ
れたInPから成り厚さ1μm、’を流挟置層4はSn
が1×10cInドープされ71c In0.85G”
O,IgA8G、36PO,g4から成夛厚さ0.5μ
mである。半導体バッファ層5はZnがドープされ7’
m In(L84G”0.16A80.36’P0.6
4から成り、そのキャリア濃度は低ければ低い程良く、
層厚は薄ければ薄い程良いが、実施例においては製造歩
留りの点よりキャリア濃度は5X10 cm 、層厚
は0.5μmとしている。絶縁膜6はstowから成シ
厚さ0.3μmv”側1!極7はAu −Qe −Ni
合金から成シ厚さ0.3μm 、 pHllE極8はA
u−Zn合金から成〕厚さ0.3μmである。第一の電
流挾窄部41及び電流注入部51は、直径20/jfi
のZn選択拡散を電流挾窄層4及び半導体バッファ層5
中に施すことにより形成されている。第二の電流挾窄部
61は絶縁膜6を直径30μmエツチングにより除去す
ることにより形成され、又光取出し窓71はn側電極7
を直径120μmエツチングによシ除去することにより
形成されている。本実施例は、その動作時において直径
20μmの第一の電流挾窄部41により活性層2へ電流
が狭窄・注入され光取出し窓71から発光を取出す面発
光型発光ダイオードとして動作する。FIG. 1 shows a cross section of an embodiment according to the present invention. In this embodiment, an active layer 2. epitaxially grown on a semiconductor substrate 1. Cladding layer 3゜first current confinement part 4
4. A current confinement layer containing 1. Semiconductor buffer layer 5 including fi current injection part 51 and insulating film 6 including second current confinement part 61
.. An n-side electrode 7 including a light extraction window 71. It is composed of a p-side electrode 8. The semiconductor substrate 1 has an (It)0) orientation and is made of InP doped with Sn I x 10"crn-'
The active layer 2 has a thickness of 7X Zn.
10 cm Doped In0.74G”0.2
Made from 6A80.56P0.44 thickness 0.5 fim
The p cladding layer 3 is made of InP doped with 1×10 crn of Zn and has a thickness of 1 μm.
is doped with 1×10cIn and 71cIn0.85G”
Constructed from O, IgA8G, 36PO, g4, thickness 0.5μ
It is m. The semiconductor buffer layer 5 is doped with Zn 7'
m In(L84G"0.16A80.36'P0.6
4, and the lower the carrier concentration, the better.
The thinner the layer thickness, the better; however, in the examples, from the viewpoint of manufacturing yield, the carrier concentration is 5×10 cm and the layer thickness is 0.5 μm. The insulating film 6 is formed from stow and has a thickness of 0.3 μm on the side 1! The electrode 7 is Au-Qe-Ni.
Made of alloy, thickness 0.3μm, pHllE electrode 8 is A
It is made of u-Zn alloy and has a thickness of 0.3 μm. The first current blocking part 41 and the current injection part 51 have a diameter of 20/jfi.
The selective diffusion of Zn is carried out in the current blocking layer 4 and the semiconductor buffer layer 5.
It is formed by applying it inside. The second current confinement portion 61 is formed by etching the insulating film 6 to a diameter of 30 μm, and the light extraction window 71 is formed by etching the insulating film 6 to a diameter of 30 μm.
It is formed by etching and removing a diameter of 120 μm. During operation, this embodiment operates as a surface-emitting type light emitting diode in which current is constricted and injected into the active layer 2 by the first current confining portion 41 having a diameter of 20 μm, and light is extracted from the light extraction window 71.
実施列において、第二の電流挾窄部61の径は第一の電
流挾窄部41の径より十分大きい為、絶縁膜を部分的に
半導体最上層の上部に形成したことによる絶縁膜のエツ
ジのストレスが発光部周辺に加わることがなく高い素子
の信頼性が得られる。In the practical row, the diameter of the second current interlocking part 61 is sufficiently larger than the diameter of the first current interlocking part 41, so that the edge of the insulating film due to the insulating film being partially formed on the uppermost semiconductor layer. High reliability of the device can be obtained because stress is not applied to the vicinity of the light emitting part.
一方、直流、低周波域において、活性層2への注入電流
は逆バイアスされたpn接合から成る第一の電流挾窄部
41により狭窄・注入されるが高周波域においては鷹流
挟置層4に寄生する大きなpn接合容量により第二の眠
流挟置部61から半導体バッファ層5の拡がシ抵抗を通
して流れる高周波電流の漏れが応答の劣化をもたらす。On the other hand, in the direct current and low frequency range, the current injected into the active layer 2 is constricted and injected by the first current confinement part 41 consisting of a reverse biased pn junction, but in the high frequency range, the current injected into the active layer 2 is Due to the large pn junction capacitance parasitic to the semiconductor buffer layer 5, leakage of high frequency current flowing through the resistor from the second interposed current intervening portion 61 causes response deterioration.
本実施例では、電流注入部51を除く半導体バッファ層
5が1×10 cm よりも低いP型溝電型を有す
ることからその抵抗率が十分に高く、かつp側電極8.
絶縁膜6及び半導体バッファ層5から成るMIS’ll
−*が素子の応答特性に影響をおよぼさない程度に十分
に小さい為、電流倒窄層4に寄生するpn接合答景を流
れる高周波電流の漏れを素子の応答特性に影響をおよぼ
さない程度に小さく抑えることが可能である。例えば素
子の大きさを300μm角とした場合、第一の電流挾窄
部41の上に半導体バッファ層5をはさまず、直接第二
の電流挾窄部61を形成した従来構造の素子におりては
寄生容量は約2007)pとなシ、大きな応答特性の劣
化をもたらし、変調速度も100 Mb/ s程度が限
界となるが本発明を適用した実施例においては寄生容量
は実効的に約20〃まで低減され、200Mb/s以上
の高速パルス変調が可能となる。In this embodiment, since the semiconductor buffer layer 5 excluding the current injection part 51 has a P-type trench conductivity type lower than 1×10 cm 2 , its resistivity is sufficiently high, and the p-side electrode 8.
MIS'll consisting of an insulating film 6 and a semiconductor buffer layer 5
-* is sufficiently small that it does not affect the response characteristics of the element, so the leakage of high-frequency current flowing through the pn junction parasitic to the current collapse layer 4 does not affect the response characteristics of the element. It is possible to keep it as small as possible. For example, when the size of the device is 300 μm square, the semiconductor buffer layer 5 is not sandwiched over the first current confinement portion 41, and the second current confinement portion 61 is directly formed on the device. In this case, the parasitic capacitance is approximately 2007)p, which causes a large deterioration of the response characteristics, and the modulation speed is also limited to about 100 Mb/s, but in the embodiment to which the present invention is applied, the parasitic capacitance is effectively reduced to approximately 20, enabling high-speed pulse modulation of 200 Mb/s or more.
尚、本発明は、面発光型発光ダイオードに限らず、半導
体レーザ素子など、あらゆる半導体発光素子に適用可能
である。半導体材料及び組成は、上述の実施例に限定す
る必要はなく、あらゆる組成の■−v族化合物半導体に
適用可能である。不純物、絶縁膜材料、電極金属材料も
上述の実施例に限定する必要はない。又、電流挟置構造
も、本実施例に示した構造に限らず、電流を装置する機
能を有するものであれば、いかなる構造にも適用可能で
ある。Note that the present invention is applicable not only to surface-emitting light emitting diodes but also to all semiconductor light emitting devices such as semiconductor laser devices. Semiconductor materials and compositions do not need to be limited to the above-mentioned embodiments, and can be applied to group 1-v compound semiconductors of any composition. There is no need to limit the impurities, insulating film materials, and electrode metal materials to those in the above-mentioned embodiments. Further, the current sandwiching structure is not limited to the structure shown in this embodiment, but can be applied to any structure as long as it has the function of supplying current.
(発明の効果)
最後に本発明が有する特徴を要約すれば、第一の電流挾
窄部と、それよシミ流装置面積が大きい第二の電流挾窄
部の間に、少なくとも第二の電流挾窄部の部分のキャリ
ア濃度がlXl0 cm より低いP型導電型であ
る半導体バッファ層をはさむことによシ、寄生容it低
減し高速パルス変調が□可能な高信頼な半導体発光素子
が得られることである。(Effects of the Invention) Finally, to summarize the features of the present invention, at least a second current By sandwiching a semiconductor buffer layer of P-type conductivity type in which the carrier concentration in the narrow part is lower than lXl0 cm, a highly reliable semiconductor light-emitting device capable of reducing parasitic capacitance and performing high-speed pulse modulation can be obtained. That's true.
第1図は本発明の一実施例の断面図である。図中、1は
半導体基板、2は活性層、3はクラッド層、4は電流挾
窄層、41は第一の電流挾窄部。
5は半導体バッファ層、51は電流注入部、6は絶縁膜
、61は第二の電流挾窄部、7はn側電極。
71は光取出し窓、8はp側電極である。FIG. 1 is a sectional view of an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is an active layer, 3 is a cladding layer, 4 is a current blocking layer, and 41 is a first current blocking portion. 5 is a semiconductor buffer layer, 51 is a current injection part, 6 is an insulating film, 61 is a second current confinement part, and 7 is an n-side electrode. 71 is a light extraction window, and 8 is a p-side electrode.
Claims (1)
電流挾窄部を有する電流挾窄層、半導体バッファ層、及
び前記第一の電流挾窄部よりも電流挾窄面積が大きい第
二の電流挾窄部が順次形成され、少なくとも前記第二の
電流挾窄部に接する領域を除く部分の前記半導体バッフ
ァ層が、1×10^1^5cm^−^3よりも低いキャ
リア濃度のP型導電型を有することを特徴とする半導体
発光素子。The active layer is provided with an active layer that participates in light emission, a current trapping layer having a first current trapping portion above the active layer, a semiconductor buffer layer, and a second current trapping layer having a larger current trapping area than the first current trapping portion. Two current confinement portions are sequentially formed, and at least a portion of the semiconductor buffer layer excluding a region in contact with the second current confinement portion has a carrier concentration lower than 1×10^1^5 cm^-^3. A semiconductor light emitting device characterized by having a P-type conductivity type.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15362784A JPS6132485A (en) | 1984-07-24 | 1984-07-24 | Semiconductor light emitting element |
CA000487312A CA1251549A (en) | 1984-07-24 | 1985-07-23 | Semiconductor light emitting device |
EP85305212A EP0170481B1 (en) | 1984-07-24 | 1985-07-23 | Semiconductor light emitting device |
DE8585305212T DE3581333D1 (en) | 1984-07-24 | 1985-07-23 | LIGHT-EMITTING SEMICONDUCTOR DEVICE. |
US06/758,237 US4670689A (en) | 1984-07-24 | 1985-07-24 | Semiconductor light emitting diode with high operating speed |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15362784A JPS6132485A (en) | 1984-07-24 | 1984-07-24 | Semiconductor light emitting element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6132485A true JPS6132485A (en) | 1986-02-15 |
Family
ID=15566631
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15362784A Pending JPS6132485A (en) | 1984-07-24 | 1984-07-24 | Semiconductor light emitting element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6132485A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62194218A (en) * | 1986-02-21 | 1987-08-26 | Kokusai Denshin Denwa Co Ltd <Kdd> | Semiconductor optical modulator |
-
1984
- 1984-07-24 JP JP15362784A patent/JPS6132485A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62194218A (en) * | 1986-02-21 | 1987-08-26 | Kokusai Denshin Denwa Co Ltd <Kdd> | Semiconductor optical modulator |
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