JPS60205637A - Data processor - Google Patents

Abstract

PURPOSE:To expand the influence range of an erroneous check due to pseudo fault data by providing the 1st, the 2nd, and the 3rd function circuits, registers in which a fault report of a fault check is registered, and an inhibiting circuit which inhibits the fault report. CONSTITUTION:When error simulation is performed assuming that a parity error occurs to the 1st function circuit 1, pseudo error data on a common bus 5 is inputted to only a register 11 according to a microprogram (MP) and not inputted to a register 21. Consequently, a parity check result from a parity checking circuit 12 is registered in an error storage register 41. Parity check results of the 2nd and the 3rd function circuits 2 and 3 are also inputted to the error storage register 41. Hardware, firmware, and software are checked by MP on the basis of the registration contents.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a data processing device, and more particularly, to a data processing device comprising a plurality of functional circuits each having a failure checking function, the functional circuits excluding at least one of the plurality of functional circuits. relates to propagation control of pseudo-failure data in data processing devices connected to a common bus.

(Technical background) Relatively large-scale data processing devices such as central processing units are designed to speed up processing operations, parallelize processing operations, shorten design periods, and improve maintainability. It is often configured by being divided into a plurality of functional circuits, such as a JTL control unit, a sequential control unit, an address translation unit, and a fault diagnosis unit. Each of these functional circuits is connected to a common bus, except for some functional circuits such as the sequential control unit.
In addition, each of them generally has a failure checking function.

These fault checking functions not only check the correctness of the operation of the functional circuit during operation, but also check the correctness of each hardware, firmware, and software using simulated fault data before starting operation. It is also used to guarantee sex. It is desired that the check using pseudo-fault data be simple and have a sufficient range of influence.

(Prior Art) A first conventional data processing device of this type exclusively stores a plurality of functional circuits each having a parity check function and a failure report based on the parity check in each of the functional circuits. A pseudo fault report generated by a microprogram is directly set in the fault storage register to make it appear as if a fault has occurred in the functional circuit.

In such a first conventional configuration, since the pseudo-fault report is not from the functional circuit, the functional circuit has no pseudo-fault data, the range of fault spread is narrow, and there is not enough data to prepare for an actual fault. The runner-up is not being able to do a sufficient shimmy range.

A conventional second data processing device of this type includes: a plurality of functional circuits each having a parity check function and in which parity bits in some registers can be inverted by a microprogram; a fault storage register for exclusively storing fault reports based on parity checks in the circuit, pseudo fault data is set in the register by a microprogram, and fault reports are generated from the functional circuit based on this pseudo fault data. is set in the fault storage register.

In such a second conventional configuration, the scope of the check can be expanded, but there is a drawback that the amount of hardware increases.

(Object of the Invention) An object of the present invention is to provide a data processing device that can expand the range of error checking using pseudo failure data by adding only a small amount of hardware.

(Structure of the Invention) The device of the present invention is a data processing device comprising a plurality of functional circuits each having a failure checking function, and in which the functional circuits except at least one of the plurality of functional circuits are connected to a common bus. In the device, a first functional circuit capable of generating pseudo-fault data and sending it to the common bus; a second functional circuit having a path from which the pseudo-fault data is to be selected; and from the second functional circuit. a third functional circuit that receives the simulated failure data and is not connected to the common bus; and - registers a failure report based on each of the failure checks in the first functional circuit, the second functional circuit, or the third functional circuit; The present invention is characterized by comprising: a fault storage register; and a fault registration suppression circuit capable of suppressing registration of the fault report from the second functional circuit in the fault storage register.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Referring to FIG. 1, this embodiment includes a first functional circuit 1 and a second functional circuit 2 connected to a common bus 5,
It is composed of two third functional circuits 3 and 4 that are not connected to. The first functional circuit 1 and the second functional circuit 2 are
The arithmetic unit, preemption control unit, and address conversion unit may be any one of the above units, or the third
The functional circuits include a 3-sequential control unit, etc., the third functional circuit 4 is a fault diagnosis unit, and other functional circuits (not shown) constituting this central processing unit are also the first functional circuit, the second functional circuit, etc.
It can be classified as either a functional circuit or a tertiary functional circuit.

The first functional circuit 1 includes a register 11, a parity check circuit 12, a 7-lip flop 13, and an exclusive OR circuit 14, and the second functional circuit 2 and the third functional circuit 3 each include a register 21 and a parity check circuit 14. A fourth functional circuit 4 including a circuit 22, a register 31, and a parity check circuit includes an error storage register 41 and a write control circuit 4.
2 and 17 lip-flops 43 and an AND circuit 44.

The registers 11 and 21 are existing registers that are directly connected to the common bus 5, and the register 31 is directly connected to the register 21, and are not provided for implementing the present invention. The register 11 can input data for generating a pseudo error by the microprogram MP, and the flip-flops X3 and 43 can be set/reset by the microprogram MP.

Parity check circuits 12.22 and 32 perform parity checks based on the contents held in registers 11.21 and 31, respectively, and the results are stored in error storage register 41 by write control circuit 42 and flip 70 tube 43.
written under the control of The write control circuit 42 checks the contents held in the error storage register 41, and if any parity check result indicating the occurrence of a parity error has already been stored, a new parity check result is not stored until this parity check result is cleared. The parity check result is not written. However, when the flip-flop 43 is in the set state, the parity check result in the parity check circuit 22 is not written to the error storage register 41, regardless of the contents held in the error storage register 41.

The contents held in the register 11 are output to the common path 5 as they are except for the parity pit. The parity pit output onto the common path 5 is obtained by performing an exclusive OR operation on the parity bit of the register 11 and the output of the 7-lip flop 13 in an exclusive OR circuit 14, and outputting the result to the common bus 5. Ru.

Now, a case will be described in which a pseudo parity error is generated in each functional circuit using pseudo error data.

First, according to instructions from a microprogram control circuit (not shown), data with a correct parity bit is input to the register 11, and the flip 7"70 tab 13 is set. As a result, the parity pit is exclusive. The logical sum circuit 14 inverts the data, and the first functional circuit 1 outputs pseudo error data to the common bus 5 that causes a parity error.

The pseudo error data outputted from the common bus 54C is input to all the second functional circuits 2 connected to the common bus 5 and the third functional circuit 3 connected to the second functional circuits 2, and is also input to the first functional circuit 3. When generating a pseudo parity error in the circuit 1, there is also a path (not shown) that can be input to the register 11 by the microprogram MP.

In this way, the first functional circuit 1. The pseudo error data inputted into the second functional circuit 2 and the third functional circuit 3 are checked for parity in parity check circuits 12, 22 and 32, respectively, via registers 11, 21 and 31, respectively.

Since the parity bit of the pseudo error data to be subjected to the parity check has been previously inverted in the exclusive OR circuit 14, the parity check outputs a parity check result indicating the occurrence of a parity error.

Both parity check results are stored in error storage register 4.
However, the write control circuit 42 operates to register only one parity check result in the error storage register 41 on a first-come, first-served basis. For the propagation path of the pseudo error data as described above, the error storage register 41
Whichever comes first is the parity check result from the parity check circuit 12 or the flip-flop 43.
Is this the parity check result from the parity check circuit 22 when is in the reset state?

When performing an error simulation assuming that a parity error has occurred in the first functional circuit 1, the pseudo error data on the common bus 5 is inputted only to the register 11 by a microprogram, and is not inputted to the register 21. Based on this result, the parity check result from the parity check circuit 12 can be registered in the error storage register 41.

When performing an error simulation assuming that a parity error has occurred in the second functional circuit 2, the pseudo error data on the common bus 5 is inputted only to the register 21 by a microprogram and not inputted to the register 11, and The lip 70 knob 43 is put into a reset state. Based on this result, the parity check circuit 2
The parity check result from 2 is registered in the error storage register 41 via the AND circuit 44.

Further, when performing an error simulation assuming that a parity error has occurred in the third functional circuit 3, the pseudo error data on the common bus 5 is prevented from being input to the register 11 by a microprogram, and the flip-flop 431 is set to a set state. As a result, the parity check result from the parity check circuit 22 is prevented from passing through the AND circuit 44, and the parity check result from the parity check circuit 32 can be registered in the error storage register 41.

As described above, when the parity check results from any one are registered in the error storage register 41, the microprogram MP checks the hardware, the error code, and the software based on the registered contents.

In the present embodiment shown in FIG. 1, the first functional circuit 1.
Although only one second functional circuit 2 and one third functional circuit 3 are shown to simplify the drawing, there may be a plurality of each.

Further, the third functional circuit 4 may be configured as a first functional circuit or a second functional circuit by being connected to the common bus 5.

(Effects of the Invention) According to the present invention, by employing the above-described configuration, it is possible to expand the range of error checking using pseudo-fault data with only a small addition of hardware.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the invention. 1...First functional circuit, 2...Second functional circuit.
3゜4...Third functional circuit, 5...Common bus, 11
, 21 , 31... register, 12.22.32...
- Parity check circuit, 13. 43... Flip-flop, 14... Exclusive OR circuit, 41... Error storage register, 42 Fig. 1

Claims (1)

[Scope of Claims] A data processing device comprising a plurality of functional circuits each having a failure checking function, and in which functional circuits other than at least one of the plurality of functional circuits are connected to a common bus, comprising: a first functional circuit capable of generating data and transmitting it to the common bus; a second functional circuit having a path from which the pseudo-fault data is to be selected; and a second functional circuit capable of transmitting the pseudo-fault data from the second functional circuit. a third functional circuit that is not connected to the common bus; and a fault storage register for registering a fault report based on each of the fault checks in the first functional circuit, the second functional circuit, or the third functional circuit. and a fault registration suppression circuit capable of suppressing registration of the fault report from the second functional circuit in the fault storage register.