JPH0512047A - Error detecting circuit - Google Patents

Abstract

PURPOSE:To improve the reliability by converting an address and an error detection code and masking an influence of control signals, whose combination is contradictory to correlations, to prevent spread of the influence of control signals including error. CONSTITUTION:When control signals are inputted to an address generating circuit 20, this circuit 20 generates an address to be sent to a control storage 10 based on control signals. A contradiction detecting means 30 monitors whether control signals are contradictory to correlations to be found or not. If they are contradictory, a contradiction detection signal is sent to a converting means 40. When this signal is present in the converting means 40, the address and the error detection code which are generated by control signals where contradictions are detected are converted to an address and an error detection code of error by a check part 10a. Thus, the influence of control signals whose combination is contradictory is masked, and the other parts are not affected by these control signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detection circuit used in a processor or the like, and more particularly to a microprogram,
A control memory that stores various programs or data,
An address generation circuit that generates an address and an error detection code to be input to the control memory from a plurality of control signals that at least partially include a combination that should have a certain kind of correlation, and an error detection code check The present invention relates to an error detection circuit that has an inspection unit and detects an error in an address.

[0002]

2. Description of the Related Art Conventionally, there has been an error detection circuit for detecting an error in an address of a control memory of a processor as shown in FIG. As shown in the figure, this circuit includes a control memory 1 for storing a microprogram, etc., an address generation circuit 2 for generating an address and a parity for the control memory 1 based on various control signals, and a parity check. The inspection unit 1a for performing the above operation and the switching circuit 5 for switching to various circuits are provided to detect an erroneous address in the control memory 1. Further, data in the control memory 1 is similarly provided with parity so that the circuit does not operate by using the data of the address which should not be used. In such a case, parity-added data for detecting is stored in advance so that the circuit does not malfunction even if an unused area address is erroneously generated.

[0003]

By the way, in the error detecting circuit according to the conventional example, it is usual to detect only by the parity error as described above, and the parity error for the address is detected. Since it was designed to prevent malfunctions, it prevents malfunctions only when an incorrect address generated by an incorrect control signal happens to be a parity error, but when an error in the control signal affects multiple bits of the address, etc. There was a case where the circuit malfunctioned even though the address was incorrect, though no error was detected. Further, if the address that is generated by mistake and the error is not detected accidentally indicates the unused area of the control memory 1, the parity check unit 1b can prevent the malfunction, but the unused area in the control memory is originally used. However, there is a problem that the circuit malfunctions as in the above case.

Therefore, the present invention utilizes a combination of a plurality of control signals, at least a part of which includes a combination having a certain kind of correlation, to make use of the control signal itself which originally has no error detection code. The purpose of this invention is to provide a reliable error detection circuit by effectively preventing the malfunction that occurs in the control memory by adding the error check of (1).

[0005]

In order to solve the above technical problems, as shown in FIG. 1, a plurality of control memories 10 and a plurality of combinations at least part of which should have a certain kind of correlation are included. An address generation circuit 20 for generating an address and an error detection code input to the control memory 10 from a control signal, and an inspection unit 10a for inspecting the error detection code.
In the error detection circuit for detecting an error of the address having the following, when the combination of the control signals that should have the correlation is detected to be inconsistent with the correlation, the contradiction detection means 30 which outputs the contradiction detection signal is output. When the detection signal is output, the address and the error detection code generated by the address generation circuit 20 are output to the check unit 10a.
The conversion means 40 is provided to shield the influence of the control signal containing the combination inconsistent with the correlation by converting the address into the error and the error detection code.

[0006]

Next, the operation of the error detection circuit according to the present invention will be described. The present invention utilizes the correlation when the control signal to which the error detection code is not added includes a combination having a certain correlation in at least a part thereof. Error detection is added to effectively detect errors. Here, the "error detection code" is a code for the purpose of detecting a data error, and is, for example, a parity code. Also,
The "certain correlation" means, for example, a control signal,
It is a relationship such as a control signal which is always the relationship in which the signal is inverted. Generally, an error detection code such as parity is not added to the control signal, and in the past it is not possible to detect an error in the control signal itself, but in the present invention, some control signals The error of the control signal itself is detected by utilizing the fact that there is a correlation in the combination of. When a control signal is input to the address generation circuit 20, the circuit 20 generates an address to be sent to the control memory 10 based on the control signal. At that time, the generation circuit 20 also creates the parity based on the control signal. On the other hand, the control signal is input to the address generation circuit 20, and the contradiction detection means 30 is also provided.
Also enter. The contradiction detection means 30 monitors whether there is a contradiction in the correlation that should be found between the control signals, and if there is a contradiction, sends a contradiction detection signal to the conversion means 40. . When the contradiction detection signal is present in the conversion means 40, the conversion means 40 determines the address generated by the control signal in which the contradiction is detected and the created error detection code as an error in the inspection unit 10a. The address of the control signal is converted into an address and an error detection code, and the influence of the control signal including the inconsistent combination is shielded so that the influence of the control signal does not spread to others. Here, as the address and the error detection code which are erroneous in the inspection unit 10a, an address which designates an unused area of the control memory 10 (the error detection code which causes an error is added to such an address). May be).

[0007]

EXAMPLES Next, examples of the present invention will be described.
FIG. 2 shows an error detection circuit according to the embodiment. In the present embodiment, as shown in the figure, from the control memory 10 for storing a microprogram and the like, and a plurality of control signals including at least a part of a combination that should have a certain kind of correlation, A combination of an address generation circuit 20 that generates an address and an error detection code input to the control memory 10, a check unit 10a that checks the error detection code, and a control signal that should have the above correlation has the correlation. When a conflict is detected, the conflict detection circuit 3 is a conflict detection means 30 that outputs a conflict detection signal, and when the detection signal is output, the address and error detection generated by the address generation circuit 20 are detected. Code the inspection unit 10a
The mask circuit 4 is provided as the conversion means 40 for shielding the influence of the control signal including the combination inconsistent with the correlation by converting the address into the error and the error detection code. Further, the mask circuit 4 has an inverting element 4b and an AND element 4a as shown in the figure, and the contradiction detection circuit 3 causes the contradiction detection signal "1".
Is output, a "0" address designating one of the unused areas of the control memory 1 and a "0" parity indicating that the designation is erroneous are output. In addition, in this embodiment, as shown in FIG.
A parity check circuit 1b is provided, and various circuits include a bus control unit 6, a storage control unit 7, and an arithmetic circuit 8 as shown in FIG. FIG. 3 shows the inside of the control memory 1. As shown in FIG.
Has a used area and an unused area,
The unused area adds erroneous parity to the data.

Next, the operation of this embodiment will be described. When the control signal is input to the address generation circuit 2, the circuit 2 generates an address based on the control signal, and creates a parity based on the control signal. On the other hand, the control signal is input to the address generation circuit 2 and the contradiction detection circuit 3. When the detection circuit 3 detects a contradiction with respect to a certain combination of the control signals, it outputs a "1" signal, which is a contradiction detection signal, to the mask circuit 4. The signal is inverted by the inverting element 4b, and the "0" signal is input to the AND element 4a. Then, the address and parity generated by the address generation circuit 2 are converted into a "0" signal by the AND element 4a and output. At that time, the "0" signal is the address "0".
And parity "0", and address "0"
As shown in FIG. 3, indicates an unused area, and parity “0” indicates an error parity for the address “0”. Therefore, when a contradiction occurs in the control signal, an erroneous address is specified for the control memory 1, and the address generated by the contradiction control signal is not transmitted to the control memory 1. Therefore, the propagation of error can be prevented. On the other hand, when the contradiction detection circuit 3 detects no contradiction, the circuit 3 outputs a "0" signal to the inverting element 4b of the mask circuit 4, and a "1" signal is output from the AND element 4a. Therefore, the address and parity output from the address generation circuit 2 are sent to the parity check unit 1a of the control memory 1 as they are, and the normal parity check is performed. As a result, if no error is detected, the data is sent to the control memory 1 and the corresponding data and parity are output from the corresponding used area. At this time, if no error is detected by the parity check unit 1b, the switching unit 5 switches to the corresponding various circuits and the data is transmitted. Note that the mask circuit 4 is not limited to the above example, and can be configured by using various logic elements, but a simpler circuit is preferable because failure is less likely to occur.

[0009]

As described above, according to the present invention, a combination of control signals that should have a correlation with various control signals used when generating an address to be input to the control memory is the correlation. In addition to providing contradiction detection means for detecting whether or not there is a contradiction in the relationship, exchange means for shielding the influence of the control signal containing the inconsistent combination is provided according to the output signal of the detection means. Therefore, according to the present invention, the error of the control signal itself to which the error detection code is not added is detected to some extent, the spread of the influence of the control signal including the error is prevented, and reliable error detection is performed. A circuit could be provided.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the invention.

FIG. 2 is a block diagram according to an embodiment.

FIG. 3 is a diagram showing the contents of control storage according to the embodiment.

FIG. 4 is a block diagram according to a conventional example.

[Explanation of symbols]

10,1 control memory 10a (1a, 1b) check unit (parity check unit) 20, 2 address generation circuit 30 (3) Contradiction detection means (contradiction detection circuit) 40 (4) Conversion means (mask circuit)

Claims (2)

[Claims] 1. An address and an error detection code input to the control memory (10) from a plurality of control signals, at least a part of which includes a combination which should have a certain correlation with the control memory (10). Address generation circuit (2
0) and an inspection unit (10a) for inspecting the error detection code.
In an error detection circuit for detecting an error in an address having a, a contradiction detection unit that outputs a contradiction detection signal when it is detected that a combination of control signals that should have the above-mentioned correlation conflicts with the correlation ( 30), and when the detection signal is output, the address and the error detection code generated by the address generation circuit (20) are converted into an address and an error detection code which are regarded as an error by the check unit (10a). By doing so, the error detecting circuit is provided with the converting means (40) for shielding the influence of the control signal including the combination inconsistent with the correlation. 2. An error detection circuit, wherein the address converted and output by the conversion means according to claim 1 is an address for an unused area of the control memory (10).