JPS5821174A - Inspecting circuit - Google Patents

Abstract

PURPOSE:To constitute an inspecting circuit systematically and to improve the reliability of logical circuits by expressing and handling the circuits to be inspected in the standard form of Reed-Muller expressed by the OR ELSE of product terms. CONSTITUTION:The outputs of combined multiple output circuit N1 having (n) inputs x0-xn-1 and (r) (r>=2) outputs y0-yr-1 are divided to (l) (2<=l>=r) groups. An inspecting circuit 2 is so constituted that when the OR ELSEs of the respective outputs belonging to said groups (i) (i=0-l-1) are defomed as gi, the functions of x0-xn-1 as (h), and the functions of x0-xn-1 which are so selected that g0(+)f0=g1(+)f1=...=gl-1(+)fl-1=h ((+): OR ELSE) holds at all times when the circuit 1 is normal are defined as fi, the (l) outputs conform to the logical equations zi=gi(+)fi(0<=i<=l-1).

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a test circuit for testing the normality of a multi-output combinational circuit in order to improve its reliability.

Conventionally, when the circuit to be tested is a data bus type circuit that handles data, the conventional testing method for multi-output combinational circuits is to add redundant sign bits to the data, perform processing on the data, and then check whether the circuit is correct. Mainly used are test circuits that test whether the code is 0 or not, and test circuits that simply duplicate the target circuit and test whether the outputs match. On the other hand, if the target is a control system circuit, a 1/N test circuit is used for the decoder to test whether only one output has a different value from other outputs; Only special circuits are provided. Generally, control system circuits are
Due to the strong randomness, no effective inspection method is known other than double inspection of a large amount of metal objects.

Furthermore, since the test circuit generally receives the output of the circuit to be tested as an input, it may not be possible to detect a failure in the test circuit itself. In other words, when the target circuit is normal, only the output when the target circuit is normal is input to the test circuit.
Faults that can be detected at this time can be tested, but other faults that can only be detected after two faults cannot be detected unless an error occurs in the output of the target circuit. There is a pseudo-failure method in which two additional circuits are provided and the test is conducted so that input can be performed, but this method has the drawback of requiring extra additional circuits, additional terminals, etc., and increasing the amount of hardware required.

In order to solve these drawbacks, the present invention provides a test circuit which requires a small amount of hardware and has self-testing properties, as opposed to an arbitrary multi-output combinational circuit, and will be described in detail below.

1 and 2 show an example of a test performed by the test circuit of the present invention. 1 indicates the target multi-output combinational circuit N, and 2 indicates the same result Zi( 1=0,1,2
．． ..., t-1), and 3 is an example of a test circuit that outputs the test result (co, C1).

To derive test circuits 2 and 3, the circuit N to be tested is represented by the exclusive OR of product terms, Reed-Mu
l Ier standard It is handled as a standard expression. In general, any logical function can be expressed using the standard form 1(4ed -11Jul er), where L, T, F 1she
r (' I E E E Trans, vo ”
23 + N[L 2 + pp166 + 1.
It is known from the literature such as 974). That is, an arbitrary logical function y (Xo, xl, . . . + Xn-1) is expressed as in the following equation.

Y (XO+Xl+””+xn-1)=”0
■a1・Xo■a2・x1■a3−XO°X1■°°°
■a2n-1・xo-xl...Xn-1...
(1) Here, °゛・' represents a logical product, "'■''' represents an exclusive OR, and ak represents a logical value of 10" or "1".

Extending this to a multi-output combinational circuit with n inputs and r outputs... (2) Here, Σ is modulo 2 (D sum, akj represents a logical value of 0 or 1, and j ” jn −1' 2°
-' +-+ jl ・21+'' When expressed as a double number, uj is A=(a+cj)rx2'', y-(
・yk・)T , II= (-・・u)...)T
Then, equation (2) can be expressed as the following equation. Here ()T
represents the transposed matrix.

y=A-traction...(3) However, the sum during matrix calculation is an exclusive OR.

Here, if the output of circuit N is divided into groups fixed to t1 (2≦t≦r), the exclusive OR of the outputs belonging to group 1 is 2. can be expressed as y=G−■ (4). Therefore, the two layers can be easily expressed in the 1eed-Mul Ier standard form by finding G from 8. When circuit N is normal, that is, equation (4) holds, for any function of Xo, xl, ... + Xn-1,
Pi f1 = h (i = 0.1.-2 L-1
) −=xO+Xl+”’ that satisfies (5)
There exists a function fi (0≦i≦t-1) of r Xn-1. In other words, it suffices to write fish■(G-1)1, and
=(...fl...)T,F'' (Fij)tX2
n, in the standard form of 1e6d -MLI I Ier,
If we express it as tributary = IF'-pull, we can find F from the equation. Here, Hoj is h=
H・u and) (, eed −MLI I Ier IH when expressed in standard form = (Hoj ) IX2n (7)
Element Theal.

Therefore, the outputs of zi”'i■f, (Q≦1≦
When the circuit N is normal, the test circuit configured according to
0) or (11...1), but if less than t-1 fl(2 errors occur, (zO+zl+...Zt
-1) becomes an output other than (00...0) or (11...1), and an error can be detected.

Also, in the case of t=,2, CO=fo■fO,CI ”
” '11 The layer path is the same as the test circuit by Zi (2. If circuit N is normal, (CoC1) - (01) or (1
0), and if an error occurs in (t-1,) of 21, the error will be (CoC1)-(00)i or (11), and the error can be detected.

The test circuit 3 that outputs (CoC1) in FIG. 2 is a test circuit that outputs Zi (it has an additional self-testing equivalency test circuit 4, and is used to detect failures in the test circuit itself).
It is sufficient to examine the test circuit that outputs zl.

Next, we will discuss the detection of failures in the test circuit itself.

The test circuit that outputs Zi is constituted by exclusive OR of a circuit 5 that generates 71 and a circuit 6 that generates fl, as shown in FIG. 3, for each 21. xo in equation (5).

If the function of xl, ... + If there is a hekabatan (XO+ + ”' + A circuit that causes an error in fl because it functions only for Xn-1 6
There are input buttons for detecting failures, and these failures can be detected by inputting such a button, inverting fl and inverting the output Zi.

If the circuit N does not include meaningless outputs such as constants, and the circuit N is normal, the input (xO+Xl+...).

Xn-1) can be divided into groups such that 21 takes logical values "0" and "1". In addition, each exclusive OR gate constituting 2 can be configured so that it does not take a fixed value when the circuit N is normal. For example, 2.-y1■y2
■y3■y4, if circuit N is normal, y1■y2■
Assuming that y3 * y4N (constant), y1 * y2 * y3 = 0, the exclusive OR gate 306 of the circuit that generates 2□ in FIG. 4 takes a fixed value "0", but the If configured like this, there will be no gate that takes a fixed value.

Therefore, the test circuit configured as described above (2) has a self-testing property that can detect a failure in the gate forming the test circuit while the circuit N is in a normal state.

Typically, an exclusive OR consists of several gates as shown in FIGS. 6 to 9. In this configuration, a single stuck-at fault in an internal gate cannot result in a stuck-at fault in the input or output of the exclusive-OR gate.

Therefore, in order to detect a failure in an exclusive OR gate, it is necessary not only to input a pattern in which the input and output are inverted, but also to input a pattern corresponding to the circuit configuration. For example, in the circuit configuration shown in FIG. 6, (01) (10) (11
), and in the circuit configuration shown in Figure 7, a total of three input buttons (00), (11), and either (01) or (10) are required. . ! Ta,
The circuit configuration shown in FIG. 8 requires input buttons (01), (10), and (11), and the circuit configuration shown in FIG. 9 requires input buttons (01), (10, and 00).

(2) For each exclusive OR gate that makes up the test circuit, select a circuit configuration that can detect stuck-at faults in the internal gates when circuit N is normal, and configure the test circuit. For example, this test circuit has a self-testing property that allows it to test for stuck-at faults in all gates constituting this test circuit while the circuit N is in a normal state.

Next, as an embodiment of the present invention, let us consider a case where a four-manpower priority control circuit (inspection circuit for two) is configured. Fig. 10 shows a four-manpower priority control circuit, and the following No. 3
It is expressed by two logical expressions.

yO-XO" (X1X2 ・X3)yl -Otsu・
Stone・(x2X3) ・・・・・・(7)Y2
= XOV XI V X2 V

Let us take as an example a case where there are three groups, that is, t'=3. At this time, f/ and G in equation (4) are the same as y and LA, respectively. XolXIIx2・Sheath function l] can be arbitrary (-, but as follows (-), the number of exclusive ORs that constitute the test circuit can be reduced.

The weight of the element in each column of the matrix G (each column (-),
If the number of elements of 1) is a town, then old - (■1oρI
2n is obtained as follows, and function 11 is determined by setting b = H-, u. From this, in the four-manpower priority control circuit (-, l(, h becomes (-).

fl(= (001] 111. ] ], 1.1.
11], ], 1)h-old・[=X]・X2・
X3 From equation (6), the 3×16 matrix ``is determined as follows.

Therefore, the test logic representing the test circuit is as follows.2 FIG. 11 shows the test circuit for the four-person priority control circuit constructed by equation (9). In the inspection circuit in Figure 11, the four-man power priority control circuit in Figure 0 is normal.
If there is no failure in the test circuit itself, Do+z1.1Z2
) outputs (ooo)4 or (], 11.,).

A malfunction occurred in the gate of the four-person priority control circuit.

is inverted, the output z of the test circuit in FIG.

Invert. Therefore, the test circuit output (z(]+zl
+22) is different from the normal case ( ], OO) or (011,), and an error can be detected. In addition, the test circuit itself (if a fault occurs, the test circuit output (Zo,
There is an input of (XO+Xl +X2.x3) such that zl, z2) is outside (000)(111,)11. For example, the "1" stuck-at fault in game 1-4.04 is (
When xO+Xl 1 x21 If there is no failure during this manual operation, (z
o, zl, z2)-(000). Therefore, the test circuit shown in FIG. 11 is a self-testing test circuit for a four-person priority control circuit. Furthermore, in order to guarantee self-checking performance for the gates forming the exclusive OR gate, 311, 312, . . . in FIG. (7) From the formula, y2 cannot be the logical value "0". In other words, game) 31
．． The input of 1 (XO+3'2) is (oo) (01) (
Only patterns 11,) can be set. therefore,
If the gate 311 is configured with the circuit shown in FIG.
1 can also be detected.

In this way, the exclusive OR game of FIG. 11) 311. .

3], 2, and 313 in Figures 7, 9, and 9, respectively.
When configured with the circuit shown in the figure, the test circuit shown in FIG. 11 becomes a test circuit for a four-man power prioritized horizontal control circuit having a self-testing property capable of detecting all single stuck-at faults.

Next, an embodiment of another test circuit for the four-man power priority horizontal control circuit shown in FIG. 10 will be described. Here, consider an example in which the output is divided into two groups, (yo) and (yl + Y2). (4) Equation? and σi are expressed as follows. □ IH= (001,1,000000000000),
+1-B, XI・From equation (6), the 2×16 matrix ``is determined as follows.

The test logic representing the test circuit that outputs (Co C1) is as follows.

FIG. 12 is a test circuit for a four-man power priority horizontal control circuit constructed from (1) (2). As in the case of the test circuit in FIG. 11, from the input button of the exclusive OR gate,
If the exclusive OR gates 314, 315, and 316 are configured with the circuits shown in FIGS.
Figure 2 shows a test circuit that has self-testing properties that can detect all single stuck-at faults within itself.

As explained below, the test circuit of the present invention uses R,eed -Mul
Expressed in ler expansion form, and from the relationship of this common term, function 11
Since the test circuit is constructed by calculating the test logic and deriving the test logic, there is an advantage that a test circuit for a multi-output combinational circuit can be constructed systematically. Furthermore, since the present test circuit has self-testing properties, it has the advantage of being able to detect not only errors in the target circuit but also failures in the test circuit itself. Additionally, if a test circuit is provided within the LSI, GO/NOGO tests during manufacturing can be performed by simply inputting an arbitrary input button and checking the output of the test circuit at that time, which is effective in simplifying testing. .

As described above, the present invention can be applied to random logic such as control system logic where there is no effective test circuit and testing is not often performed, and has a great effect on increasing the reliability of logic circuits.

[Brief explanation of the drawing]

1 and 2 are diagrams showing an outline of a test using the test circuit of the present invention, FIG. 3 is a diagram showing an example of the circuit configuration for generating the test output Zi, and FIGS. Figures 6 to 9 are diagrams showing circuit configuration examples of exclusive OR gates, Figure 10 is a diagram showing a four-man power priority horizontal control circuit, Figure 11 is FIG. 12 is a diagram showing an embodiment of the inspection circuit of the present invention for a four-manpower priority horizontal control circuit. DESCRIPTION OF SYMBOLS 1... Combinational circuit, 2... Testing circuit that outputs 21, 3... Testing circuit that outputs co'l c], 4... Self-testing equivalence testing circuit, 5...・2
A circuit that generates 1, a circuit that generates 6...fi,
101-106...A, ND gate, 20
1~209...NOR gate, 301~316・
...Exclusive OR gate, 401-406...Inversion gate, 501-505...OR gate, 601
~605...NAND gate. Agent Patent Attorney Name Tree Castle Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1. n inputs XO+ xl + "' t xn-
1 and r outputs (r≧2) y6, yl,...
A circuit for testing the normality of a multi-output combinational circuit having Yr-1, the circuit tests the output of the multi-output combinational circuit by t (2
Divide into groups ≦t≦r, and group 1 (i=
Q. 1.2. ..., t-1) is set as 11, and xO+Xl+"'+"n
−1 is the function h, and if the multi-output combinational circuit is normal, 7o ■ fo: r1 ■ f1 = “”” = ?t
-1 ■ ft-1 = h (■: exclusive OR) is always (2) selected above
When the function of Xn-1 is f, the output at t1 is Zi
""i■f, (0≦i≦t-1) logical expression (a test circuit characterized by being configured by two twists. 2. Advice to the test circuit according to claim 1) , from its output Z1 (0≦1≦, lt21), S=-1, V, ZI, t =, A:.Zi (V: logical sum, △
: logical product), then two signals (t, s), (t, s
), (1, τ), or (t, s). 3. n inputs XO + ``1 + ''' + Xn
-] and r1 fixed (r≧2) output yo, y], ...,
A circuit for testing the normality of a multi-output combinational circuit with Yr-1, which divides the output of the multi-output combinational circuit into two groups, and each output belonging to group 1 (t=Q, l). Exclusive OR of 7. inputs Xo, X1 . ... + Let h be the function of xn-1, and when the multi-output combinational circuit is normal, fQ(+)f(1
-fl ■ The above XO+ selected so that f1=h holds true
Xl +,, ”' +, X(function − of 1-1 as fo,
When fl is set, the two outputs are co-vo fO, C1
A test path, characterized in that it is constructed according to the logical formula =41 f1. 1 TLi, 4 The outputs of all the exclusive OR gates that generate the function h, the function 2, (0≦1≦t-1), and Pi are the XO+ xl +...+ Xrl-1 3. The test circuit according to claim 1, 2, or 3, wherein the test circuit is configured such that the value does not become a fixed value. 5. All exclusive OR gates constituting the test circuit have two inputs (a, b) as (0, 0).
, (0,1), (1,0), and (1°1), only those that can be set by the above XO + Xl + "' + Xn-1 constitute the exclusive OR gate. Item 1, item 2, item 3, or item 4 of the claim is characterized in that the invention is constructed using a circuit that can detect a single stuck-at fault in a gate using the output of the exclusive OR gate. Test circuit described.