JPS5947654A - Microprogram controller - Google Patents

Abstract

PURPOSE:To simplify a means for generation of the parity signal and to reduce undesired microinstructions, by inverting a parity bit when a set or reset instruction is executed for each bit of a main register. CONSTITUTION:When a power supply is applied to a microprogram controller, an output signal line 106 of an initializing circuit 7 is set in a state 1 for a specified time. The bits 0-7 of a main register 5 are reset, and at the same time a bit P is set in the state 1. While the inverted initializing signal suppresses the output of an instruction decoder 2 from energization and also suppresses the energization of the output of an AND circuit 21 until the register 5 is set in an initialization state. As a result, the odd parity condition is not satisfied and a parity error is detected in case a microinstruction having a reset function is stored to a register 1 despite of the bit 0 of the register 5 is set in a state 0.

Description

DETAILED DESCRIPTION OF THE INVENTION (Description of the technical field to which the invention pertains) The present invention relates to a microprogram control device, particularly a microprogram control device σ, in which bl and n are set in bit units.
Concerning generation and checking of parity bits of registers to be reset.

(Description of Prior Art) Conventionally, in order to check the normality of registers that are set, reset, or reset bit by bit in a microprogram control device, two registers, a primary register and a secondary register, are provided, and a set command, This is done by checking the coincidence of each bit in both registers every time a straddle reset instruction is executed. It is unreasonable that an error will not occur even if a microinstruction is executed to set the bit to +1 again. Therefore, this has the disadvantage that extra microinstructions are executed.

(Detailed Description of the Invention) An object of the present invention is to provide a simple parity generation circuit and check circuit for a register that can eliminate such defects and Q, and can be set or reset bit by bit. An object of the present invention is to provide a microprogram control device in which unnecessary microinstructions are reduced.

(Description of structure and operation of the invention) The microprogram control device according to the present invention consists of a microinstruction register, a microinstruction decoder, a set decoder, a reset decoder, a main register, a first type 016 circuit, and an exclusive The circuit includes a logical OR circuit, a first inverter circuit, a parity check circuit, an initialization circuit, a plurality of second type OR circuits, a second inverter circuit, and an AND circuit. .

The microinstruction register is a register circuit that holds microinstructions for setting, reading, or resetting information bit by bit. A microinstruction decoder is a circuit for decoding whether a microinstruction is a set instruction or a reset instruction. A set decoder is a circuit for determining the bit position targeted for execution of a set instruction.
The reset decoder is a circuit for determining the bit position targeted for execution of the reset instruction. The main register can be set or reset by a set decoder and a reset decoder, and has a plurality of set/reset flip-flop means corresponding to each of a plurality of information bits and one parity bit. It is constructed with the following features.

The first type of OR circuit is a selection circuit for selecting the decoding output of the set instruction or the decoding output of the reset instruction of the microinstruction decoder. The exclusive OR circuit is a circuit that combines the output of the 011 circuit and the output of the parity bit of the main register into a logic tree of 111t + 1 and outputs the output into the set input of the parity bit of the main register. The first inverter circuit is a circuit for inverting the output of the exclusive OR circuit and adding it to the reset input of the parity bit of the main register. The parity check circuit is a circuit for determining whether the sum total of the outputs of the information bits of the main register and the parity bits is a 1M numerical value. The initialization circuit is a block circuit that resets and initializes all the information bits and parity bits of the main register. The second (7) type of OR circuit resets each bit by adding the output of the initialization circuit or the output of the reset decoder to each bit of the main register. This is a circuit for making it 1irffD. The second inverter circuit is a circuit for preventing the output of the instruction decoder from being activated during the operation period of the initialization circuit. The AND circuit is a circuit for preventing the output of the parity check circuit from being activated by the output of the second inverter circuit during operation 11 of the initialization circuit.

(Detailed Description of the Invention) Next, the present invention will be described in detail with reference to the drawings. A block diagram of an embodiment of a microprogram control device according to the present invention is shown in FIG.

In FIG. 1, the microprogram control device includes a microinstruction register 1, a microinstruction decoder 2, a set decoder 3, a reset decoder 4, and a main register 5.
, the first type of Q1(, the circuit 8, the exclusive OR circuit 9, the first inverter circuit 1(), the parity check circuit 6, the initialization circuit 7, and the second type of The circuit includes first to ninth OR circuits 11 to 19, a second inverter circuit 20, and an AND circuit 2].

Information indicating the instruction type of the microinstruction stored in the microinstruction register 1 is applied to the instruction decoder 2 through an output signal line 101. Information for specifying bits to be set or reset in the main register 5 is transmitted to the set decoder 3 through the output signal line ]()2. It is added to the hexagram and reset decoder 4. The signal on the output signal @103 of instruction decoder 2 goes to state 1 when the instruction type is set, and the output signal +! I!
xo3 is connected to the enable input E of the set decoder 3 and the first type of OR circuit 8. Output signal line 10
The signal above 4 is in state l when the instruction type is reset.
Otherwise, the output signal line 104 is connected to the enable input E of the reset decoder 4 and the first type OB circuit 8. The output signal line 121 of the set decoder 3 is connected to the set input terminal of bit 0 of the main register 5, which is set or reset bit by bit. Similarly, output signal line 122 is bit l.

The output signal line 123 is bit 2, the output signal line 124 is bit 3, and the output signal line 125 is bit 4. Output signal line 12
6 is bit 5. Output signal line 127 has bit 6, output (4
The output signal line 131 of the reset decoder 4 is connected to the set input terminal of bit 7 through the first 0 circuit of the second type.
Connected to the reset input terminal of bit 0 of register 5. Similarly, the second type of output signal line 1321d
bit 1 through the OR circuit 12, output signal N] 33 is the third on of the second type, bit 2 through the circuit 13
, the output signal line 134 is connected to the fourth OR circuit 1 of the second type.
4 to jfi, bit 3, output signal line 135 is the fifth OI of the second type (, bit 4 through circuit 15, bit 6 through OR circuit 17 of output signal 7, output signal line 138
are respectively connected to the reset input terminal of bit 7 through the second type of eighth OR circuit 1B. ','4
The output signal line 105 of the OR circuit 8 of type S1 is connected to the exclusive OR circuit 9, and the output signal line 129 of this circuit
is connected to the set input terminal of the parity bit of the main register 5 by stacking the ninth OR circuit 619 of the second type, and is also connected to the first inverter circuit IO. The output signal line 149 of the first inverter circuit 10 is connected to the reset input terminal of the parity bit of the main register 5. Signal line 15 for output of each bit of main register 5
1 to 159 are each connected to the parity check circuit 6, and the output signal line 1()8 of the parity check circuit 6 is connected to the AND circuit 21. The parity bit output signal line 159 of the main register 5 is also connected to the exclusive OR circuit 9. The output signal line 106 of the initialization circuit 7 is connected to the first to ninth OR circuits 11-1 of the second type.
9 and the second inverter circuit 2a), and the output signal 4Ii! of the second inverter circuit 20 is connected to the second inverter circuit 2a). 107 is connected to the instruction decoder 2 and the AND circuit 21.

Next, the circuit operation will be explained in detail. When the power of the microprogram device is turned on, the state of the output signal line 106 of the initialization circuit 7 remains in state 1 for a certain period of time, and the main register is output through the first to eighth O-circuits 11 to 18 of the second type. bits 0 to 7 of the main register 5 are reset, and the parity bit of the main register 5 is set to state l through the first type of OR circuit 19. Further, the initialization signal inverted by the inverter circuit 20 of @2 prevents the output of the instruction decoder 2 from being activated, and also causes the main register 5 to be in the initial state, that is, bits 0 to 7.
The output of the AND circuit 21 is inhibited from being activated until the state of the AND circuit 21 is O and the state of the parity bit becomes 1.

Next, the operation when a microinstruction for setting bit 0 of register 5 to state Ml is stored in microinstruction register 1 will be described. At this time, the state of the output signal line 1()3 of the instruction decoder 2 becomes 1, and the set decoder 3 becomes operable.

Output signal line 1 of microinstruction register 1 (]
Z contains the content to specify bit 0,
With this information, the state of the output signal line 121 of the set decoder 3 becomes 1, and the state of bit 0 of the register 5 is set to 1. In this case, the output signal lines 122-128 of the set decoder 3 are not activated, so the states of bits 1-7 remain 0.

On the other hand, the parity bit works as follows. That is, the state of the output signal line 103 of the instruction decoder 2 becomes 1, so that the state of the output signal line [C)5 of the first type of OR circuit 8 becomes 1]. Since the state of the output signal line 159 from the parity bit of main 1/register 5 is 1 before the instruction is executed, the output signal line from the exclusive OR circuit 9]
The state of 29 is 0. Therefore, the set input of the parity bit of the main register 5 is not activated, but since the state of the output signal line 149 of the first inverter circuit 10 is 1, the reset input of the parity bit is not activated. , the state of the output signal line 159 of the parity bit is reset from 1 to ().

Next, the operation when bit ( ) of main register 5 is reset will be explained. At this time, lk_ftM of the output signal @104 of the instruction decoder 2 is not 1, and the reset decoder 4 is enabled to operate. Further, the output signal line 102 of the micro life register 1 includes the content μ that specifies the bit (), and the output signal of the reset decoder 4 -P! 4
The state of 1131 becomes 1 and the main register 50 bit 0 is reset. Output signal line 11 of reset decoder 4
32 to 138 are divided into rX, and bits 1 to 7 are 0.
Noma1. Since the state of the output signal line 1L)4 of the instruction decoder 2 becomes 1, the state of the output signal line xo5 of the first type of zero circuit 8 becomes 1.

At this time, the state of the output signal line 159 from the parity bit of the main register 5 is (), so the state of the output signal line 129 of the exclusive OR circuit 9 becomes 1, and the parity bit of the main register 5 The set input becomes 1. Also the first
Inverter circuit] The state of the output signal line z4q of () is O
Then, the state of the reset input of the parity bit of register 5 becomes 0 and ζ. Above is the state of the parity bit of main register 5! 1 is set to l.

Next, even though the state of bit 0 of main register 5 is 0, a microinstruction with a reset function≠
The operation when stored in the second microinstruction register L will be explained below. At this time, the reset input for the main register 50-bit OVC is activated as described above, so it remains at 0. On the other hand, the parity bit operates as follows.Since the state 104 of the output signal line of the instruction decoder 2 becomes 1, the state of the first type 0) 1 and the output signal line 1()5 of the circuit 8 becomes 1. becomes 1. At this time,
Output signal line 159 from parity bit of main register 5
Since the state of is 1, the state of the output signal line ]29 of the exclusive OR circuit 9 becomes (). Therefore, main register 5
The state of the set input of the parity bit becomes 0, the state of the reset input becomes 1, and the state of the output signal line 159 from the parity bit becomes (). Therefore, in this case, since the odd parity condition of the main register 5 is not satisfied, the output of the parity check circuit 6 is activated and the AN
The state of the output signal line 1()9 of the D circuit 21 becomes 1, and a parity error is detected.

(Detailed Description of the Invention) As explained above, the present invention includes bits of the main register.
By inverting the parity bit when executing a 1σ set command or reset command, the means for generating a parity signal can be simplified and unnecessary microinstructions can be reduced. There is an effect called.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a microprogram control device according to the present invention. l...Micro instruction register 2...Instruction decoder 3...Set decoder 4...
Reset decoder 5... Main register 6... Parity check circuit 7... Initialization circuit 8, l] ~ 19... 0T (1 circuit 9... Exclusive OR circuit) (1, 211...・Inverter circuit 21...AN
D circuit 1 (11-109, 121-139, 141-
149.15] ~ 159...Signal line

Claims (1)

[Claims] a microinstruction register for holding a microinstruction for setting or resetting information for each hit; a microinstruction decoder for decoding whether the microinstruction is a set instruction or a reset instruction; and a target for executing the set instruction. a set decoder for determining a pit position to be executed; a reset decoder for determining a bit position to be executed by the reset instruction; , and a plurality of t#
A plurality of set/reset flip-flop means corresponding to each bit of the information pit and one parity bit are provided.
and a first type of Or? for selecting the decoded output of the set instruction or the decoded output of the reset instruction of the microinstruction decoder. a circuit, and the first
f, 4 ii) OJ(, Exclusive OR of the output of the circuit and the output of the ! 1) an inverter for inverting the output of the circuit and adding it to the reset input of the parity bit of the main register; a parity check circuit for determining whether a single sum of the outputs of the information bits and the parity bits of the main register is an even value; an initialization circuit for resetting and initializing all bits, and an output of either the initialization circuit or the reset decoder is added to each bit of the main register to reset each bit. a second class 11II plurality of OR circuits for enabling the operation of the instruction decoder; and an AND circuit for preventing the output of the parity check circuit from being activated by the output of the second inverter circuit during the operation period of the initialization circuit.
(It, a microprogram control device.