JPH02132524A - Information processor - Google Patents

Abstract

PURPOSE:To realize the optional and proper change of the combination of instructions that can be carried out in parallel with each other by using a deciding means consisting of an instruction combination detecting means and a memory means which is capable of proper writing jobs and decides whether the combinations of instructions can be carried out in parallel with each other or not. CONSTITUTION:A parallel executing combination deciding circuit 1 contains an instruction group decoder, an instruction combination grant latch, an AND circuit, an OR circuit. The contents of instruction registers 41 and 42 are inputted to the circuit 1 via the signal lines 941 and 942. The circuit 1 decides whether two instructions can be carried out in parallel with each other or not and sends this deciding result to a 2nd arithmetic unit 72 and an instruction reading circuit 3 via a signal line 91. When the deciding result is affirmative, the unit 72 performs the arithmetic operations of subsequent instructions. While the unit 72 does not work in case the deciding result is negative. Thus it is possible to optionally and properly change the combination of instructions that can be carried out in parallel with each other by writing the appropriate value into the contents of the instruction combination grant latch.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an information processing device that executes multiple instructions simultaneously and in parallel to improve processing speed. [Prior Art] Conventional large-scale general-purpose computers effectively increase the execution speed of a sequence of instructions by executing each instruction in a pipeline manner and executing different instructions in an overlapping manner. In an attempt to further improve this, a device has been proposed that has multiple resource means and executes multiple conceptually consecutive instructions simultaneously and in parallel. In this device, the combination of instructions that can be executed in parallel is fixed, and changing this combination requires major changes to the hardware6. For example, JP-A-58-176751, JP-A-59-22777
No. 5, JP-A-63-12029, etc. [Problem to be Solved by the Invention] In the above-mentioned conventional technology, the combination of instructions that can be executed in parallel is fixed, and when a failure occurs in some of the plurality of resource means, instructions that require the resource cannot be exchanged with each other. It was not possible to prevent only the parallel execution of combinations.
As a result, even when a failure occurs in a part of the resource means, it is necessary to suppress parallel execution of all combinations of instructions. Furthermore, it is necessary to fix the combination of parallel executable instructions before designing the device, and there is a problem in that it is not possible to respond flexibly to design changes.

It is an object of the present invention to make it possible to arbitrarily change the combination of instructions that can be executed in parallel when a plurality of instructions are executed in parallel, and to make it possible to change the combination of instructions that can be executed in parallel at any time. An object of the present invention is to provide an information processing device that can prohibit only the combination of parallel execution of instructions.

[Means to solve the problem]

The purpose of making it possible to change the combination of instructions that can be executed in parallel at any time is to use an instruction combination detection means that detects combinations of instructions, and a writable storage means that allows the combination to be executed in parallel. This is achieved by providing a determination means that consists of: The purpose of prohibiting only parallel execution combinations of instructions that require the resource means when a failure occurs in a part of the resource means is to have a fault occurrence detection means for each resource means and if the detection result is positive. This is sometimes achieved by providing a means for resetting the combination of instructions that can be executed in parallel by writing to the memory means that can be written at any time corresponding to the combination of instructions that use the resource means. [Operation] A combination of two instructions is detected by the instruction combination detection means. Whether or not to permit parallel execution of this combination is stored in advance in the above-mentioned writable storage means. Parallel execution is permitted only when both the contents of the storage means and the corresponding instruction combination detection result are positive. This allows the combination of instructions that can be executed in parallel to be changed at any time by writing an appropriate value to the contents of the storage means. Further, when the detection result of the failure occurrence detection means provided for each of the plurality of resource means is implicit, the means for resetting the combination of instructions mentioned above corresponds to the combination of instructions requiring the resource means. A value indicating negation is written to the writable storage means at any time. By doing this,
Even when a failure occurs in some of the plurality of resource means, parallel execution can be restricted to the relevant combination of instructions. This makes it possible to suppress a decrease in performance compared to the case where all parallel execution is suppressed when a partial failure occurs.

〔Example〕

A first embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 4.

FIG. 4 shows an example of the overall configuration of an information processing device using the present invention. This information processing device uses the contents stored in the main memory 23 as a command word in the buffer memory 2o.
an instruction reading circuit 3 which reads out two consecutively via the instruction register 4 and supplies the conceptually preceding one to the instruction register 41 and the subsequent one to the instruction register 42;
Decode the contents of 1 and 42 to obtain the general register number,
Instruction degoders 51 and 52 that obtain memory operand addresses, etc. and issue operation instructions to the arithmetic units, a general-purpose register group 6, buffer memories 21 and 22 for memory operands, and for executing preceding instructions capable of performing all types of defined operations. a first arithmetic unit 71, a second arithmetic unit for executing subsequent instructions capable of some types of operations and whose logical scale is smaller than the first arithmetic unit, and a second arithmetic unit 71 during decoding;
The parallel execution combination determination circuit 1 determines whether or not two instructions can be executed simultaneously.

The contents of main memory 23 are temporarily stored in buffer memories 20, 21 and 22. The instruction word is buffer memory 2
Two commands are successively taken into the command reading circuit 3 from the command line 920 from the command line 920 from the command line 920. The instruction reading circuit 3 inputs one leading one of the two instruction words into the instruction register 41 and the other following one into the instruction register 42. These two instruction words are decoded by the instruction decoders 51 and 52, and necessary operand data is read out from the puffer memories 21 and 22 and the general-purpose register group 6 according to the respective instructions of the instruction decoders, and the first arithmetic unit 71 and The data is taken into the second arithmetic unit 72. In the first arithmetic unit 71, a predetermined arithmetic operation is executed for the preceding instruction.

On the other hand, the contents of the instruction registers 41 and 42 are transmitted to the parallel execution combination determination circuit 1 through signal lines 941 and 942.
is input to. The determination circuit determines whether or not the two input instructions can be executed in parallel, and sends the result to the second arithmetic unit 72 and the instruction reading circuit 3 via the signal line 91. The arithmetic unit executes an arithmetic operation on a subsequent instruction only when the determination result is positive. When the decision result is negative, the second arithmetic unit 72 does not operate, and therefore only the conceptually preceding instruction is executed. The configuration of the second arithmetic unit 72 is
As shown in the figure. Signal 415 output from instruction decoder 52
20 is a signal 5 indicating the type of operation in the arithmetic unit 7200;
201 and a signal 5202 indicating the validity of the operation.

In the arithmetic unit 7200, the signal lines 60, 210, 220
An output signal 7201 is generated by performing an operation specified by a signal line 5201 on input data. On the other hand, the signal line 7202 indicating the validity of output data is the signal line 52
It is generated by ANDing 02 and 91. In other words, the operation is deemed to be valid based on the decoding result of the instruction,
Further, the output data of the arithmetic unit 7200 is valid only when the output of the parallel execution combination determination circuit 1 is positive and it is determined that the parallel operation with the first arithmetic unit 71 is valid.

The signal line 7202 is used as a write permission signal for the output data 7201. On the other hand, if the output of the parallel execution combination determination circuit 1 is negative, the AND gate 7210 inhibits the operation of the second operation unit 72. It turns out. The subsequent instruction that was not executed at this time is read out again as the next preceding instruction by the instruction reading circuit 3 that received the determination result, and is executed.

The arithmetic results executed by the one or two arithmetic units are written to predetermined locations in the buffer memories 20, 21, and 22 and the general-purpose register group 6 according to the instruction specifications. In this way, one or two commands are sent one after another.
It is executed one by one.

FIG. 1 shows an example of the configuration of the parallel execution combination determination circuit 1. Instruction group decoders 101 and 102 decode which arithmetic units are used by instructions, and the decoders are arranged in a matrix, and a 1 bit is placed on each intersection point to indicate whether instructions can be executed in parallel. instruction combination permission latches 111, 11 consisting of flip-flops;
2, 113, and 114, an AND circuit 121, 1 that takes the logical product of the output of the decoder and the output of the permission latch;
22, 123, and 124, and an OR circuit 131 that takes the logical sum of the outputs of the four AND circuits. Further, the output signal lines 191 and 291 of the decoder correspond to the fact that an instruction can be executed by either the first arithmetic unit or the second arithmetic unit, and the output signal line 19
2 and 292 correspond to the fact that the instruction can only be executed in the first arithmetic unit. To simplify the following explanation, FIG. 2 is a table showing a one-to-one correspondence between the output of the instruction group decoder and the contents stored in the instruction combination permission latch. In this embodiment, the instruction combination permission latch 11
1, 112, and 113, and “1” to 114.
Write 0 71. In FIG. 2, the values shown in brackets are the values written to the latch assumed in this embodiment.

it 1 pt corresponds to that the corresponding combination of instructions can be executed in parallel, and "0" corresponds to that it cannot be executed in parallel. Note that this writing uses a conventional flip-flop scan-in technique, although not particularly shown. Conventionally, all flip-flops constituting a computer have always had scan-in/scan-out logic built in, and the above writing can be easily realized using conventional technology. FIG. 11 shows the structure of the instruction reading circuit 3.

The instruction string read from the buffer memory 20 is the signal line 9.
It is input via 20. The preceding instruction is extracted by the instruction extraction circuit 30o1 and set in the instruction register 41 via the signal line 941.

Further, a subsequent instruction is extracted by the instruction extraction circuit 3002 and set in the instruction register 42 via the signal line 942.

When two instructions are executed in parallel, the instruction extraction circuit 3001 for the next instruction following the previously executed preceding instruction and subsequent instruction extracts the instruction as the preceding instruction to be decoded next. On the other hand, if only the preceding instruction is executed and the subsequent instruction is not executed, the subsequent instruction that was not executed is extracted as the preceding instruction to be decoded next. The control circuit 350 performs this control. When the signal line 91 becomes positive indicating that parallel instruction execution has been performed, the instruction extraction circuit 300 increases the instruction extraction pointer for 1 by the sum of the instruction lengths of the preceding and succeeding instructions. When the signal line 91 becomes negative, the instruction extraction pointer for the instruction extraction circuit 3001 is increased by the instruction length of the preceding instruction. The instruction return pointer for the instruction extraction circuit 3002 is controlled so that the instruction following the instruction to be extracted by the instruction extraction circuit 3001 is always extracted. The instruction lengths of the executed preceding and subsequent instructions are input to the control circuit 350 through signal lines 301 and 302, respectively, and each pointer is controlled through the signal line 351.
, 352. In this way, the signal line 92
If the instruction is negative, re-reading of the subsequent instruction is controlled and execution becomes possible.

Details of the instruction extraction circuits 3001 and 3002 are omitted here. Please refer to Japanese Patent Application Laid-Open No. 58-176751.

Signal lines 941 and 9 from instruction registers 41 and 42
Instruction words input via 42 are decoded by instruction group decoders 101 and 102. The decoding result corresponds to the arithmetic unit used by the instruction, and the decoding result corresponds to one of the signal lines 191 and 192 and the signal line 291.
and 292 is always 14 1 IT, and the other is always "0". If the output signal lines of the two instruction group decoders corresponding to the two instructions are arranged in a matrix, only one of the four intersection points will be "1". This point uniquely corresponds to the combination of the two instructions. As an example, assume that one of two instructions that precedes the instruction can also be executed by the second arithmetic unit, and the other instruction that follows is an instruction that can be executed only by the first arithmetic unit.

At this time, II I TJ is connected to signal lines 191 and 292.
are output, and both become "1" at the intersection corresponding to the instruction combination permission latch 112. At this time, all three inputs of the AND circuit 122 become 11 1 II, and It i 1
1 is output. This output becomes an input to the OR circuit 131, which outputs "'1". This output is transmitted via the signal line 91 to the second ? It is input to the gi calculation unit 72 and the instruction reading circuit 3. Here, ll I I+ corresponds to the fact that the determination result is implicit, and as mentioned above, the first arithmetic unit and the second arithmetic unit operate simultaneously,
The two instructions are executed in parallel.

However, when both instructions can be executed only in the first arithmetic unit, signal lines 192 and 292 are
The contents of the instruction combination enable latch 114 corresponding to this intersection, where / 1 tt is asserted, is 11 0 tp.

At this time, the output of the AND circuit 124 becomes it O t+. In addition, the other three AND circuits 121 and 12 at this time
The outputs of 2 and 123 are both 11 0 M, and the output 91 of the resultant ORB path 131 is also u O pp. Therefore, the second arithmetic unit does not operate, and only the preceding instruction is executed.

Assume that in the information processing apparatus described above, a design change occurs during the design process, and the second arithmetic unit 72 is able to have exactly the same function as the first arithmetic unit 71. Since information processing devices are usually designed in multiple groups, there is a high possibility that such a situation will occur. At this time, by simply storing a 1 17 in the instruction combination permission latch 114, all instruction combinations can be executed in parallel.

Note that this embodiment assumes an instruction specification in which the operands of an instruction are placed in general-purpose registers and memory, as in the HITAC M series computer manufactured by Hitachi, Ltd. Examples of the instruction corresponding to the first arithmetic unit include a multiplication instruction M, and the instruction corresponding to the second arithmetic unit is an addition instruction A. For the instruction specifications of M series computers, please refer to the [M series processing unit] manual.

According to this embodiment, in an information processing device that selectively executes a specific combination of instructions in parallel, when a previously assumed combination of instructions is changed at the design stage or when specifications are changed after product shipment, hardware It is possible to change the combination of instructions that can be executed in parallel without making changes, which is effective in shortening product development time and making it easier to expand functionality after shipping. In addition, when the information processing device stops in an abnormal state and it is determined that the cause is a malfunction of multiple resource means provided for parallel execution, a scan is performed on the instruction combination permission latch mentioned above. By manually resetting the combination of instructions that can be executed in parallel using technology and prohibiting the parallel execution of instructions that use the resource means, the entire device can be saved until the resource means recovers from a failure. This has the advantage that it can be operated without stopping.

A second embodiment of the present invention will be described using the first embodiment and FIGS. 3, 5, 6, and 7.

FIG. 5 shows an example of the overall configuration of an information processing device using the present invention. The present information processing apparatus adds failure detection circuits 81 and 82 to the information processing apparatus according to the first embodiment, respectively, for detecting when a failure occurs in the functions of the buffer memories 21 and 22 and they become unusable. A failure occurs in which both the first arithmetic unit and the second arithmetic unit are replaced with arithmetic units 73 and 74 capable of performing all types of arithmetic operations, and each detects that a failure has occurred in the function of the arithmetic unit and it has become unusable. Detection circuits 83 and 84, the four failure detection circuits 81, 82, 83
, and the instruction combination permission latch 111 of the parallel execution combination determination circuit 1 based on the combination of the detection results.
, 112, 113, and 114, and the arithmetic unit 74 executes a conceptually preceding instruction corresponding to the instruction register 41, or executes a subsequent instruction corresponding to the instruction register 42. a parallel combination reconfiguration circuit 8 which sends a selection condition to a selector 89 that selects a combination, and further sends an operation instruction signal to the calculation unit 74 and an operation prohibition signal to the calculation unit 73 when a failure occurs in the calculation unit 73; an OR circuit 891 that inputs the logical sum of the judgment result of the judgment circuit 1 and the operation instruction signal from the reconfiguration circuit to the calculation unit 74;
It has a configuration with the addition of. Further, the parallel execution combination determination circuit 1 has been modified as shown in FIG. 7, which will be described later. In this embodiment, the instruction combination permission latch 11
1, 112, 113, and 114, values shown in FIG. 3 (during normal operation), which will be described later, are stored in advance by scan-in.

FIG. 7 shows the configuration of the parallel execution combination determination circuit in this embodiment. This configuration is in addition to the first embodiment described above. A signal line 901 is added for writing from the parallel execution combination reconfiguration circuit 8 to the instruction combination permission latches 111 to 114 independently of scan-in. In this embodiment, signal lines 191 and 291, which are the outputs of instruction group decoders 101 and 102, correspond to instructions that do not refer to the buffer memory, and signal lines 192 and 292 correspond to instructions that refer to the buffer memory, respectively.

HITAC: In M series computers, load register instruction L is an instruction that does not refer to buffer memory.
As an example, R is an instruction that refers to a buffer memory, and a load instruction L is an instruction that refers to a buffer memory.

FIG. 3 shows output signal lines 191 and 192 of instruction group decoders 101 and 102 in the parallel execution matching judgment circuit.
, 291 and 292 and the instruction combination permission latch 111~
This table shows a one-to-one correspondence between the stored contents of 114 and 114. The four instruction combination enable latches are
The value indicated by is written in advance by scan-in.

In this embodiment, the functions of the two arithmetic units 73 and 74 are equivalent, and in the initial state, the parallel combinational reconfigurable circuit 8 sends a signal to the selector 89 via a signal line 902 corresponding to a subsequent instruction. 912 is selected. During normal operation, two conceptually consecutive instructions are executed in parallel, regardless of their type.

Here, during the operation of this information processing device, the buffer memory 21
or 22, and when the output of one of the corresponding failure detection circuits 81 or 82 becomes positive, the parallel combinational reconfiguration circuit 8 receives this output.
writes the value 11 0 I+ to the instruction combination permission latch 114 via the signal line 901 so that it becomes the value shown in "When one buffer memory fails" in FIG. As a result,
Thereafter, it is no longer possible to execute instructions that refer to the buffer memory in parallel. On the other hand, the calculation unit 73 or 74
When a fault occurs in either one of the fault occurrence detection circuits 83 or 84 and the output of one of the corresponding fault detection circuits 83 or 84 becomes positive, the parallel combinational reconfiguration circuit 8 that receives this output operates as shown in FIG. Four instruction combination permission launches 111 are sent via the signal line 901 so that the value shown in "When one of the arithmetic units has a failure" is reached.
, 11.2, 113, and 114.

Further, when the occurrence of a fault is detected by the detection circuit 83, the selector 89 is instructed to select the signal line 911 corresponding to the preceding instruction via the signal line 902, and at the same time the arithmetic unit 73 in which the fault has occurred is instructed to select the signal line 911 corresponding to the preceding instruction. An operation instruction is issued to the arithmetic unit 74 via the OR circuit 891. By doing this, the parallel combination judgment circuit always outputs 11 0 I+, making it impossible to execute instructions in parallel, but it executes the instructions one by one by connecting one of the arithmetic units that is not malfunctioning. can continue.

FIG. 6 shows an example of the configuration of the parallel combinational reconfigurable circuit 8. OR circuits 601 and 602, which calculate the logical sum of the outputs of the failure detection circuits 81 and 82, and 83 and 84, respectively;
It consists of an instruction combination permission latch position determination write circuit 811 that writes to the instruction combination permission latch of the parallel execution combination determination circuit according to the output of the OR circuit. Arithmetic units 73 and 7 based on failure detection circuits 83 and 84
The fault occurrence detection results of 4 are logically summed by the OR circuit 602, and the fault occurrence detection results of the buffer memories 21 and 22 by the fault occurrence detection circuits 81 and 82 are ORed by the OR circuit 602.
A logical OR is taken with 1. The outputs of the two OR circuits are input to the instruction combination permission latch position determination writing circuit 811,
If at least one of these inputs is positive, it means that a functional failure has occurred in some of the components necessary for parallel execution of instructions, and as described above, the parallel execution combination determination circuit 1,
Instructions are given to arithmetic units 73 and 74 and selector 89, and parallel execution is partially or completely inhibited.

According to this embodiment, when a failure occurs in a part of a function in an information processing device that executes two consecutive instructions in parallel, only the parallel execution of instructions that use the function at the same time is limited. It is possible to suppress parallel execution to allow partial parallel execution to continue, or to completely suppress parallel execution to continue logically correct operation although processing efficiency is reduced accordingly.

In the above two embodiments, two types of arithmetic units,
Although the explanation has been limited to two instruction groups, such as whether or not to refer to the buffer memory, it can be easily extended to a case where there are three or more instruction groups.

A third embodiment of the present invention will be described using the first embodiment and FIGS. 8 and 9.

Figure 9 shows an example of the structure of a command word. R for command word
1. The first instruction format performs an operation using the contents of two registers indicated by Rx and writes the result to register R1. A second instruction format that performs an operation and writes the result to register Rz or a memory operand, and a third instruction format that performs an operation using the contents of the memory operands indicated by memory address 1 and memory address 2 and writes the result to memory operand 1. etc. In HITAC M series computers, the first instruction format is called the RR instruction, the second instruction format is called the RX instruction, and the third instruction format is called the SS instruction. here,
We will focus on the RR format and RX format.

FIG. 8 shows the configuration of the parallel execution combination determination circuit in this embodiment. 31 is a comparator that compares register numbers R1 in two instruction words.

Here, the two outputs of the instruction group decoders 101 and 102 are respectively 191 and 291, which correspond to the instruction writing to the general-purpose register, and 192 and 29, which correspond to the instruction writing to the general-purpose register.
2 corresponds to not writing.

Further, the instruction combination permission latch used in the first embodiment is excluded.

Now, assume that the two instructions to be executed in parallel are each in the RR format or the RX format. As described above, the outputs 191 and 291 of the instruction group decoder correspond to an instruction writing to register R1. When at least one of the two instructions is an instruction that does not write to a register, for example a store instruction, the two instructions are executed in parallel, as can be easily inferred from the above embodiment. However, when the two instructions are both instructions for writing to the register, the output of the comparison circuit 31 is "1".
”, the two instructions are executed in parallel.Here, the comparator circuit 31 outputs 11 1 17 when R1 in the instruction words are equal.

As described above, in this embodiment, when two instructions are instructions for writing to general-purpose registers, they are executed in parallel only when the register numbers to be written are the same. When two instructions write to the same register number, they are executed in parallel.

Needless to say, writing by one of the preceding instructions is unnecessary, and only writing by the following instruction is sufficient.

According to this embodiment, even when the general-purpose register group is configured such that writing can only be performed to one register at a time, instructions for writing to registers can be executed in parallel.

Note that this embodiment can be easily combined with the first and second embodiments.

〔Effect of the invention〕

According to the present invention, when designing an information processing device that executes two conceptually consecutive instructions in parallel,
When changing the specifications of buffer memory, arithmetic unit, etc. during the design process, the combination of instructions that can be executed in parallel can be changed flexibly without changing the parallel execution control hardware, which is effective in reducing design man-hours due to design changes. There is. Furthermore, according to the present invention, when a failure occurs in a part of the function in the information processing device, the operation of the entire processing device is suspended until the hardware of the function is recovered by limiting the combinations of instructions that can be executed in parallel. It is possible to minimize the decrease in instruction processing efficiency without stopping the process.

Furthermore, by combining the present invention with a circuit that compares a part (register part) of two instructions, it is possible to easily configure an instruction processing device that allows parallel execution only in special cases such as when there is a register dependency. can do.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a parallel combination determination circuit when the present invention is implemented, and FIGS. 2 and 3 are examples of instruction combination tables when the present invention is implemented. Figures 4 and 5
The figure shows an example of the configuration of an information processing device using the present invention.
FIG. 6 is a diagram showing one configuration example of a parallel execution combination reconfigurable circuit when the present invention is implemented, and FIGS. 7 and 8 are diagrams each showing other configuration examples of a parallel execution combination determination circuit according to the present invention. , FIG. 9 is a diagram showing an example of the structure of the instruction word, FIG. 10 is a diagram showing an example of the structure of the second arithmetic unit 72 in FIG.
FIG. 1 is a diagram showing an example of the configuration of the instruction reading circuit 3 shown in FIG. 4. In FIG. 1... Parallel execution combination determination circuit, 101, 102...
・Instruction group decoder, 111 to 114...Instruction combination permission latch, 121 to 124...AND circuit, 1
31,601,602,891...OR circuit, 21.
22...Buffer memory. 41.42... Instruction register, 71... First arithmetic unit, 72... Second arithmetic unit, 8... Parallel combinational reconfigurable circuit, 81-8
4...Failure occurrence detection circuit, 811...Instruction combination permission latch position determination writing circuit, 89...Selector. 1st cause 1st ward ■ j'l toz E L times W th (α) (})) 口茅Bi

Claims (1)

[Claims] 1. In an information processing device capable of mutually executing a plurality of instructions in parallel, a combination of a plurality of resource means capable of mutually operating in parallel and an instruction to be mutually executed in parallel is detected. An information processing device comprising: means for determining whether to permit or disallow execution of the detected combination of instructions in parallel. 2. In the information processing device set forth in paragraph 1, a plurality of resource means capable of mutually operating in parallel, a means for detecting a combination of instructions to be executed in parallel with each other, and a means for detecting a combination of instructions to be executed in parallel with each other, and a means for detecting a combination of instructions to be executed in parallel with each other; storage means that can be written at any time and holds a status bit indicating whether execution is permitted or not; means for reading out the storage means for retrieval based on a combination of the plurality of instructions; An information processing device comprising means for determining whether or not to execute the plurality of instructions in parallel based on a read result. 3. The information processing apparatus according to item 2, further comprising means for controlling the operation of all or part of each resource means in response to the determination result of the determination means. 4. In the information processing apparatus according to item 2 or 3, the failure occurrence detection means detects the occurrence of a failure in each resource means, and the memory means which can be written at any time can be executed in parallel by writing to the storage means. An information processing device characterized by having means for resetting a combination of instructions. 5. The information processing device according to item 4, characterized by having a circuit that allocates instruction execution to a resource means in which no fault has occurred based on the output of the means for resetting the combination when a fault occurrence is detected. Information processing device.