JPS60205490A - Display control circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a display control circuit having a random access memory (RAM) that stores digital nonaturn data, and a circuit that improves display effects such as screen division and partial scrolling. Regarding.

[Technical background of the invention]

The circuit for displaying an image on the screen of a cathode ray tube is a circuit that stores digital pattern data in the image RAM K through data processing by a microprocessor, reads out the contents using a high-speed counter, and displays the image on the screen. widely known.

FIG. 1 shows the configuration of this type of display control circuit, and FIG. 2 shows its operating signal waveform.

The capacity of the image RAM 79 is determined by the number of dots in the horizontal (H) direction and the number of lines in the vertical (V) direction on the display screen. Here, in order to explain the conventional example, we will use 256 dots horizontally and 204 dots vertically.
Line. Display clock obtained from oscillator J1 (
CP)Fi, can be determined from the relationship between the number of horizontal dots, the horizontal frequency of the display section, and the retrace period. Here image 99 RAM
In order to adjust the access time with No. 19, the image data is accessed on a 4-bit (1 word) basis. This 4
The part that counts bits is the bit counter 12, and the part that counts words is the word counter 13.
3 constitutes a tH advance counter that can fail in one horizontal period. That is, the outputs of the bit counter 12 and word counter I3 are input to the horizontal signal generating section 14.

This horizontal signal generating section 14 includes a horizontal signal (H8) generated once in one horizontal period, various timing signals Tl, T2,
Generates synchronization signal (5YNC), etc. ・Horizontal signal (H8)
is input to the line counter 15 and used as a clock. This line counter 15 constitutes a ty signal corresponding to one vertical period, and inputs its output to the vertical signal generating section 16. The output dirt signal G of the vertical signal generating section 16 gives vertical timing to the output of the horizontal signal generating section 14.

The addresses required to access the image RAM 19 are 6 word addresses (bits) and 8 line addresses (bits), a total of 14 addresses (bits), and these are connected via the synthesis circuit 17 and address switch 18. Image RAM
19 K is given to the address switch 18, the image R
Only during the data read period of AM J 9, the timing signal T2 selects the address data on the synthesis circuit 17 side and applies it to the address input end of the image RAM J 9. The data read from the input/output terminals of the image RAM 19 is converted into serial data by the parallel/serial conversion circuit 2o, and outputted via the AND circuit 21t.

Figure 2 shows the display clock (CP) and image RA11111.
Address data for 9 (Ao - A2), image R
Output data of AM 79 (D'o - D2), timing signal TI, serial output data from AND circuit 21 (
SD).

The above is the data reading process for the image RAM 19, and the next data omitting process will be explained. Microglosse (MPU) 22, Read Only Memory (ROM) 23, Random Access Memory (
RAM) 24, Chig selector 25, bidirectional path,
The FA circuit 26 and the like obtain the main operation during r-data writing. Write data to the image RAM 19 is outputted to the data bus (DBUS) K and passed through the bidirectional buffer circuit 26 to l! 1Iil# RAM 79. There is also an address switch, address bus (ABUS), 'address switch 187!' that specifies the destination of the image RAM 19. i- given via. Therefore, at this time, the bidirectional buffer circuit 26 and the address switch 18 are controlled by a timing signal T2 that distinguishes between a non-display period and a display period (256 lines in the horizontal direction and 204 lines in the vertical direction).

[Problems with background technology]

When controlling the entire screen of 256 dots horizontally and 204 lines vertically, the conventional circuit configuration described above is sufficient. However, if you want to perform processing that divides the display screen into several parts (for example, a replacement screen, partial vertical scrolling, etc.), the contents of the image RAM corresponding to the position on the screen you want to display are
It is necessary to rewrite the content stored in the work RAM in advance. Furthermore, in this case, if the original screen information is also to be saved, it is necessary to partially rewrite and at the same time move the original screen information to a free area of the work RAM and store it. Furthermore, when partially vertically scrolling a part of the entire screen, the data in the scroll specified area is changed by shifting the data by (words x lines of the area) by 1 in the non-display period. must be processed. As mentioned above, in either case, data processing is required to replace all the contents of the divided image RAM, and when displaying divided images on many screens, data processing time is insufficient. : There is a lump.

[Purpose of the invention]

This invention was made in consideration of the above-mentioned circumstances, and it displays images as if the display screen were divided. in
It is an object of the present invention to provide a display control circuit that can improve data processing speed when performing display.

[Summary of the invention]

In this invention, as shown in FIG. 3, a line address conversion RAM JE is provided so that the read line address of the image RAM 19 can be freely viewed.

Next, mapping RA not only obtains line address switching timing information from the line counter 15 but also reads horizontal scanning position information as timing information.
M36 is provided so that the input data of the line at conversion RAM 33 can be corrected by the correction data from the mapping RAM J6. As a result, display effects (partial scrolling, partial replacement, image assembly) on multiple screens with a high degree of freedom can be obtained at high speed.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows one embodiment of the present invention, and the same parts as the circuit of FIG. 1 are given the same reference numerals and will be explained.

According to the present invention, when reading data from the image RAM 19, the line addresses are switched and designated according to a preset order, and multi-screen data can be read out. The perfect unit to form a multi-screen! In this embodiment, 4 dots x 4 lines are allocated as the minimum unit for the lock screen. Therefore, the total screen area is 256 dots x 204 lines, so 64 x 51
=3264Pro can be set.

Next, to address the area of each unit block,
Set 4 bits. This is information equivalent to dividing the entire screen into 16 parts.

The above 4-bit address conversion information is stored in the mapping RAM.
This mapping RAM 36
The data read from the line counter 15 is combined with the data of the line counter 15 in the combining circuit 3, and the 12-bit conversion information is provided to the line address conversion RAM 33 via the address switch 32. Line address conversion■33
outputs line address data (8 bits) based on the 12-bit conversion information, and this data is sent to the synthesis circuit 1.
7, applied to the addressing terminal of the image RAM 19 via the address switch 18. Matuping RAM 3
The read address No. 6 is specified by inputting the outputs of the word counter 13 and line counter 15 via the combining circuit 34 and the address switch 35, and the read order is determined in synchronization with the scanning line. ing.

That is, the circuit of the present invention has a combination circuit 31, an address switch 32, and a line address conversion RA compared to the conventional circuit.
M33, synthesis circuit 34, address switch 35, mapping RAM 36, bidirectional buffer circuit 37.3
8 has been added.

As the horizontal address data input to the synthesis circuit 17, the output of the word counter 3 is input, but as the vertical address data, the output of the line counter I is input.
The output of 5 is corrected by the synthesis circuit 3, inputted to the line address conversion RAM 3J via the address switch 32, converted there, and then inputted to the synthesis circuit 17. The modification data is 4-bit data from mapping RAM 36. The data in this mapping RAM 36 is stored in each of the six word counters 13 and line counters 15.
Bit data is synthesized by a synthesizer 34 and read out by addressing via an address switch 35.

The bidirectional buffer circuit 37 has a line address change) JR
AM 33 K is a circuit that forms a data path when address data is written from the microgrossesser 22 side. In addition, the bidirectional buffer circuit 38Fi, mapping R
This circuit forms a data path when the corrected data is input into the AM 36 from the microgross 722 side. When the data from the microphone agrocessor 22 side is written to the line address conversion RAM J 3 and the mapping RAM 36, the address switches 32 and 35 respectively select the address data from the microgrossessor side and write the corresponding data. Input to RAM.

The display control circuit of the present invention is constructed as described above, and its basic operation is the same as that shown in FIG.
A function is provided to freely change and set the readout lines of 9.

Now, for example, as shown in FIG. 4(,), image A.

It is assumed that data of Ik, C, and D are stored in the image RAM 19. If you read this in the normal way,
As shown in FIG. 4(b), four screens are displayed vertically. Next, if images $A, half A7 of C, and CI are to be displayed vertically, and halves B1 and B2 of image B are to be displayed vertically, the screen Anl will be displayed by 7 horizontal periods (H
), line Bn7 is read out for the next 7 horizontal periods (
H) is read out, and then the mapping RAM S is read so that the life An2 can be alternately switched to Σf (and the line Bnl to ΣH).
It is sufficient to store the correction data in 6.

And image k1. When the BI combination is completed, (1) 7H is read out from line Cnl, the process returns to line Bn7 again, TI is read out, then 7H is read out from line Cn2 again, and the process returns to line Bn2. By obtaining such line switching, it is possible to freely obtain combinations of images.

Furthermore, the image RAM I9 has a buffer area 191.
exists as shown in FIG. 4, but this area can be effectively used when partially scrolling a part of the screen. For example, when attempting to vertically scroll the screen B part in FIG. If it is a line, it is sufficient to move to the newly written line/data line Fnl. Next, this time reading starts from line t3n3 of image B, and the missing part of the image area is replaced by line Fn1 with new line data. Read from Fn2, this is 5
It is good to repeat the line specification repeatedly. Furthermore, when replacing the screen, you can change the line at the timing when the data of image B would normally be read, and change the line to read the data of the image, leaving the data of image B. Get the screen replaced.

For example, if you want to erase screen A and display it, use uzby
It is sufficient to specify that one line of data (no recording or all 1's) in the 7A area 191 be read out repeatedly in sections on the screen.

〔Effect of the invention〕

According to the invention described above, first, by providing the line address conversion RAM 33, the image RAM 19
It is possible to obtain display effects such as partial scrolling at high speed by switching and changing the line address data without having to directly rewrite the data.

Furthermore, according to the invention, the line address conversion RAM
The line address information is not simply inputted from the line counter 15 to Jj. In other words, Matuping RA
The corrected data is read from M36, combined with the output data of the line counter 15, and the combined data is input to the line address conversion RAM 33. Moreover, Ma.

The modified data in the bin f RAM J 6 is read out based on the outputs of the word counter 13 and line counter 15. This means that when changing the line address, it is not only possible to change it at the start of horizontal scanning, but also to provide horizontal position information so that the readout line can be changed by t/l even in the middle of horizontal scanning. means to be As a result, many display effects such as changing the position of split screens, combining them, erasing parts, and replacing them can be easily obtained in a short period of time, which is extremely advantageous for multi-screen display devices. .

If you increase the number of bits of Mataping lζAM36,
The number of divided blocks has increased, and in addition, the number of divided blocks has increased to 18 RA.
By increasing the buffer area of M19, you can create a screen with a higher degree of freedom.

[Brief explanation of drawings]

Figure 1 is a plotter diagram showing a conventional display control circuit;
1 is an operational waveform diagram of the circuit shown in FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is an explanation shown to explain an example of display control operation of the display control circuit of this invention. It is a diagram. 13...Word counter, 15...Line counter,
1g, 32.35...Address switch, 19...Image RAM, 3J, 3(...Synthesizing circuit, 33...Line to V/S conversion RAM, 36...Mapping RAM.

Claims (1)

[Claims] Display device t K-4' for displaying turn data
It has an image memory in which the digital pattern data can be written or read, a word counter that outputs horizontal address data when reading data from the image memory, and a line address generation means that outputs vertical line address data. In the display control circuit, the line address generating means includes a line counter that counts the number of lines t of the display device based on the output of the word counter, and an address that converts input data and outputs address data of the line. conversion memory,
a synthesis circuit that synthesizes the output of the line counter and the correction data to generate the input data to be applied to the address conversion memory; and a synthesis circuit that is capable of reading and writing the correction data, and that changes the line address by the correction data applies to the entire image memory. A display control characterized by comprising: a mapping memory stored so as to divide an area into a plurality of areas; and means for reading out the modified data in the mapping memory based on the outputs of the word color/line counter. circuit.