JPS60198897A - Method of producing multilayer printed circuit board - Google Patents

Method of producing multilayer printed circuit board

Info

Publication number
JPS60198897A
JPS60198897A JP5654684A JP5654684A JPS60198897A JP S60198897 A JPS60198897 A JP S60198897A JP 5654684 A JP5654684 A JP 5654684A JP 5654684 A JP5654684 A JP 5654684A JP S60198897 A JPS60198897 A JP S60198897A
Authority
JP
Japan
Prior art keywords
resist
plating
circuit board
printed circuit
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5654684A
Other languages
Japanese (ja)
Inventor
岡村 寿郎
▲つる▼ 義之
昭士 中祖
魚津 信夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Lincstech Circuit Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Hitachi Condenser Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd, Hitachi Condenser Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP5654684A priority Critical patent/JPS60198897A/en
Publication of JPS60198897A publication Critical patent/JPS60198897A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (芹条土のオリ用号1’? ) A弁明り多増印刷配悔叡の製造法に関すを。[Detailed description of the invention] (Serijo soil ori number 1'?) A: Concerning the manufacturing method of a large number of printed condolences.

(使米技ψ1σ) 多層印刷配lfM似に、汐りえは特公昭38−1497
7号公報に示さn心ように1両面に配ア脈パターン【重
子基板とプリプレグ【父互にム、ね台せイ貞層プレスし
、槓ノー波孔で開けて、全開に化学鋼めっきと電解銅め
っ@で應し、その仮エツチングレジストを血イhし不安
の銅層tエツチングして製造している。しかし多層化嵌
屓にプリプレグtブ「してブレス槓)IIit?Tう7
ζめ、大型の製造装置が必袈と77:9コスト世諷にも
限界かめ6゜ (発明の目的) 不発明けこのような点に1みてなきn1ζもので、低コ
ストで製造し侍Φ旨1警度パターン多l蚊印桐配@板の
製造法忙提供するものである。
(Use rice technique ψ1σ) Similar to multi-layer printing layout lfM, Rie Shio is a special public official 1497-1977.
As shown in Publication No. 7, the conductor pattern [multilayer board and prepreg] was pressed on one side with the n-core layer, and then the layer was pressed, drilled with a no-corrugated hole, and fully exposed with chemical steel plating. It is manufactured by plating with electrolytic copper plating and etching the copper layer using the temporary etching resist. However, when multi-layering is applied, the prepreg is
ζ, large manufacturing equipment is required, and the cost is 77:9, and the limit is 6゜ (objective of the invention). The manufacturing method of the 1st degree pattern multi-mosquito ink paulownia plate is provided.

(発明の楊g) 本発明a久の工程?含む多ノシ印桐酩腺也の装造法であ
る0すなわち、 A、極傳金拘法9.b媒入り杷6基似に、めっきレジス
トτj詫ノ双し、無−鱗めっg ’I:’(J ’) 
(Yang g of invention) Process of this invention for a long time? 0, which is the method of dressing Tanoshi Indou Adenya, including: A, Gokuden Kinkoho 9. Similar to the 6 loquats containing B, the plating resist τj is used, and no scales are used. 'I:'(J')
.

B、めっきレジストを剥船してクイックエッナング【行
いめっきレジストが形成さIした′画用の毬傅金Mτ除
去するO C0全表囲に触媒人9接眉沖」を塗イb1ゐ。
B. Strip off the plating resist and perform quick etching [After the plating resist is formed, remove the paint mold Mτ and apply catalyst 9 engravings on the entire surface. .

D、廣眉Δり驕を粗化丁ゐυ E、無′屯mめつさレジストτ形成1゛る0ド、スルー
ホールを明ける0 6゜焦゛龜房めっき欣に(支)供し、レジストが形成a
rしていないrib)’)+に無電解めっさ笛行う。
D, Roughen the wide eyebrows Δ, D, Roughen the width, E, Form a resist τ, open a through hole. Resist is formed a
Perform an electroless whistle on the rib)')+ that has not been r.

以1図囲に基いて本発明を説明する〇 パラジウム、白金、調停無電屏銅υりきに対重ゐ醐媒が
混入さrtた槙鳩似1に触妹人か歇μm〜10μm程1
紺の惨博銅泊2τ法り会ぜた儲博銅加槙増板(aJにめ
っきレジスト6τ)形成し、 (bJ。
The present invention will be explained based on the following figure 1. 〇Palladium, platinum, and non-electroplating copper υ were mixed with a heavy alcoholic medium.
A dark blue copper plating plate was formed using the 2τ process, and a plating resist 6τ was formed on aJ (bJ).

煕屯屑鉋めっさ畝V(置誠し、無電解銅めつさ4忙イ’
fい内!曽回路パターンて形成する<C)Q内層回路4
「11縫が同上し、市1密1糺目己餓刀島口」hヒとな
る〇又、内層に候7#鳩なしのエツチング法で作り7C
回剤板τ使用し侍ゐことになめ。
Hitun scrap plane Messaune V
Inside! <C) Q inner layer circuit 4 formed by the circuit pattern
"11 stitches are the same as above, city 1 dense 1 tajime self-gutter Shimaguchi" hhi 〇 Also, the inner layer is made using the etching method without 7 # doves 7C
I used the medicine board τ and licked it to the samurai.

久にυつきレジストf味太しくa)、艷のクイックエッ
ナング?Il−何い、めっきレジストが形成さnていた
+i!a酒の極博剣k・除去し内層回路パターン盆児既
す^(e)。
Resist f taste thick with υ for a long time a), quick engraving of 艷? Il-What, plating resist was formed! A sake's ultimate sword k-remove the inner layer circuit pattern Bonji already ^(e).

次に7!11i媒入り猿ノβ創5 f Q Jli丁ゐ
(f)。この接看剤は塗イfJs ま7ζはホットロー
ル等の大ルリプレス忙必襞としない方法で形成しイ47
ゐ〇化学組化准で州北で行い(ω、レジスト6τ形成し
くh)、スル伺貨ル7ン曲けゐ。この場廿、スルーホー
ル開け→レジスト形成→粗化でも良い。
Next, 7!11i Intermediate Monkey β Creation 5 f Q Jli Ding (f). This adhesive is coated and formed using a method that does not require large presses such as hot rolls.
ゐ○ Chemical recombination was carried out in Shukoku (ω, resist 6τ was formed), and 7 rounds were bent. In this case, it may be possible to open a through hole → form a resist → roughen it.

スルーホールτ開けるのtコバンテで竹う0バンチ穴形
状eJ、複雑であり、電気めっきの場合σめっきボイド
が発生しやすいが、無電解銅めつ@けつさまわ9性が艮
(、低コスト、スば子処理がない利点もある。スルーホ
ールにドリルで開けることも出来る0 次に、無電解銅&つつき欲に反眞し、レジストが形成さ
nていない、スルーホール、及びその周辺に無1!を解
めっき8を行う(it。
Opening the through hole τ is complicated, and σ plating voids are likely to occur in the case of electroplating. , there is also the advantage that there is no sintering process.Through holes can also be drilled.Next, resisting the desire to use electroless copper and poking, resist is not formed, and through holes and their surroundings can be drilled. Solve No. 1! and perform plating 8 (it.

以上4j曽のものVCついて説明し罠が、6壱又に5鳩
以上のものも裏遺し侍ゐ。
Above I have explained about the VC of 4J So, but there are also traps that leave behind 6 Ichimata and 5 or more pigeons.

(発明の籾米) 以上説明し′f′c不発明により次の効果が雇成さIL
ゐ〇 (1) 7ルス槓鳩τ行なlりないので低コストが口J
h−となゐ0 (2)絶縁τかねπ候漕岸」盾τ仕怠り厚さに出来心の
で、インピーダンス)u!I御が容易である。
(Paddy rice of invention) As explained above, 'f'c non-invention has the following effects IL
ゐ〇(1) There is no 7-Russ flying pigeon τ line, so the cost is low.
h-tonai 0 (2) Insulation τ or π due to the thickness of the shield τ, impedance) u! Easy to control.

【図面の簡単な説明】[Brief explanation of the drawing]

凶囲a本晃明の方法でボす幼囲図であ壱〇符号の説明 1、tlすf々1(人!1lii* ノーinシ2、巾
訊博★同ン白 & レジスト 4、内)曽[11」路 5、触媒人!7接*剤 6、 レジスト 乙 スルーホール a 無゛屯屏蛤めつさ 代理へ升埋士 若 林 邦 彦 手l続補正書(方式) 昭和 59′Fニア月IB日 発明の名称 多層印刷配線板の製造法 補正をする者 補正命令の日付 昭和59年6月26日(発送日)補正
の内容 (1)明細書3頁9行〜4頁17行I:、「以下図面に
基いて〜無電解めっき8を行う(1)。」とあるのを次
のように訂正する。 [以下図面に基いて本発明を説明する。 パラジウム、白金、調停無電解銅めっきに対する触媒が
混入された積層板1に触媒入り数μm〜10μm程度の
極薄鋼箔2を張り合せた極薄銅張積層板(第1図)にめ
っきレジスト6を形成しく第2図)、無電解銅めっき液
に浸漬し、無電解銅めっき4を行い内層回路パターンを
形成する(第3図)。内層回路精度が向上し、高密度配
線が可能となる。 又、内層に接着層なしのエツチング法で作った回路板を
使用し得ること罠なる。 次にめっきレジストを除去しく第4図)、銅のクイック
エツチングを行い、めりきレジストが形成されていた箇
所の極薄銅を除去し内層回路パターンを完成する(第5
図)。 次に触媒入り接着剤5を塗布する(第6図)。 この接着剤は塗布、またはホットロール等の大型プレス
を必要としない方法で形成し得る。 化学粗化液で粗化を行い(第7図)、レジスト6を形成
しく第8図)、スルーホール7を開ける(第9図)。こ
の場合、スルーホール開け→レジスト形成→粗化でも良
い。スルーホールを開けるのはパンチで行う。パンチ穴
形状は、初雑であり、電気めっきの場合はめっきボイド
が発生しやすいが、無電解銅めっきはつきまわり性が良
く、低コスト、スミア処理がない利点もある。スルーホ
ールはドリルで開けることも出来る。 次に、無電解鋼めっき液に浸漬し、レジストが形成され
ていない、スルーホール、及びその周辺に無電解めっき
8を行う(第10図)。」(2)明細書5頁、図面の簡
単な説明の欄を次のよう忙訂正する。 「第1図〜第10図は、本発明の方法を示す断面図であ
る。」 (3)図面の全てを、別紙のとうり訂正する。 以上 第1頁の続き [相]発明者 魚津 信夫栃木 会社
Explanation of 1〇 code 1, tlsu ffu 1 (person! 1lii * no in shi 2, wakan Hiroshi★ same white & resist 4, in) Zeng [11] Road 5, catalyst person! 7 Adhesive 6, Resist B Through Hole A Mutsu-tun Hamaguri Metsusa Substitute to Masu Burialist Kuni Wakabayashi Hikote I Continuation Amendment (Method) Showa 59'F Near Month IB Date of Invention Name Multilayer Printed Wiring Date of amendment order by the person amending the manufacturing method of the plate: June 26, 1980 (shipment date) Details of the amendment (1) Specification page 3, line 9 to page 4, line 17 I: ``The following is based on the drawings...'' Perform electroless plating 8 (1).'' should be corrected as follows. [The present invention will be explained below based on the drawings.] A plating resist is applied to an ultra-thin copper-clad laminate (Fig. 1) in which a catalyst-containing ultra-thin steel foil 2 of several μm to 10 μm is laminated to a laminate 1 mixed with palladium, platinum, and a catalyst for mediation electroless copper plating. 6), then immersed in an electroless copper plating solution to perform electroless copper plating 4 to form an inner layer circuit pattern (FIG. 3). The accuracy of inner layer circuits is improved and high-density wiring becomes possible. It is also possible to use etched circuit boards without an adhesive layer on the inner layer. Next, the plating resist is removed (Fig. 4), and quick copper etching is performed to remove the extremely thin copper where the plating resist had been formed to complete the inner layer circuit pattern (Fig. 5).
figure). Next, a catalyst-containing adhesive 5 is applied (FIG. 6). The adhesive may be applied or formed by methods that do not require large presses, such as hot rolls. Roughening is performed with a chemical roughening solution (FIG. 7), a resist 6 is formed (FIG. 8), and a through hole 7 is opened (FIG. 9). In this case, the process may be as follows: opening a through hole → forming a resist → roughening. Use a punch to open the through hole. The punch hole shape is rough and plating voids are likely to occur in the case of electroplating, but electroless copper plating has the advantage of good throwing power, low cost, and no smear treatment. Through holes can also be drilled. Next, it is immersed in an electroless steel plating solution to perform electroless plating 8 on the through holes and their surroundings where no resist is formed (FIG. 10). (2) On page 5 of the specification, the column for a brief explanation of the drawings has been amended as follows. ``Figures 1 to 10 are cross-sectional views showing the method of the present invention.'' (3) All figures in the drawings will be corrected as separate sheets. Continuation of page 1 [phase] Inventor Nobuo Uozu Tochigi Company

Claims (1)

【特許請求の範囲】 1、次の工程tゴむ多膚印刷配腺似の製造w0A、Zr
1lA薄金@叛り、触媒入り絶縁基板にめっきレジスト
τ形成し、無′a解めっ@を竹う。 B、めっきレジスト【剥^1してクイックエッナングτ
行いめっきレジストが形成さn 7を画用の他博釡鵜を
除去するO C8全表曲に触媒人V接′4創忙呈而する。 D、接虐削鳩τ租化すん。 E、無電解めっきレジストを形峨丁ゐ。 F、スルーホールで明は心。 G、無%屏めっき敵に浸漬し、レジストがブレノ戎さf
していない固n1に無電解めっきτ何9゜
[Claims] 1. Next step t Manufacture of rubber printed gland pattern w0A, Zr
A 11A thin gold plate was formed on the catalyst-containing insulating substrate, and a non-a-plated plate was applied. B. Plating resist [Peel ^1 and quick etching τ
After the plating resist is formed, the catalytic contact '4 will be applied to the OC8 complete table, which will remove the n7 and other parts used for painting. D. I'm going to turn into a pigeon. E. Shape the electroless plating resist. F, through hole and light is heart. G, No% immersion in the plating enemy, the resist is blemish f
Electroless plating on solid n1 without τ9゜
JP5654684A 1984-03-23 1984-03-23 Method of producing multilayer printed circuit board Pending JPS60198897A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5654684A JPS60198897A (en) 1984-03-23 1984-03-23 Method of producing multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5654684A JPS60198897A (en) 1984-03-23 1984-03-23 Method of producing multilayer printed circuit board

Publications (1)

Publication Number Publication Date
JPS60198897A true JPS60198897A (en) 1985-10-08

Family

ID=13030086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5654684A Pending JPS60198897A (en) 1984-03-23 1984-03-23 Method of producing multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS60198897A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06104570A (en) * 1992-09-18 1994-04-15 Shin Kobe Electric Mach Co Ltd Production of multilayer printed wiring board

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856386A (en) * 1981-09-29 1983-04-04 日立化成工業株式会社 Method of producing printed circuit board
JPS58161760A (en) * 1982-03-18 1983-09-26 Matsushita Electric Ind Co Ltd Method for plating on aluminum substrate
JPS58161759A (en) * 1982-03-18 1983-09-26 Matsushita Electric Ind Co Ltd Method for plating on aluminum base plate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856386A (en) * 1981-09-29 1983-04-04 日立化成工業株式会社 Method of producing printed circuit board
JPS58161760A (en) * 1982-03-18 1983-09-26 Matsushita Electric Ind Co Ltd Method for plating on aluminum substrate
JPS58161759A (en) * 1982-03-18 1983-09-26 Matsushita Electric Ind Co Ltd Method for plating on aluminum base plate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06104570A (en) * 1992-09-18 1994-04-15 Shin Kobe Electric Mach Co Ltd Production of multilayer printed wiring board

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