JPS62145796A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPS62145796A
JPS62145796A JP28670085A JP28670085A JPS62145796A JP S62145796 A JPS62145796 A JP S62145796A JP 28670085 A JP28670085 A JP 28670085A JP 28670085 A JP28670085 A JP 28670085A JP S62145796 A JPS62145796 A JP S62145796A
Authority
JP
Japan
Prior art keywords
plating
resist
etching
printed wiring
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP28670085A
Other languages
Japanese (ja)
Other versions
JPH0654832B2 (en
Inventor
邦司 鈴木
▲つる▼ 義之
上山 宏治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP28670085A priority Critical patent/JPH0654832B2/en
Publication of JPS62145796A publication Critical patent/JPS62145796A/en
Publication of JPH0654832B2 publication Critical patent/JPH0654832B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、無電解鋼めっきを採用した高密度印刷配線板
の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a high-density printed wiring board using electroless steel plating.

(従来の技術) 従来の印刷配線板の代表的製造方法は、(1)テンティ
ング法、(2)はんだ法、(3)部分アディティブ法、
(4)フルアディティブ法がある。第2図にテンティン
グ法の一例を示すが、b)穴明け、C)触媒処理、無電
解鋼めっき、d)電気めっき、e)エツチングレジスト
形成、 f)エツチング、g)エツチングレジスト除去
、h)ソルダレジスト形成の工程により印刷配線板を製
造する。また、はんだ法はエツチングレジストの代りに
はんだを用いるが、第2図のe)工程が第3図のe、)
レジスト形成、e2)はんだめっき、e3)レジスト剥
離の工程となる。部分アディティブ法は、表面回路を銅
箔、穴内を無電解鋼めっきで行う方法であってその主な
工程を第4図に示す。こlrLは、b)エツチングレジ
スト形成、C)エツチング、エツチングレジスト剥離、
d)めっきレジスト(ソルダレジスト)形成り e)穴
明け、f)無電解鋼めっきという工程である。
(Prior art) Typical conventional methods for manufacturing printed wiring boards include (1) tenting method, (2) soldering method, (3) partial additive method,
(4) There is a fully additive method. Fig. 2 shows an example of the tenting method, which includes b) drilling, C) catalyst treatment, electroless steel plating, d) electroplating, e) etching resist formation, f) etching, g) etching resist removal, h ) A printed wiring board is manufactured by a process of forming a solder resist. Also, in the soldering method, solder is used instead of etching resist, but step e) in Figure 2 is replaced by step e,) in Figure 3.
The steps are resist formation, e2) solder plating, and e3) resist peeling. The partial additive method is a method in which the surface circuit is formed with copper foil and the inside of the hole is formed with electroless steel plating, and its main steps are shown in FIG. This lrL includes b) etching resist formation, C) etching, etching resist peeling,
The steps are d) forming a plating resist (solder resist), e) drilling holes, and f) electroless steel plating.

最後にフルアディティブ法であるが、こnは接着剤付触
媒入り基板を用いて、無電解鋼めっきにより表面回路及
び穴内めっきを行うものであり、その工程は第5図b)
穴明け、C)永久フォトぬっきレジスト形成、 d)ぬ
っき、e)ソルダレシスト形成による。
Finally, the fully additive method uses a catalyst-containing substrate with adhesive and performs surface circuit and hole plating by electroless steel plating, and the process is shown in Figure 5b).
By drilling, C) forming a permanent photoresist, d) plating, and e) forming a solder resist.

(発明が解決しようとする問題点) テンティング法及びはんだ法に共通の問題点は、電気め
っきで大円を厚付けするために、高密度化に伴う小径穴
でのめっきつきまわり性が悪く、板肉のめっき厚みが不
均一である。かつ、導体が銅箔、無電解銅めっき、電気
鋼めっきにより構成されているため、平面部の回路パタ
ーンが厚く、エツチングによって回路を形成する場合ア
ンダーカットの問題があり、パターン密度に自ずと制限
がある。
(Problems to be Solved by the Invention) A common problem with the tenting method and the soldering method is that because the large circles are thickened by electroplating, the plating coverage is poor in small diameter holes due to high density. , The plating thickness of the plate is uneven. In addition, since the conductor is made of copper foil, electroless copper plating, and electrical steel plating, the circuit pattern on the plane part is thick, and when forming a circuit by etching, there is a problem of undercutting, which naturally limits the pattern density. be.

さらに、テンティング法については、パッド面積が小さ
い場合はレジストと銅箔の密着力がエツチング液の吹付
けによる衝撃に対して不足になり、レジストが剥離して
エツチング液が大円にしみ込むという問題もあり、篩密
度化への対応が困難である。
Furthermore, with the tenting method, if the pad area is small, the adhesion between the resist and the copper foil is insufficient to withstand the impact of the spraying of the etching solution, causing the resist to peel off and the etching solution to seep into the large circle. Therefore, it is difficult to cope with increasing sieve density.

又、部分アディティブ法では、永久フォトレジストを用
いる場合はパリ取り及び多層機におけるスミア処理が出
来ないという間順があり、インクレジスIf−用いる場
合は前NL VC加えインクのにじみ及びめっき液のレ
ジスト下へのしみ込みの問題がある。加うるに、触媒入
り基板を使わなけγLはならないためコス)4になる。
In addition, in the partial additive method, if a permanent photoresist is used, deburring and smear processing in a multilayer machine cannot be performed, and if an ink resist is used, the pre-NL VC, ink bleeding and plating solution resist. There is a problem with seepage to the bottom. In addition, the cost becomes 4 because γL cannot be achieved unless a catalyst-containing substrate is used.

また、ツルアディディプ法では、回路パターン以外の部
分にめっきが析出する(銅ふり)という問題があり、高
密度化しにくい。さらに、多層化する場合には工程が増
えてコスト高となる。
In addition, the Tsuruadidip method has the problem that plating is deposited on areas other than the circuit pattern (copper deposition), making it difficult to achieve high density. Furthermore, in the case of multi-layering, the number of steps increases, resulting in higher costs.

(問題点を解決するための手段) 以上の問題点を解決するための検討全本発明者は種々行
った。表面回路パターン及びスルーホールだけを無電解
銅めっきする製造方法全検討したが、この工程では溶剤
現像型ドライフィルムの耐めっき液性が問題となる。ド
ライフィルムは、標準的ラミネートでは無電解鋼めっき
液中で剥がれる。また、表面銅箔全酸化処理した後ラミ
ネートしても、回路パターン、スルーホールパッドエツ
ジ部分から酸化鋼が還元さiL剥がn易くなる。又、公
知例として報告さnているベンゾトリアゾール処理でも
、密着性は向上するが一部剥がちる。
(Means for Solving the Problems) The inventors of the present invention have conducted various studies to solve the above problems. All manufacturing methods have been investigated in which only the surface circuit pattern and through-holes are electrolessly plated with copper, but the resistance of the solvent-developed dry film to the plating solution becomes a problem in this process. The dry film will peel off in an electroless steel plating solution for standard laminates. Furthermore, even if the surface copper foil is laminated after being fully oxidized, the oxidized steel will be reduced and easily peeled off from the circuit pattern and through-hole pad edge portions. Furthermore, benzotriazole treatment, which has been reported as a known example, improves adhesion but causes some peeling.

以上の検討結果をもとに、本発明は小径穴を有する高密
度印刷配線aの製造法を提供する。
Based on the above study results, the present invention provides a method for manufacturing high-density printed wiring a having small diameter holes.

本発明は、溶剤現像型フォトレジストの耐めっき液性向
上の手段として次に挙げるものを用いた。
The present invention uses the following as means for improving the plating solution resistance of a solvent-developed photoresist.

(1)  フォトレジストラミネート前に、基板表面銅
箔に砥粒を高圧で吹きつける方法によって粗面化する。
(1) Before photoresist lamination, the surface of the copper foil on the substrate is roughened by spraying abrasive grains at high pressure.

(2)  基板表面をアルカリ脱脂溶液および/または
トリアゾール基を含んだ有機化合物溶液に浸漬処理する
(2) The surface of the substrate is immersed in an alkaline degreasing solution and/or an organic compound solution containing a triazole group.

(3)  フォトレジストのラミネート、露光、現像後
さらに紫外線露光および加熱を行う。
(3) After laminating, exposing and developing the photoresist, it is further exposed to ultraviolet light and heated.

(作用) エツチング用ドライフイルラの耐めっき液性を向上させ
たことによって従来不可能であった表面回路の長時間め
っきが可能となった。その結果として、表面鋼のエツチ
ングも銅箔部のみであり、非常に良いエツチングファク
ターとなる。これによす萬密度細線パターンが形成し易
くなった。また、穴内もすべて無電′M、銅めっきで形
成していることより、小径穴でも良好なめっきつきまわ
り性を示し、高性能めっき液を高活性で用いるため製品
の接続信頼性も良い。
(Function) By improving the plating solution resistance of the dry filler for etching, it has become possible to plate surface circuits for a long time, which was previously impossible. As a result, the etching of the surface steel is limited to the copper foil portion, resulting in a very good etching factor. This made it easier to form a high-density fine line pattern. In addition, since the inside of the hole is all electroless and copper plated, it shows good plating coverage even in small diameter holes, and the connection reliability of the product is also good because a high-performance plating solution is used with high activity.

実施例 第1図は、本発明の印刷配線板の製造方法を示すもので
、以下図面によって本発明全説明する。第1図b)の穴
明けは、穴明は機により行う。
Embodiment FIG. 1 shows a method of manufacturing a printed wiring board according to the present invention, and the present invention will be fully explained below with reference to the drawings. The holes shown in Figure 1 b) are made using a machine.

特に小径ドリルでは折れや穴品質を考慮して20〜50
μm/ r e vの値とする。次に無電解銅めっき用
触媒MS−201B(日立化成KK製)により穴に触媒
全付与し表面全研摩する。さらに表面処理を行って溶剤
現像型フォトレジストフィルムをラミネートする。表面
処理としては、まず20〜40ttmの砥粒’に3〜6
kg/aII+のポンプ圧で基板表面に吹きつけ、?′
にいてアルカリ脱脂液HCR−201(日立化成KK製
)チたはベンゾトリアゾール溶液(和光紬薬KK製)で
処6一 理する。この時、両方の溶液で処理すnげ効果は太きく
 trる。さらに基板を100〜120℃に加熱しレジ
ストフィルム、ラミナーGT(ダイナケム社製)をラミ
ネートする。焼付、現像を行いd)のように平面回路と
なるべき箇所、穴および穴周辺のパッドとなるべき箇所
を除いてレジストを形成する。レジストと基板との密着
をさらに怖くするために、紫外線露光機で10100O
/Cm  以上で蕗光を行い、160℃、90分〜15
0℃、50分の間で加熱する。さらに無電解銅めっきを
行う。無電解銅めっき液は。
Especially for small diameter drills, 20 to 50
The value is μm/r ev. Next, a catalyst for electroless copper plating MS-201B (manufactured by Hitachi Chemical KK) is applied to the entire hole, and the entire surface is polished. Further surface treatment is performed and a solvent-developed photoresist film is laminated. As for surface treatment, first apply 3 to 6 abrasive particles of 20 to 40 ttm
Spray onto the substrate surface with a pump pressure of kg/aII+, ? ′
Then, treat with alkaline degreasing solution HCR-201 (manufactured by Hitachi Chemical KK) or benzotriazole solution (manufactured by Wako Tsumugi KK). At this time, the effect of treatment with both solutions becomes stronger. Further, the substrate is heated to 100 to 120° C., and a resist film and Laminar GT (manufactured by Dynachem) are laminated thereon. Baking and development are performed to form a resist except for the areas that should become planar circuits, the holes, and the areas around the holes that should become pads, as shown in d). In order to make the adhesion between the resist and the substrate even worse, we used an ultraviolet exposure machine to
/Cm or more, 160℃, 90 minutes to 15 minutes.
Heat at 0°C for 50 minutes. Furthermore, electroless copper plating is performed. Electroless copper plating solution.

通常のもの例えば銅イオン0.ill[14−0,2m
a7I/I、銅イオンの錯化剤0.004〜1 mo 
ill、還元剤0.01〜0.25 mol/l  及
びPH11,8〜155とするに必要な…調製剤を基本
組成とするものを使用する。めっき析出速度2.2zz
m/h、以上の高活性で、平面回路となるべき箇所。
Normal ones such as copper ion 0. ill[14-0,2m
a7I/I, copper ion complexing agent 0.004-1 mo
Ill, reducing agent 0.01 to 0.25 mol/l, and a preparation agent necessary to adjust the pH to 11.8 to 155 are used as the basic composition. Plating deposition rate 2.2zz
m/h or more, and should be a planar circuit with high activity.

穴および穴周辺のパッドとなるべき箇所にめっきを析出
させる(第1図e))。さらに銅析出部分にはんだ等の
エツチングレジスト全付与して、めっきレジスl−Th
 ill mLエッチングケ行う。次いでソルダレジス
ト全印刷する。
Plating is deposited on the hole and the area around the hole that will become the pad (Fig. 1e)). Furthermore, an etching resist such as solder is completely applied to the copper deposited area, and a plating resist L-Th is applied.
Perform ill mL etching. Next, the entire solder resist is printed.

また、一般鋼箔(18,、35,70tim )を用い
た銅張り積層板の代りに極薄鮪1箔(5,8μm)銅張
り槓層枦牙用いると、クイックエツチングにより回路形
成が可能である。
Also, if you use an ultra-thin copper foil (5.8 μm) copper-clad laminate layer instead of a copper-clad laminate made of general steel foil (18, 35, 70 tim), it is possible to form a circuit by quick etching. be.

(発明の効果) 以上説明した本発明の印刷配糾鈑の製造方法については
、次の効果がw4者である。
(Effects of the Invention) The method for manufacturing a printed board of the present invention described above has the following effects.

(1)餉張り積層棲の銅箔(例えば18..55゜70
μmまたは5.8μm)のみエツチングして回路形fy
、を行うため、銅張り積層板の銅箔の上VC電気銅ぬっ
き全行いエツチングを行う従来方法に比べ、エツチング
積度が極めて良く回路を精度良く形成することができる
(1) Glazed laminated copper foil (e.g. 18.55°70
μm or 5.8 μm) is etched to form the circuit fy.
Compared to the conventional method in which VC electrolytic copper plating is performed on the copper foil of a copper-clad laminate and then etching is performed, the etching density is extremely high and circuits can be formed with high precision.

(2)穴内35μm程度の厚みを無電解鋼めっきのみで
行うため、電気銅めっきでは穴;りのめっき厚が薄くな
ってしまうようなアスペクト比の大きい小径穴でも10
0%のつきまわり性が得らする。
(2) Electroless steel plating is applied only to a thickness of about 35 μm inside the hole, so even small diameter holes with a large aspect ratio, where electrolytic copper plating would result in a thinner plating thickness,
Achieves 0% throwing power.

(3)平面部の回路は、餉張り積層板の銅箔であるため
に細密パターンでも基板と強いビールが得らt高密度化
が可能である。
(3) Since the circuit on the plane part is made of copper foil of a glazed laminated board, it is possible to obtain a substrate and a strong beer even with a fine pattern, and to achieve high density.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による工程の例を示し、第2図は従来の
方法であるテンティング法を、第6図は従来の方法であ
るはんだ法の工程でテンティング法と異なる工程を、第
4図は従来の方法である部分アディティブ法の工程を、
第5図は従来の方法であるフルアディティブ法の工8を
示す。 符号の説明
Figure 1 shows an example of the process according to the present invention, Figure 2 shows the conventional method of tenting, and Figure 6 shows the conventional soldering process, which is different from the tenting method. Figure 4 shows the process of the conventional partial additive method.
FIG. 5 shows Step 8 of the conventional fully additive method. Explanation of symbols

Claims (1)

【特許請求の範囲】[Claims] 1、フォトレジストラミネート工程の前に、基板表面銅
箔に砥粒を高圧で吹きつけることによって粗面化し、基
板表面をアルカリ脱脂溶液および/またはトリアゾール
基を含んだ有機化合物溶液に浸漬し、次いでフォトレジ
ストラミネート、露光、現像後さらに紫外線露光および
加熱を行うことを特徴とする印刷配線板の製造方法。
1. Before the photoresist lamination process, the copper foil on the substrate surface is roughened by spraying abrasive grains at high pressure, the substrate surface is immersed in an alkaline degreasing solution and/or an organic compound solution containing a triazole group, and then A method for manufacturing a printed wiring board, which comprises further performing ultraviolet exposure and heating after photoresist lamination, exposure, and development.
JP28670085A 1985-12-19 1985-12-19 Method for manufacturing printed wiring board Expired - Lifetime JPH0654832B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28670085A JPH0654832B2 (en) 1985-12-19 1985-12-19 Method for manufacturing printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28670085A JPH0654832B2 (en) 1985-12-19 1985-12-19 Method for manufacturing printed wiring board

Publications (2)

Publication Number Publication Date
JPS62145796A true JPS62145796A (en) 1987-06-29
JPH0654832B2 JPH0654832B2 (en) 1994-07-20

Family

ID=17707851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28670085A Expired - Lifetime JPH0654832B2 (en) 1985-12-19 1985-12-19 Method for manufacturing printed wiring board

Country Status (1)

Country Link
JP (1) JPH0654832B2 (en)

Also Published As

Publication number Publication date
JPH0654832B2 (en) 1994-07-20

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