JPS5877292A - Method of producing printed circuit board - Google Patents

Method of producing printed circuit board

Info

Publication number
JPS5877292A
JPS5877292A JP17609181A JP17609181A JPS5877292A JP S5877292 A JPS5877292 A JP S5877292A JP 17609181 A JP17609181 A JP 17609181A JP 17609181 A JP17609181 A JP 17609181A JP S5877292 A JPS5877292 A JP S5877292A
Authority
JP
Japan
Prior art keywords
plating
circuit board
printed circuit
printed
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17609181A
Other languages
Japanese (ja)
Other versions
JPH0137877B2 (en
Inventor
瑛一 綱島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17609181A priority Critical patent/JPS5877292A/en
Publication of JPS5877292A publication Critical patent/JPS5877292A/en
Publication of JPH0137877B2 publication Critical patent/JPH0137877B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は両面に所定形状の導体回路網を有し。[Detailed description of the invention] The present invention has a conductor network of a predetermined shape on both sides.

これら導体回路網をスルーホール導体路でもって電気的
に接続した印刷配線板の製造方法に関するものであり、
その目的とするところは上記導体回路網に対する用途の
異なるめっき層を効率よく形状することができる印刷配
線板の製造Jj fJ<を提供することにある。
The present invention relates to a method for manufacturing a printed wiring board in which these conductor circuit networks are electrically connected by through-hole conductor paths,
The purpose is to provide a method for manufacturing printed wiring boards that can efficiently form plating layers for different uses for the conductor network.

一般に、キーボードのスイッチ回路とその周辺回路を1
枚の印刷配線板に集約に設ける場合には、印刷配線板と
して両面に所定形状の導体回路網を有し、これら導体回
路網をスルーホール導体路でもって電気的に接続した両
面印刷配線板が使用される。そして、両面印刷配線板は
キーボードのスイッチ回路のた°めの導体回路網に対し
ては接点めっきとしての金めつきが、捷だ、スルーホー
ル導体路としての銅めっきが施されることが多ν1.シ
かしながら、上述した両面印刷配線板への異なるめっき
処理は、金めつきの形成予定箇所に剥離紙等を設けた状
態で池のすべてにめっきレジスト11りを設けた後に剥
離紙を除去して金めつきの形成予定箇所を露出させて金
のめっき処理を行ない、その後、上記めっきレジスト膜
を除去した後に金めつきの形成面をめっきレジスト膜で
覆って銅のめっき処理を行ない、最後に上記金め−2き
の形成向上のめっきレジスト膜を除去しなければならな
い関係で、すでに形成されている導体回路網に対[7て
も銅のめっき層が設けられることになり、心安以外に銅
のめっき層が形成されてしまうという問題があった。そ
こで、すでに形成されている導体回路網の必要箇所のみ
に銅のめっき層を形成しようとすると、めっきレジスト
膜の選択的な塗布をしなければならず、特にスルーホー
ル導体路の形成箇所と非形成箇所が混在する場合にはめ
っき処理が非常に面倒になるという問題があった。
Generally, the keyboard switch circuit and its peripheral circuits are
When integrated into a single printed wiring board, a double-sided printed wiring board is used, which has conductor networks of a predetermined shape on both sides of the printed wiring board and electrically connects these conductor networks with through-hole conductor paths. used. On double-sided printed wiring boards, the conductor circuit network for the switch circuit of the keyboard is often gold-plated as a contact plating, but copper plating is often applied as a through-hole conductor path. ν1. However, the different plating processes for double-sided printed circuit boards mentioned above are performed by placing a release paper, etc. in the areas where gold plating is to be formed, and then removing the release paper after applying a plating resist 11 to all of the ponds. Then, after removing the above-mentioned plating resist film, the surface on which the gold plating is to be formed is covered with a plating resist film, and then copper plating is performed, and finally the above-mentioned Since the plating resist film that improves the formation of gold plating must be removed, a copper plating layer will be provided on the conductor circuit network that has already been formed. There was a problem that a plating layer was formed. Therefore, if you try to form a copper plating layer only on the necessary parts of the conductor network that has already been formed, you will have to selectively apply the plating resist film, especially where the through-hole conductor path will be formed and where it will not be applied. When the formation locations are mixed, there is a problem in that the plating process becomes extremely troublesome.

本発明はこのような従来め欠点を解消するものであり、
基板本体の表面と透孔とに同時にめっきレジストの選択
的な印刷処理を行なうことにより、用途の異なるめっき
層を効率よく形成することができるようにしたものであ
る。
The present invention solves these conventional drawbacks,
By selectively printing plating resist on the surface of the substrate body and the through holes at the same time, plating layers for different uses can be efficiently formed.

以下、本発明の実施例について説明する。Examples of the present invention will be described below.

実施例 まず、第1図に示すように両面に所定形状の導体回路網
としての導体層(銅箔)1.2が設けられ、所定置所に
透子t3が設けられたガラス布基材エポキシ樹脂積層板
よりなるプリント基板4を用意した。次に、第2図に示
すように上記プリント基板4の一方の導体回路網として
の導体層1が設けられた而にマスク孔6と段付きマスク
孔6を備えるメタルマスク7を配置して、めっきレジス
ト8をスクリーン印刷の手法で印刷した。この時、上記
めっきレジスト8としてナラブーツ1:製のビニル系樹
脂ペイント206Bをブチルカルピトール溶剤にて粘度
20,0OOOPS K調整して用いた。
Example First, as shown in FIG. 1, a glass cloth base material epoxy resin is provided with a conductor layer (copper foil) 1.2 as a conductor network of a predetermined shape on both sides and a translucent T3 at a predetermined position. A printed circuit board 4 made of a laminated board was prepared. Next, as shown in FIG. 2, a metal mask 7 having a mask hole 6 and a stepped mask hole 6 is placed on one of the printed circuit boards 4 on which the conductor layer 1 is provided as a conductor circuit network. Plating resist 8 was printed using a screen printing method. At this time, as the plating resist 8, vinyl resin paint 206B manufactured by Nara Boots 1 was used after adjusting the viscosity to 20.0OOOPSK with a butyl carpitol solvent.

このスクリーン印刷により、第2図に示すようにスルー
ホール導体路の非形成箇所に相当する透孔2の孔壁およ
びその孔周りの導体層1に対してめっきレジスト8の立
体的な印刷を選択的に行なうと同時に金めつきの形成予
定箇所に相当する導体層1に対してめっきレジスト8の
平面的な印11111を選択的に行なった。次に、上記
プリント基板4’i反転し、その他方の導体回路網とし
ての導体層2が設けられた面に第3図に示すようにマス
ク孔9と段付きマスク孔1oを備えるメタルマスク11
を配置して、めっきレジスト8をスクリーン印刷の手法
で印刷した。このスクリーン印刷により、第3図に示す
ようにスルーホール導体路の非形成箇所に相当する透孔
2の孔壁およびその孔周りの導体層2に対してめっきレ
ジスト8の)“1体的な印刷を選択的に行なうと同時に
銅めっきの非形成箇所に相当する導体層2に対してめっ
きレジ子ト8の平面的な印刷を選択的に行なった。次に
1.上記プリント基板4は電気炉中に入れて120°C
910分の条件でめっきレジスト8の印刷層を硬化した
のちにめっきの活性化処理を行ない、その後公知の銅の
めっき溶液中に浸漬して第4図に示すようにめっきレジ
スト8の印刷層の未形成箇所に相当する透孔2の孔壁お
よびその孔周りの導体層1.2に対してはとめ状に銅の
めっき唇12、を形成すると同時に、めっきレジスト8
の印1itl1層の未形成箇所に相当する導体層2に銅
のめっき層12を設けた。そして、このめっき処理の後
に上記プリント基板4は2%のアルカリ溶液中に浸して
上記めっきレジスト8の印刷層を剥離した。このように
して銅のめっき層12を形成する第1のめつき処理工程
を終了する。次に、第5図に示すように上記プリント基
板4の一方の導体回路網としての導体層1が設けられた
而にマスク孔13と段付きマスク孔14を備えるメタル
マスク15を配置して、めっきレジスト8をスクリーン
印刷の手法で印刷した。このスクリーン印刷により、第
5図に示すようにスルーホール導体路の非形成箇所に相
当する透孔2の孔壁およびその孔周りの導体層1、スル
ーホール導体路としての銅のめっき層12が設けられた
透孔2の孔壁およびその孔周りの銅めっき層12のそれ
ぞれに対してめっきレジスト8の立体的な印刷を行なう
と同時に金めつきの形成予定箇所に相当する導体層1を
残して他のすべて導体層1に対してめっきレジスト80
乎+rri的な印刷を選択的に行なった。次に、上記プ
リント基板4を反転し、その他方の導体回路網とし7て
の導体層2が設けられだ面に第6図に示すようにマスク
孔16と段付きマスク孔17を備えるメタルマスク18
を配置して、めっきレジスト8をスクリーン印刷の手法
で印■りした。このスクリーン印刷により、第6図に示
すようにスルーホール10体路の非形成箇所に相当する
透孔2の孔壁および□その孔周りの導体層2.スルーホ
ール導体路としての銅のめっき層12が設けられた透孔
2の孔壁およびその孔周りの銅めっき層12のそれぞれ
に対してめっきレジスト8の立体的な印刷を行なうと同
時に他のすべての導体層2に対してめっきレジスト8の
平面的な印刷を行なった。次に、上記プリント基板4は
電気炉中に入れて120°C9−10分の条件でめっき
レジスト8の印刷層を硬化したのちめっきの活性化処理
を行ない、その後、公知の金のめっき溶液中に浸漬して
第7図に示すようにめっきレジスト8の印刷層の未形成
部分に相当する導体層1に金のめっき層19を設けた。
Through this screen printing, three-dimensional printing of the plating resist 8 is selected on the hole wall of the through hole 2 and the conductor layer 1 around the hole, which corresponds to the area where the through-hole conductor path is not formed, as shown in FIG. At the same time, planar markings 11111 of the plating resist 8 were selectively made on the conductor layer 1 corresponding to the locations where the gold plating was to be formed. Next, the printed circuit board 4'i is inverted, and a metal mask 11 having mask holes 9 and stepped mask holes 1o as shown in FIG.
was placed, and a plating resist 8 was printed using a screen printing method. By this screen printing, as shown in FIG. At the same time as printing was selectively performed, plating resist 8 was selectively printed on a plane on the conductor layer 2 corresponding to the areas where copper plating was not formed.Next, 1. The printed circuit board 4 was Put it in the oven and heat it to 120°C
After curing the printed layer of the plating resist 8 for 910 minutes, the plating is activated, and then immersed in a known copper plating solution to harden the printed layer of the plating resist 8 as shown in FIG. At the same time, a copper plating lip 12 is formed in a grommet shape on the hole wall of the through hole 2 corresponding to the unformed area and the conductor layer 1.2 around the hole, and at the same time, a plating resist 8 is formed.
A copper plating layer 12 was provided on the conductor layer 2 corresponding to the portion where the mark 1itl1 layer was not formed. After this plating treatment, the printed circuit board 4 was immersed in a 2% alkaline solution to peel off the printed layer of the plating resist 8. In this way, the first plating process for forming the copper plating layer 12 is completed. Next, as shown in FIG. 5, a metal mask 15 having a mask hole 13 and a stepped mask hole 14 is placed on one of the printed circuit boards 4 on which the conductor layer 1 is provided as a conductor circuit network. Plating resist 8 was printed using a screen printing method. By this screen printing, as shown in FIG. 5, the hole wall of the through hole 2 corresponding to the area where the through hole conductor path is not formed, the conductor layer 1 around the hole, and the copper plating layer 12 as the through hole conductor path are formed. A three-dimensional plating resist 8 is printed on each of the hole wall of the provided through hole 2 and the copper plating layer 12 around the hole, while at the same time leaving the conductor layer 1 corresponding to the area where the gold plating is planned to be formed. Plating resist 80 for all other conductor layers 1
乎+rri-like printing was performed selectively. Next, the printed circuit board 4 is turned over, and a metal mask having mask holes 16 and stepped mask holes 17 as shown in FIG. 18
was placed, and a plating resist 8 was printed using a screen printing method. By this screen printing, as shown in FIG. 6, the hole wall of the through hole 2 corresponding to the non-forming part of the through hole 10 and the conductor layer 2 around the hole. Three-dimensional printing of the plating resist 8 is performed on each of the hole wall of the through hole 2 provided with the copper plating layer 12 as a through-hole conductor path and the copper plating layer 12 around the hole, and at the same time, all other A plating resist 8 was printed flat on the conductor layer 2. Next, the printed circuit board 4 is placed in an electric furnace and the printed layer of the plating resist 8 is cured at 120°C for 9-10 minutes, and then the plating is activated, and then placed in a known gold plating solution. As shown in FIG. 7, a gold plating layer 19 was provided on the conductor layer 1 corresponding to the portion where the printed layer of the plating resist 8 was not formed.

そして、このめっき処理の後に上記プリント基板4は2
%のアルカリ溶液中に浸して上記めっきレジスト8の印
刷層を剥離した。このようにして金のめっき層19を形
成する第2のめっき処理工程を終了する。
After this plating process, the printed circuit board 4 is
% alkaline solution to peel off the printed layer of the plating resist 8. In this way, the second plating process for forming the gold plating layer 19 is completed.

尚、上記の実施例では第1のめっき処理工程の終りにめ
っきレジスト8の印刷層をすべて除去したが、これは金
のめっき層の形成予定部分に相当する導体層1のめっき
レジストの印刷層のみを除去し、第2のめっき処理工程
で上記金めっき層の形成予定部分に相当する導体層1を
残して他に残存する部分のすべてをめっきレジスト8の
印刷層でおおうようにしてもよい。
In the above example, the entire printed layer of the plating resist 8 was removed at the end of the first plating process, but this was because the printed layer of the plating resist of the conductor layer 1 corresponding to the portion where the gold plating layer was to be formed was removed. In the second plating process, only the conductor layer 1 corresponding to the area where the gold plating layer is planned to be formed is left, and all other remaining areas are covered with a printed layer of the plating resist 8. .

又、第1.第2のめっき処理工程は順序を入れかえて金
めつきの処理の後に銅めっきの処理を行なうようにして
もよいものである。
Also, 1st. The order of the second plating process may be changed so that the copper plating process is performed after the gold plating process.

以上のように本発明によれば、両面印M11配線板の表
面と透孔に対して同時にめっきレジストを印刷するよう
にしたので、上記めっきレジストの印刷層を選択的に設
けることができ、命めっきと銅めっきを必要箇所にのみ
選択的に喚宜形成することができ、経済的にめっき処理
を行なうことができる。丑だ、スルーホール導体路の形
成部分と未形成部分が混在する場合′でもめっきレジス
トの印刷層を選択的に簡単に形成することができるので
As described above, according to the present invention, the plating resist is printed simultaneously on the surface of the double-sided M11 wiring board and the through hole, so the printed layer of the plating resist can be selectively provided, and Plating and copper plating can be selectively formed only on necessary locations, and plating can be performed economically. This is advantageous because even if there are areas where through-hole conductor paths are formed and areas where they are not formed, a printed layer of plating resist can be selectively and easily formed.

めっき処理工程を煩雑にすることなく、必要箇所にのみ
異なるめっき層を設けることができる利点を有するもの
である。
This has the advantage that different plating layers can be provided only at necessary locations without complicating the plating process.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の印刷配線板の製造Jj法の一実施例を示
し、第1図は出発材としての両面プリント基板の断面図
、第2図および第3図は銅めっきのためのめっきレジス
トの印刷工程の、1G)四国、第4図は銅めっきおよび
レジスト除去工程の説明図、第5図および第6図は金め
つきのだめのめっきレジストの印刷工程の説明図、第7
図は金めつきおよびレジスト除去工程の説明図である。 1.2・・・・・・導体層、3・・・・・・透孔、4・
・・・・・プリント基板%5,9,13.16・・・・
・・マスク孔、6゜1.0,14.17・・・・・・段
付きマスク孔、7 、11゜15.18・・・・・・メ
タルマスク、8・・・・・・めっきレジスト、12・・
・・・・銅めっき、19・・・・・・金めつき。 代理人の氏名 弁理士 中 尾 赦 男 ほか1名第1
図 第2図 第3図 第4図 第5図 第6図 第7図
The drawings show an embodiment of the Jj method for manufacturing printed wiring boards of the present invention, in which FIG. 1 is a cross-sectional view of a double-sided printed circuit board as a starting material, and FIGS. 2 and 3 are cross-sectional views of a plating resist for copper plating. Printing process, 1G) Shikoku, Figure 4 is an explanatory diagram of the copper plating and resist removal process, Figures 5 and 6 are explanatory diagrams of the printing process of the plating resist for gold plating, and Figure 7
The figure is an explanatory diagram of the gold plating and resist removal process. 1.2...Conductor layer, 3...Through hole, 4.
...Printed circuit board%5,9,13.16...
...Mask hole, 6゜1.0, 14.17...Stepped mask hole, 7, 11゜15.18...Metal mask, 8...Plating resist , 12...
...Copper plating, 19...Gold plating. Name of agent: Patent attorney Masao Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

【特許請求の範囲】[Claims] 両面に所定形状の導体回路網を有すると共にその所定筒
所に複数の透孔を有するプリント基板を有し、このプリ
ント基板の一方の導体回路網の所定箇所および上記透孔
の所定箇所にめっきレジストを同時に選択的に印刷する
と共に[−記プリント基板の他方の導体回路の所定箇所
および1−配送孔の所定箇所にめっきレジストを同時に
選択的に印刷し、上記めっきレジストを硬化したのちに
第1のめっき溶液中で第1の金属めっき層を析出さtム
る第1のめっき処理工程と、上記プリント基板の一方の
導体回路網の所定箇所および上記すべての透孔に対して
めっきレジストを同時に選択的に印刷すると共に上記プ
リント基板の他方・の導体回路の所定箇所および上記す
べての透孔に対してめっきレジストを同時に選択的に印
刷し、上記めっきレジストを硬化したのちに上記第1の
めっき溶液とは異なる第2のめっき溶液中で第2の金属
めっき層を析出させる第2のめっき処理工程を備え、−
上記第1.第2のめっき処理により上記プリント基板の
異なる部分に異なる金−めっき層を析出させることを特
徴とする印刷配線板の製造方法。
It has a printed circuit board having a conductive circuit network of a predetermined shape on both sides and a plurality of through holes in a predetermined position of the printed circuit board, and a plating resist is applied to a predetermined location of one of the conductor circuit networks and a predetermined location of the through holes of the printed circuit board. At the same time, a plating resist is simultaneously selectively printed at a predetermined location of the other conductor circuit of the printed circuit board and a predetermined location of the delivery hole, and after the plating resist is cured, the first A first plating process in which a first metal plating layer is deposited in a plating solution, and a plating resist is simultaneously applied to predetermined locations of one conductor network of the printed circuit board and all of the through holes. At the same time, a plating resist is selectively printed on predetermined portions of the conductor circuit on the other side of the printed circuit board and all of the through holes, and after the plating resist is cured, the first plating is applied. a second plating process step of depositing a second metal plating layer in a second plating solution different from the solution;
Above 1st. A method for manufacturing a printed wiring board, characterized in that a second plating process deposits different gold plating layers on different parts of the printed circuit board.
JP17609181A 1981-11-02 1981-11-02 Method of producing printed circuit board Granted JPS5877292A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17609181A JPS5877292A (en) 1981-11-02 1981-11-02 Method of producing printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17609181A JPS5877292A (en) 1981-11-02 1981-11-02 Method of producing printed circuit board

Publications (2)

Publication Number Publication Date
JPS5877292A true JPS5877292A (en) 1983-05-10
JPH0137877B2 JPH0137877B2 (en) 1989-08-09

Family

ID=16007542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17609181A Granted JPS5877292A (en) 1981-11-02 1981-11-02 Method of producing printed circuit board

Country Status (1)

Country Link
JP (1) JPS5877292A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01124295A (en) * 1987-11-09 1989-05-17 Fujitsu Ltd Formation of component-mounting hole in printed-circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01124295A (en) * 1987-11-09 1989-05-17 Fujitsu Ltd Formation of component-mounting hole in printed-circuit board

Also Published As

Publication number Publication date
JPH0137877B2 (en) 1989-08-09

Similar Documents

Publication Publication Date Title
US4770900A (en) Process and laminate for the manufacture of through-hole plated electric printed-circuit boards
US2965952A (en) Method for manufacturing etched circuitry
US3060076A (en) Method of making bases for printed electric circuits
JPS5877292A (en) Method of producing printed circuit board
JPH09307216A (en) Manufacture of wiring board, and wiring board
JPS58134497A (en) Method of producing printed circuit board and printed circuit board
JPH0779191B2 (en) Manufacturing method of three-dimensional wiring board
JP2566424B2 (en) Conductive circuit transfer foil and manufacturing method thereof
JPH10335779A (en) Formation of pattern
JPS61102093A (en) Manufacture of printed circuit board
JPH10284814A (en) Circuit pattern and its formation
JPS588600B2 (en) Ryomen Print High Senban no Seizouhouhou
JPS648478B2 (en)
JPS5877287A (en) Method of producing printed circuit board
JPS5828890A (en) Electric wiring circuit board and method of producing same
JPS6372189A (en) Manufacture of circuit board
JP2522968B2 (en) Printed circuit transfer foil and manufacturing method thereof
JPS61147595A (en) Manufacture of double side printed wiring board
JPS6235595A (en) Manufacture of transfer sheet
JPS59121895A (en) Method of producing printed circuit board
JPH04360596A (en) Manufacture of circuit board
JPS58121698A (en) Multilayer printed board
JPH05259609A (en) Manufacture of printed wiring board
JPH0821776B2 (en) Double-sided circuit board manufacturing method
JPS6387787A (en) Manufacture of printed wiring board