JPH0137877B2 - - Google Patents

Info

Publication number
JPH0137877B2
JPH0137877B2 JP17609181A JP17609181A JPH0137877B2 JP H0137877 B2 JPH0137877 B2 JP H0137877B2 JP 17609181 A JP17609181 A JP 17609181A JP 17609181 A JP17609181 A JP 17609181A JP H0137877 B2 JPH0137877 B2 JP H0137877B2
Authority
JP
Japan
Prior art keywords
plating
printed
hole
conductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP17609181A
Other languages
Japanese (ja)
Other versions
JPS5877292A (en
Inventor
Eiichi Tsunashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17609181A priority Critical patent/JPS5877292A/en
Publication of JPS5877292A publication Critical patent/JPS5877292A/en
Publication of JPH0137877B2 publication Critical patent/JPH0137877B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

【発明の詳細な説明】 本発明は両面に所定形状の導体回路網を有し、
これら導体回路網をスルーホール導体略でもつて
電気的に接続した印刷配線板の製造方法に関する
ものであり、その目的とするところは上記導体回
路網に対する用途の異なるめつき層を効率よく形
成することができる印刷配線板の製造方法を提供
することにある。
DETAILED DESCRIPTION OF THE INVENTION The present invention has a conductor network of a predetermined shape on both sides,
The present invention relates to a method for manufacturing a printed wiring board in which these conductor networks are electrically connected by through-hole conductors, and its purpose is to efficiently form plated layers for different uses on the conductor network. An object of the present invention is to provide a method for manufacturing a printed wiring board that allows for the production of printed wiring boards.

一般に、キーボードのスイツチ回路とその周辺
回路を1枚の印刷配線板に集約に設ける場合に
は、印刷配線板として両面に所定形状の導体回路
網を有し、これら導体回路網をスルーホール導体
路でもつて電気的に接続した両面印刷配線板が使
用される。そして、両面印刷配線板はキーボード
のスイツチ回路のための導体回路網に対しては接
点めつきとしての金めつきが、また、スルーホー
ル導体路としての銅めつきが施されることが多
い。しかしながら、上述した両面印刷配線板への
異なるめつき処理は、金めつきの形成予定箇所に
剥離紙等を設けた状態で他のすべてにめつきレジ
スト膜を設けた後に剥離紙を除去して金めつきの
形成予定箇所を露出させて金のめつき処理を行な
い、その後、上記めつきレジスト膜を除去した後
に金めつきの形成面をめつきレジスト膜で覆つて
銅のめつき処理を行ない、最後に上記金めつきの
形成面上のめつきレジスト膜を除去しなければな
らない関係で、すでに形成されている導体回路網
に対しても銅のめつき層が設けられることにな
り、必要以外に銅のめつき層が形成されてしまう
という問題があつた。そこで、すでに形成されて
いる導体回路網の必要箇所のみに銅のめつき層を
形成しようとすると、めつきレジスト膜の選択的
な塗布をしなければならず、特にスルーホール導
体路の形成箇所と非形成箇所が混在する場合には
めつき処理が非常に面倒になるという問題があつ
た。
Generally, when a keyboard switch circuit and its peripheral circuits are integrated on a single printed wiring board, the printed wiring board has conductor networks of a predetermined shape on both sides, and these conductor networks are connected to through-hole conductor circuits. A double-sided printed wiring board with electrical connections is used. In double-sided printed wiring boards, the conductor circuit network for the switch circuit of the keyboard is often plated with gold as a contact plating, and also with copper plating as a through-hole conductor path. However, the above-mentioned different plating process for double-sided printed wiring boards involves providing a release paper, etc. in the area where the gold plating is to be formed, and then applying a plating resist film to all other areas, then removing the release paper, and then applying the gold plate. The area where plating is to be formed is exposed and subjected to gold plating, and then, after removing the plating resist film, the surface on which the gold plating is to be formed is covered with a plating resist film and copper plating is performed, and finally Since the plating resist film on the surface on which the gold plating is formed must be removed, a copper plating layer is also provided on the conductor network that has already been formed, There was a problem that a glazed layer was formed. Therefore, if you try to form a copper plating layer only on the necessary parts of the already formed conductor network, you will have to selectively apply a plating resist film, especially on the parts where through-hole conductor paths will be formed. There was a problem that the plating process became extremely troublesome when there were both non-formed parts.

本発明はこのような従来の欠点を解消するもの
であり、基板本体の表面と透孔とに同時にめつき
レジストの選択的な印刷処理を行なうことによ
り、用途の異なるめつき層を効率よく形成するこ
とができるようにしたものである。
The present invention solves these conventional drawbacks and efficiently forms plating layers for different uses by selectively printing plating resist on the surface of the substrate body and the through holes at the same time. It was made so that it could be done.

以下、本発明の実施例について説明する。 Examples of the present invention will be described below.

実施例 まず、第1図に示すように両面に所定形状の導
体回路網としての導体層(銅箔)1,2が設けら
れ、所定箇所に透孔3が設けられたガラス布基材
エポキシ樹脂積層板よりなるプリント基板4を用
意した。次に、第2図に示すように上記プリント
基板4の一方の導体回路網としての導体層1が設
けられた面にマスク孔5と段付きマスク孔6を備
えるメタルマスク7を配置して、めつきレジスト
8をスクリーン印刷の手法で印刷した。この時、
上記めつきレジスト8としてナツダー社製のビニ
ル系樹脂ペイント205Bをブチルカルビトール溶
剤にて粘度20000CPSに調整して用いた。このス
クリーン印刷により、第2図に示すようにスルホ
ール導体路の非形成箇所に相当する透孔2の孔壁
およびその孔周りの導体層1に対してめつきレジ
スト8の立体的な印刷を選択的に行なうと同時に
金めつきの形成予定箇所に相当する導体層1に対
してめつきレジスト8の平面的な印刷を選択的に
行なつた。次に、上記プリント基板4を反転し、
その他方の導体回路網としての導体層2が設けら
れた面に第3図に示すようにマスク孔9と段付き
マスク孔10を備えるメタルマスク11を配置し
て、めつきレジスト8をスクリーン印刷の手法で
印刷した。このスクリーン印刷により、第3図に
示すようにスルホール導体路の非形成箇所に相当
する透孔2の孔壁および孔周りの導体層2に対し
てめつきレジスト8の立体的な印刷を選択的に行
なうと同時に銅めつきの非形成箇所に相当する導
体層2に対してめつきレジスト8の平面的な印刷
を選択的に行なつた。次に、上記プリント基板4
は電気炉中に入れて120℃、10分の条件でめつき
レジスト8の印刷層を硬化したのちにめつきの活
性化処理を行ない、その後公知の銅のめつき溶液
中に浸漬して第4図に示すようにめつきレジスト
8の印刷層の未形成箇所に相当する透孔2の孔壁
およびその孔周りの導体層1,2に対してはとめ
状に銅のめつき層12を形成すると同時に、めつ
きレジスト8の印刷層の未形成箇所に相当する導
体層2に銅のめつき層12を設けた。そして、こ
のめつき処理の後に上記プリント基板4は2%の
アルカリ溶液中に浸して上記めつきレジスト8の
印刷層を剥離した。このようにして銅のめつき層
12を形成する第1のめつき処理工程を終了す
る。次に、第5図に示すように上記プリント基板
4の一方の導体回路網としての導体層1が設けら
れた面にマスク孔13と段付きマスク孔14を備
えるメタルマスク15を配置して、めつきレジス
ト8をスクリーン印刷の手法で印刷した。このス
クリーン印刷により、第5図に示すようにスルー
ホール導体路の非形成箇所に相当する透孔2の孔
壁およびその孔周りの導体層1、スルーホール導
体路としての銅のめつき層12が設けられた透孔
2の孔壁およびその孔周りの銅めつき層12のそ
れぞれに対してめつきレジスト8の立体的な印刷
を行なうと同時に金めつきの形成予定箇所に相当
する導体層1を残して他のすべて導体層1に対し
てめつきレジスト8の平面的な印刷を選択的に行
なつた。次に、上記プリント基板4を反転し、そ
の他方の導体回路網としての導体層2が設けられ
た面に第6図に示すようにマスク孔16と段付き
マスク孔17を備えるメタルマスク18を配置し
て、めつきレジスト8をスクリーン印刷の手法で
印刷した。このスクリーン印刷により、第6図に
示すようにスルーホール導体路の非形成箇所に相
当する透孔2の孔壁およびその孔周りの導体層
2、スルーホール導体路としての銅のめつき層1
2が設けられた透孔2の孔壁およびその孔周りの
銅めつき層12のそれぞれに対してめつきレジス
ト8の立体的な印刷を行なうと同時に他のすべて
の導体層2に対してめつきレジスト8の平面的な
印刷を行なつた。次に、上記プリント基板4は電
気炉中に入れて120℃、10分の条件でめつきレジ
スト8の印刷層を硬化したのちめつきの活性化処
理を行ない、その後、公知の金のめつき溶液中に
浸漬して第7図に示すようにめつきレジスト8の
印刷層の未形成部分に相当する導体層1に金のめ
つき層19を設けた。そして、このめつき処理の
後に上記プリント基板4は2%のアルカリ溶液中
に浸して上記めつきレジスト8の印刷層を剥離し
た。このようにして金のめつき層19を形成する
第2のめつき処理工程を終了する。
Example First, as shown in FIG. 1, conductor layers (copper foil) 1 and 2 as a conductor network of a predetermined shape are provided on both sides, and through holes 3 are provided at predetermined locations.A glass cloth base epoxy resin is prepared. A printed circuit board 4 made of a laminated board was prepared. Next, as shown in FIG. 2, a metal mask 7 having a mask hole 5 and a stepped mask hole 6 is placed on the surface of the printed circuit board 4 on which the conductor layer 1 as one conductor circuit network is provided. Plating resist 8 was printed using a screen printing method. At this time,
As the plating resist 8, vinyl resin paint 205B manufactured by Nazda Corp. was used after adjusting the viscosity to 20,000 CPS with a butyl carbitol solvent. Through this screen printing, three-dimensional printing of the plating resist 8 is selected on the hole wall of the through hole 2 and the conductor layer 1 around the hole, which corresponds to the area where the through-hole conductor path is not formed, as shown in FIG. At the same time, a plating resist 8 was selectively printed on a plane on the conductor layer 1 corresponding to the location where the gold plating was to be formed. Next, the printed circuit board 4 is reversed,
As shown in FIG. 3, a metal mask 11 having mask holes 9 and stepped mask holes 10 is arranged on the surface on which the conductor layer 2 as the other conductor circuit network is provided, and a plating resist 8 is screen printed. Printed using the method. By this screen printing, the plating resist 8 is selectively printed three-dimensionally on the hole wall of the through hole 2 and the conductor layer 2 around the hole, which corresponds to the area where the through-hole conductor path is not formed, as shown in FIG. At the same time, plating resist 8 was selectively printed on a plane on the conductor layer 2 corresponding to the areas where copper plating was not formed. Next, the printed circuit board 4
After hardening the printed layer of the plating resist 8 in an electric furnace at 120°C for 10 minutes, a plating activation process is performed, and then the fourth layer is immersed in a known copper plating solution. As shown in the figure, a copper plating layer 12 is formed in a grommet shape on the hole wall of the through hole 2 corresponding to the area where the printed layer of the plating resist 8 is not formed and on the conductor layers 1 and 2 around the hole. At the same time, a copper plating layer 12 was provided on the conductor layer 2 corresponding to the portions of the plating resist 8 where the printed layer was not formed. After this plating treatment, the printed circuit board 4 was immersed in a 2% alkaline solution to peel off the printed layer of the plating resist 8. In this way, the first plating process for forming the copper plating layer 12 is completed. Next, as shown in FIG. 5, a metal mask 15 having a mask hole 13 and a stepped mask hole 14 is placed on the surface of the printed circuit board 4 on which the conductor layer 1 as one conductor circuit network is provided. Plating resist 8 was printed using a screen printing method. By this screen printing, as shown in FIG. 5, the hole wall of the through hole 2 corresponding to the area where the through hole conductor path is not formed, the conductor layer 1 around the hole, and the copper plating layer 12 as the through hole conductor path. The plating resist 8 is three-dimensionally printed on the hole wall of the through hole 2 provided with the through hole 2 and the copper plating layer 12 around the hole, and at the same time, the conductor layer 1 corresponding to the area where the gold plating is planned to be formed is printed. Planar printing of plating resist 8 was selectively performed on all conductor layers 1 except for . Next, the printed circuit board 4 is turned over, and a metal mask 18 having mask holes 16 and stepped mask holes 17 is placed on the other surface on which the conductor layer 2 as the conductor circuit network is provided, as shown in FIG. Then, a plating resist 8 was printed using a screen printing method. By this screen printing, as shown in FIG. 6, the hole wall of the through hole 2 corresponding to the area where the through hole conductor path is not formed, the conductor layer 2 around the hole, and the copper plating layer 1 as the through hole conductor path.
The plating resist 8 is three-dimensionally printed on the hole wall of the through hole 2 in which the conductor layer 2 is provided and the copper plating layer 12 around the hole. A flat resist 8 was printed. Next, the printed circuit board 4 is placed in an electric furnace and the printed layer of the plating resist 8 is cured at 120° C. for 10 minutes, followed by a plating activation treatment, followed by a known gold plating solution. As shown in FIG. 7, a gold plating layer 19 was provided on the conductor layer 1 corresponding to the portion where the printed layer of the plating resist 8 was not formed. After this plating treatment, the printed circuit board 4 was immersed in a 2% alkaline solution to peel off the printed layer of the plating resist 8. In this way, the second plating process for forming the gold plating layer 19 is completed.

尚、上記の実施例では第1のめつき処理工程の
終りにめつきレジスト8の印刷層をすべて除去し
たが、これは金のめつき層の形成予定部分に相当
する導体層1のめつきレジストの印刷層のみを除
去し、第2のめつき処理工程で上記金めつき層の
形成予定部分に相当する導体層1を残して他に残
存する部分のすべてをめつきレジスト8の印刷層
でおおうようにしてもよい。
In the above example, the entire printed layer of the plating resist 8 was removed at the end of the first plating process; Only the printed layer of the resist is removed, and in a second plating process, the printed layer of the resist 8 is plated, leaving only the conductor layer 1, which corresponds to the area where the gold plating layer is to be formed, and plating all remaining parts. You may also cover it with water.

又、第1、第2のめつき処理工程は順序を入れ
かえて金めつきの処理の後に銅めつきの処理を行
なうようにしてもよいものである。
Further, the order of the first and second plating processes may be reversed so that the copper plating process is performed after the gold plating process.

以上のように本発明によれば、両面印刷配線板
の表面と透孔に対して同時にめつきレジストを印
刷するようにしたので、上記めつきレジストの印
刷層を選択的に設けることができ、金めつきと銅
めつきを必要箇所にのみ選択的に適宜形成するこ
とができ、経済的にめつき処理を行なうことがで
きる。また、スルーホール導体路の形成部分と未
形成部分が混在する場合でもめつきレジストの印
刷層を選択的に簡単に形成することができるの
で、めつき処理工程を煩雑にすることなく、必要
箇所にのみ異なるめつき層を設けることができる
利点を有するものである。
As described above, according to the present invention, the plating resist is printed on the surface of the double-sided printed wiring board and the through holes at the same time, so the printed layer of the plating resist can be selectively provided. Gold plating and copper plating can be selectively and appropriately formed only at necessary locations, and the plating process can be performed economically. In addition, even when there are areas where through-hole conductor paths are formed and areas where they are not formed, it is possible to selectively and easily form a printed layer of plating resist, so the plating process does not become complicated, and the printed layer can be printed at the required locations. This has the advantage that different plating layers can be provided only on the two sides.

【図面の簡単な説明】[Brief explanation of drawings]

図面は本発明の印刷配線板の製造方法の一実施
例を示し、第1図は出発材としての両面プリント
基板の断面図、第2図および第3図は銅めつきの
ためのめつきレジストの印刷工程の説明図、第4
図は銅めつきおよびレジスト除去工程の説明図、
第5図および第6図は金めつきのためのめつきレ
ジストの印刷工程の説明図、第7図は金めつきお
よびレジスト除去工程の説明図である。 1,2……導体層、3……透孔、4……プリン
ト基板、5,9,13,16……マスク孔、6,
10,14,17……段付きマスク孔、7,1
1,15,18……メタルマスク、8……めつき
レジスト、12……銅めつき、19……金めつ
き。
The drawings show an embodiment of the method for manufacturing a printed wiring board of the present invention, in which FIG. 1 is a sectional view of a double-sided printed circuit board as a starting material, and FIGS. 2 and 3 are cross-sectional views of a plating resist for copper plating. Explanatory diagram of the printing process, 4th
The figure is an explanatory diagram of the copper plating and resist removal process,
FIGS. 5 and 6 are explanatory diagrams of the printing process of plating resist for gold plating, and FIG. 7 is an explanatory diagram of the gold plating and resist removal process. 1, 2... Conductor layer, 3... Through hole, 4... Printed circuit board, 5, 9, 13, 16... Mask hole, 6,
10, 14, 17...Stepped mask hole, 7, 1
1, 15, 18...Metal mask, 8...Plating resist, 12...Copper plating, 19...Gold plating.

Claims (1)

【特許請求の範囲】[Claims] 1 両面に所定形状の導体回路網を有すると共に
その所定箇所に複数の透孔を有するプリント基板
を有し、このプリント基板の一方の導体回路網の
所定箇所および上記透孔の孔壁を含む所定箇所に
めつきレジストを同時に選択的に印刷すると共に
上記プリント基板の他方の導体回路網の所定箇所
および上記透孔の孔壁を含む所定箇所にめつきレ
ジストを同時に選択的に印刷し、上記めつきレジ
ストを硬化したのちに第1のめつき溶液中で第1
の金属めつき層を析出させる第1のめつき処理工
程と、上記プリント基板の一方の導体回路網の所
定箇所および上記すべての透孔に対してめつきレ
ジストを同時に選択的に印刷すると共に上記プリ
ント基板の他方の導体回路の所定箇所および上記
すべての透孔に対してめつきレジストを同時に選
択的に印刷し、上記めつきレジストを硬化したの
ちに上記第1のめつき溶液とは異なる第2のめつ
き溶液中で第2の金属めつき層を析出させる第2
のめつき処理工程を備え、上記第1、第2のめつ
き処理により上記プリント基板の異なる部分に異
なる金属めつき層を析出させることを特徴とする
印刷配線板の製造方法。
1. A printed circuit board having a conductive circuit network of a predetermined shape on both sides and a plurality of through holes at predetermined locations thereof, and a predetermined portion including a predetermined location of one of the conductor circuit networks of the printed circuit board and the hole wall of the through hole. At the same time, a plating resist is selectively printed on the other conductive circuit network of the printed circuit board and at a predetermined location including the hole wall of the through hole. After curing the plating resist, a first plating resist is applied in a first plating solution.
a first plating treatment step in which a metal plating layer is deposited; a plating resist is simultaneously selectively printed on predetermined locations of one conductor network of the printed circuit board and all of the through holes; A plating resist is simultaneously selectively printed on predetermined locations of the other conductor circuit of the printed circuit board and all of the above-mentioned through holes, and after the above-mentioned plating resist is cured, a plating resist different from the first plating solution is applied. a second step of depositing a second metal plating layer in a second plating solution;
A method for manufacturing a printed wiring board, comprising a plating process, and depositing different metal plating layers on different parts of the printed circuit board by the first and second plating processes.
JP17609181A 1981-11-02 1981-11-02 Method of producing printed circuit board Granted JPS5877292A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17609181A JPS5877292A (en) 1981-11-02 1981-11-02 Method of producing printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17609181A JPS5877292A (en) 1981-11-02 1981-11-02 Method of producing printed circuit board

Publications (2)

Publication Number Publication Date
JPS5877292A JPS5877292A (en) 1983-05-10
JPH0137877B2 true JPH0137877B2 (en) 1989-08-09

Family

ID=16007542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17609181A Granted JPS5877292A (en) 1981-11-02 1981-11-02 Method of producing printed circuit board

Country Status (1)

Country Link
JP (1) JPS5877292A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01124295A (en) * 1987-11-09 1989-05-17 Fujitsu Ltd Formation of component-mounting hole in printed-circuit board

Also Published As

Publication number Publication date
JPS5877292A (en) 1983-05-10

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