JPS6318693A - Manufacture of printed circuit board - Google Patents

Manufacture of printed circuit board

Info

Publication number
JPS6318693A
JPS6318693A JP16214186A JP16214186A JPS6318693A JP S6318693 A JPS6318693 A JP S6318693A JP 16214186 A JP16214186 A JP 16214186A JP 16214186 A JP16214186 A JP 16214186A JP S6318693 A JPS6318693 A JP S6318693A
Authority
JP
Japan
Prior art keywords
metal foil
copper plating
circuit board
printed circuit
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16214186A
Other languages
Japanese (ja)
Inventor
西島 礼蔵
上野 国樹
直臣 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui Mining and Smelting Co Ltd
Original Assignee
Mitsui Mining and Smelting Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui Mining and Smelting Co Ltd filed Critical Mitsui Mining and Smelting Co Ltd
Priority to JP16214186A priority Critical patent/JPS6318693A/en
Publication of JPS6318693A publication Critical patent/JPS6318693A/en
Pending legal-status Critical Current

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  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野] 本発明は印刷回路板の製造方法に関し、詳しくは金属箔
表面上に銅メッキ層からなる回路を形成し、絶縁基材と
一体化した後、金属箔を除去する、生産性に優れ、しか
も簡便で安価な印刷回路板の製造方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a printed circuit board, and more specifically, after forming a circuit consisting of a copper plating layer on the surface of a metal foil and integrating it with an insulating base material. This invention relates to a method for manufacturing printed circuit boards that is simple and inexpensive, with excellent productivity, and in which metal foil is removed.

[従来技術1 従来、印刷回路板を製造する方法はいくつがあるが、実
用的な方法として主流を占めているのは湿式エツチング
によるサブトラクティブ法である。
[Prior Art 1] Conventionally, there are a number of methods for manufacturing printed circuit boards, but the predominant practical method is a subtractive method using wet etching.

この方法は銅箔の製造、銅箔と絶縁基材の張り合せ工程
、銅箔表面上の非エツチング部分をエツチングレジスト
剤で覆う工程、銅の不要部分を湿式エツチング法により
除去する工程等複′j11な多くの工程が必要であり、
多額のコストを必要とするという問題がある。
This method involves multiple steps, including the production of copper foil, the process of laminating the copper foil and the insulating substrate, the process of covering the non-etched areas on the surface of the copper foil with an etching resist agent, and the process of removing unnecessary areas of copper using wet etching. It requires many steps,
There is a problem in that it requires a large amount of cost.

また工程を短縮または簡略化するため、金属板または金
属箔上に銅回路を直接形成し、その銅回路を絶縁基板に
転写、接着する方法も発表されている(例えば特公昭5
5−32239号公報等)。しかしながら、この方法は
転写接着性が必ずしも充分でなく、またそれを避けるた
め高密度回路が出来ないという問題点がある。
In addition, in order to shorten or simplify the process, a method has been announced in which a copper circuit is directly formed on a metal plate or metal foil, and the copper circuit is transferred and bonded to an insulating substrate (for example,
5-32239, etc.). However, this method has the problem that the transfer adhesion is not necessarily sufficient, and to avoid this, high-density circuits cannot be formed.

U発明の目的] 本発明は、これらの従来技術の問題点を解決するために
なされたもので、工程の短縮および簡略化を図ると共に
、安価に良質の印刷回路板を製造する方法を提供するこ
とを目的とする。
UObject of the Invention] The present invention was made to solve the problems of these conventional techniques, and provides a method for shortening and simplifying the process and manufacturing a high-quality printed circuit board at low cost. The purpose is to

し発明の構成および作用] 本発明の印i+1回路板の製造方法は、金属箔の表面上
に、ネガパターンを絶縁性レジスト剤で形成した後、銅
メッキを行ない、該金属箔の表面上に銅メッキ層からな
る回路を形成し、次いで該金属筒の銅メッキ層を内側に
して絶縁基材と小ね合せ加熱加圧により一体化した後、
該金属箔を除去することを特徴とするものである。
Structure and operation of the invention] The method for manufacturing an I+1 circuit board of the present invention involves forming a negative pattern on the surface of a metal foil using an insulating resist agent, then performing copper plating, and then forming a negative pattern on the surface of the metal foil. After forming a circuit consisting of a copper plating layer, and then integrating the metal cylinder with the insulating base material with the copper plating layer inside by kneading and heating and pressurizing,
This method is characterized by removing the metal foil.

本発明においては、先ず金属箔(金属板)上に所望のネ
ガパターンを絶縁性レジスト剤で形成する。このネガパ
ターンの形成法としては、スクリーン法、フォトレジス
ト印刷法等の公知の印Ωす1ノ法が用いられる。
In the present invention, first, a desired negative pattern is formed on a metal foil (metal plate) using an insulating resist agent. As a method for forming this negative pattern, a known method such as a screen method or a photoresist printing method is used.

ここに用いられる金I11箔としては、銅メッキおよび
エツチング可能なものであれば特に制限はなく、例えば
亜鉛、アルミニウム、鉄、ニッケルまたはこれらを主成
分とする合金が用いられるが、特に10〜200μm、
好ましくは20〜iooμm程度の厚さを有するアルミ
ニウムが取り扱い、価格上からも好適である。また、こ
こに用いられる絶縁性レジスト剤としては熱硬化性レジ
スト剤、紫外線硬化レジスト剤等が挙げられる。
The gold I11 foil used here is not particularly limited as long as it can be copper plated and etched. For example, zinc, aluminum, iron, nickel, or alloys containing these as main components are used, but in particular, gold I11 foil with a thickness of 10 to 200 μm is used. ,
Preferably, aluminum having a thickness of about 20 to ioo μm is used, and is suitable from the viewpoint of cost. Further, examples of the insulating resist agent used here include a thermosetting resist agent, an ultraviolet curing resist agent, and the like.

次に、金属筒の表面上のネガパターンを形成していない
部分に銅メッキを行ない、接着性、耐熱性、耐湿性等に
優れた回路適性を有する銅メッキ層からなる回路を形成
する。銅メッキは電解銅メッキでも、無電解銅メッキで
も良いが、本発明においては、金属箔を陰極とし、電解
液として硫酸銅溶液等を用いた電解銅メッキが好ましい
Next, copper plating is performed on the surface of the metal tube where the negative pattern is not formed, to form a circuit made of a copper plating layer having excellent circuit suitability in terms of adhesiveness, heat resistance, moisture resistance, etc. Copper plating may be electrolytic copper plating or electroless copper plating, but in the present invention, electrolytic copper plating using a metal foil as a cathode and a copper sulfate solution or the like as an electrolyte is preferable.

このようにしてtqられた銅メツキ居士を所望により、
粗面化処理および/または防錆処理を行なう。粗面化処
理は、銅メツキ層上に微細な銅をメッキによりf」着さ
せることにより行なわれる。また防錆処理は、クロメー
ト処理等の無機処理またはベンゾトリアゾール等を用い
た有機処理によって成される。
If desired, the copper-metsuki koshi tqed in this way can be
Perform surface roughening treatment and/or rust prevention treatment. The surface roughening treatment is performed by depositing fine copper on the copper plating layer by plating. Further, the rust prevention treatment is performed by an inorganic treatment such as chromate treatment or an organic treatment using benzotriazole or the like.

次に、金属箔の銅メッキ層を内側にして絶縁基材と手ね
合せ加熱加圧により一体化する。この絶縁基材と一体化
する前に、金属箔上の絶縁性レジスト剤(ネガパターン
)を剥離しても良く、また絶縁基材との接着性を良好に
すべく、金属箔上に接着剤を塗工してもよい、ここに用
いられる接着剤としてはフェノール系またはエポキシ系
のものが好ましい。
Next, the metal foil is integrated with the insulating base material with the copper plating layer on the inside by hand kneading and heating and pressing. Before integrating with this insulating base material, the insulating resist agent (negative pattern) on the metal foil may be peeled off. The adhesive used here is preferably a phenolic or epoxy adhesive.

また、使用される絶縁基+4としては、紙−フェノール
基材、ガラス−フェノール基材、ガラス−エポキシ基材
等が挙げられる。
Further, examples of the insulating group +4 used include paper-phenol base material, glass-phenol base material, glass-epoxy base material, and the like.

ここにおいて、一体化する条件は、温度100℃以上、
圧力 1〜120k(1/ci、圧着時間5分以上と従
来の印刷回路板の製造にJ5ける一体化条件と比較して
、低温、低圧かつ短時間で一体化が可能であり、工程の
短縮および簡略化が図れる。
Here, the conditions for integration are a temperature of 100°C or higher,
Pressure: 1 to 120 k (1/ci), crimping time: 5 minutes or more. Compared to the J5 integration conditions used in conventional printed circuit board manufacturing, integration is possible at low temperatures, low pressure, and in a short time, shortening the process. and simplification can be achieved.

本発明においては、次に金属筒を除去する。この金属箔
の除去においては、銅メッキ層を損わないことが必要で
あり、一般的にはエツチング液を用いたエツチングが用
いられる。この際のエツチング液は金R箔によって異な
り、金属箔がアルミニウム、亜鉛の場合は、水酸化ナト
リウム、水酸化カリウム等のアルカリ溶液、鉄、ニッケ
ルの場合は塩酸、硫酸等の酸性溶液が用いられる。なお
、金属箔の除去はエツチング液を用いたエツチングのみ
ならず、エツチングガスを用いたエツチングまたは機械
的剥離によって除去してもよい。
In the present invention, the metal tube is then removed. In removing this metal foil, it is necessary not to damage the copper plating layer, and etching using an etching solution is generally used. The etching solution used at this time differs depending on the gold R foil. If the metal foil is aluminum or zinc, an alkaline solution such as sodium hydroxide or potassium hydroxide is used, and if the metal foil is iron or nickel, an acidic solution such as hydrochloric acid or sulfuric acid is used. . Note that the metal foil may be removed not only by etching using an etching solution but also by etching using an etching gas or mechanical peeling.

以下、本発明を図面に基づいて詳細に説明する。Hereinafter, the present invention will be explained in detail based on the drawings.

第1〜5図は、本発明の製造方法の一実施例であり、好
適に採用される各工程の概略図を示す。
FIGS. 1 to 5 show an embodiment of the manufacturing method of the present invention, and show schematic diagrams of each process preferably employed.

第1図に示されるように、金属箔1の表面上に絶縁性レ
ジスト剤2でネガパターン(マスク)を形成した後、銅
メッキによって銅メッキ、層からなる回路3が形成され
る。この銅メッキ筈からなる回路3の形成は、第2図に
示されるように、絶縁性レジスト剤2でマスクされた金
属箔1を陰極とし、アノード4を備えた第1電解槽5で
行なわれる。この第1電解槽5の電解液としては硫酸銅
溶液等が用いられる。金属箔1上の銅メッキ層からなる
回路3は、アノード6を備えた第2電解槽7で粗面化処
理が施される。この際の電解液も硫酸鋼溶液等が用いら
れる。粗面化処理を施された銅メッキ層からなる回路3
は、アノード8を備えた第3電解槽9に入り防錆処理が
施される。使用される防錆剤としては亜鉛、クロム、ニ
ッケル等の防錆力があり、絶縁基材との相性を損わない
ものを用いる。絶縁性レジスト剤2と粗面化処理および
防錆処理を施された銅メッキ層からなる回路3を有する
金属箔1は乾燥機10で乾燥し巻取られる。
As shown in FIG. 1, after forming a negative pattern (mask) with an insulating resist agent 2 on the surface of a metal foil 1, a circuit 3 consisting of a copper plating layer is formed by copper plating. The formation of this copper-plated circuit 3 is carried out in a first electrolytic cell 5 equipped with an anode 4 and a metal foil 1 masked with an insulating resist agent 2 as a cathode, as shown in FIG. . As the electrolyte for this first electrolytic cell 5, a copper sulfate solution or the like is used. A circuit 3 made of a copper plating layer on a metal foil 1 is subjected to surface roughening treatment in a second electrolytic bath 7 equipped with an anode 6. The electrolyte at this time also uses a sulfuric acid steel solution or the like. Circuit 3 consisting of a copper plating layer subjected to surface roughening treatment
enters a third electrolytic cell 9 equipped with an anode 8 and is subjected to rust prevention treatment. The rust preventive agent used is zinc, chromium, nickel, etc., which have rust preventive properties and do not impair compatibility with the insulating base material. A metal foil 1 having an insulating resist agent 2 and a circuit 3 made of a copper plating layer subjected to surface roughening treatment and rust prevention treatment is dried in a dryer 10 and wound up.

この際にカットしシートとしてもよい。At this time, it may be cut and made into a sheet.

次に、金属箔1は第3図に示されるように、接着剤コー
ター11により接着剤が塗布され、乾燥機12で接着剤
を乾燥した後、巻取られるか、カットしシートする。な
お、この段階でネガパターンを形成する絶縁性レジスト
剤2を剥離してもよい。
Next, as shown in FIG. 3, the metal foil 1 is coated with an adhesive by an adhesive coater 11, dried by a dryer 12, and then wound or cut into sheets. Note that the insulating resist agent 2 forming the negative pattern may be peeled off at this stage.

次に金属箔1は絶縁基材13と併せ、第4図に示すよう
な、熱板14、ステンレスプレート15等を有する積層
プレス橢16中で積層プレスして一体化した後、第5図
に示されるスプレーノズル17、ロールコンベアー18
等を有する金属エツチング装買19で金属箔]を全面エ
ツチング除去することにより絶縁基材13上に良質な銅
メッキ層からなる回路3を形成させる。
Next, the metal foil 1 is laminated and pressed together with the insulating base material 13 in a laminated press 16 having a hot plate 14, a stainless steel plate 15, etc. as shown in FIG. Spray nozzle 17, roll conveyor 18 shown
The circuit 3 made of a high-quality copper plating layer is formed on the insulating base material 13 by etching away the entire surface of the metal foil using a metal etching device 19 having a metal etching device 19.

「実施例」 以下、本発明を実施例および比較例に基づき具体的に説
明する。
“Examples” The present invention will be specifically described below based on Examples and Comparative Examples.

実施例1およびtヒ較例1 金属箔として市販のアルミニウム箔を用い、絶縁性レジ
スト剤として市販の熱硬化性レジスト剤を用い、アルミ
ニウム箔の上にネガパターンを形成した。なお、回路の
最小巾は0.2mm、最大中は20vunとした。
Example 1 and Comparative Example 1 A negative pattern was formed on the aluminum foil using a commercially available aluminum foil as the metal foil and a commercially available thermosetting resist agent as the insulating resist agent. Note that the minimum width of the circuit was 0.2 mm, and the maximum width was 20 vun.

次に、’AM銅溶液(Cu30q/)、1イ2S○45
0(1/j)を電解液として銅メッキを行ない、銅メッ
キ層からなる回路を作成した後、防錆処理として無水ク
ロム酸10g/Jの溶液に浸漬し、クロメート処理を行
なった。
Next, 'AM copper solution (Cu30q/), 1i2S○45
Copper plating was performed using 0(1/j) as an electrolytic solution to create a circuit consisting of a copper plating layer, and then chromate treatment was performed by immersing it in a solution of 10 g/J of chromic anhydride as antirust treatment.

このアルミニウム箔をガラス−エポキシ基材と積層プレ
スを行なって一体化した後、水酸化ナトリウム溶液(3
0g/J )により、エツチングを行なってアルミニウ
ム箔を溶解除去した。
This aluminum foil was integrated with a glass-epoxy base material by lamination pressing, and then a sodium hydroxide solution (3
0g/J) to dissolve and remove the aluminum foil.

このようにして得られた銅回路板(実施例1)について
、JISC6481に規定する印判回路用鋼張積層板試
験方法にQ−拠して接着力および260℃ハンダ処理、
120秒について試験を行ない、結果を第1表に示した
The thus obtained copper circuit board (Example 1) was tested for adhesive strength and 260°C soldering according to the test method for steel clad laminates for stamp circuits specified in JISC6481.
The test was conducted for 120 seconds and the results are shown in Table 1.

また、比較として市販の銅張V4舅板からサブ1〜ラク
テイブ法により1qられた銅回路板(比較例1)につい
ても同様の試験を行ない、この結果も第1表に示した。
Further, for comparison, a similar test was conducted on a copper circuit board (Comparative Example 1) prepared from a commercially available copper-clad V4 leg plate by the sub-1 to lactive methods, and the results are also shown in Table 1.

第1表 m;■ 第1表に示されるように、本発明により1!′?られた
印刷回路板(実施例1)は、従来より用いられているサ
ブ1〜ラクテイブ法により肖られる印刷回路板(比較例
1)と同等の特性を有している。
Table 1 m;■ As shown in Table 1, according to the present invention, 1! ′? The printed circuit board (Example 1) produced by the present invention has characteristics equivalent to those of the printed circuit board (Comparative Example 1) produced by the conventionally used sub-1 to lactive methods.

[発明の効果] 以上説明したように、本発明の印刷回路板の製造方法に
よれば、工程の短縮および簡略化が図れると共に、安価
に良質の印刷回路板が製造できるという利点を有する。
[Effects of the Invention] As described above, the method for manufacturing a printed circuit board of the present invention has the advantage that the process can be shortened and simplified, and a high-quality printed circuit board can be manufactured at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第1〜5図は、本発明の製造方法の一実施例であり、好
適に採用される各工程の概略図を示1゜1:金属箔、 
 2:絶縁性レジスト剤、3:鋼メンキ層からなる回路
、 13;絶縁吊材。 特許出願人  三井金属鉱業株式会社 代理人 弁理士 伊 東 辰 雄 代理人 弁理士 伊 東 哲 仁 ジ 第 1 図 第2図 第3図 第 5 回
Figures 1 to 5 show an example of the manufacturing method of the present invention, and show schematic diagrams of each process preferably adopted.1゜1: Metal foil,
2: Insulating resist agent, 3: Circuit made of steel coating layer, 13: Insulating hanging material. Patent applicant Mitsui Kinzoku Mining Co., Ltd. Agent Patent attorney Tatsuo Ito Agent Patent attorney Satoshi Ito No. 1 Figure 2 Figure 3 Figure 5

Claims (1)

【特許請求の範囲】 1、金属箔の表面上に、ネガパターンを絶縁性レジスト
剤で形成した後、銅メッキを行ない、該金属箔の表面上
に銅メッキ層からなる回路を形成し、次いで該金属箔の
銅メッキ層を内側にして絶縁基材と重ね合せ加熱加圧に
より一体化した後、該金属箔を除去することを特徴とす
る印刷回路板の製造方法。 2、前記銅メッキ層が粗面化処理および/または防錆処
理が施されている特許請求の範囲第1項記載の印刷回路
板の製造方法。 3、前記銅メッキが前記金属箔を陰極とする電解銅メッ
キである特許請求の範囲第1項または第2項記載の印刷
回路板の製造方法。 4、前記金属箔の除去がエッチング液を用いたエッチン
グによりなされる特許請求の範囲第1項、第2項または
第3項記載の印刷回路板の製造方法。
[Claims] 1. After forming a negative pattern with an insulating resist agent on the surface of the metal foil, copper plating is performed, and a circuit consisting of a copper plating layer is formed on the surface of the metal foil, and then A method for manufacturing a printed circuit board, which comprises stacking the metal foil on an insulating base material with the copper plating layer on the inside and integrating the metal foil by heating and pressing, and then removing the metal foil. 2. The method for manufacturing a printed circuit board according to claim 1, wherein the copper plating layer is subjected to surface roughening treatment and/or antirust treatment. 3. The method for manufacturing a printed circuit board according to claim 1 or 2, wherein the copper plating is electrolytic copper plating using the metal foil as a cathode. 4. The method for manufacturing a printed circuit board according to claim 1, 2, or 3, wherein the metal foil is removed by etching using an etching solution.
JP16214186A 1986-07-11 1986-07-11 Manufacture of printed circuit board Pending JPS6318693A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16214186A JPS6318693A (en) 1986-07-11 1986-07-11 Manufacture of printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16214186A JPS6318693A (en) 1986-07-11 1986-07-11 Manufacture of printed circuit board

Publications (1)

Publication Number Publication Date
JPS6318693A true JPS6318693A (en) 1988-01-26

Family

ID=15748813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16214186A Pending JPS6318693A (en) 1986-07-11 1986-07-11 Manufacture of printed circuit board

Country Status (1)

Country Link
JP (1) JPS6318693A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02122691A (en) * 1988-11-01 1990-05-10 Shinko Electric Ind Co Ltd Manufacture of printed circuit board
JPH02163540A (en) * 1988-12-15 1990-06-22 Kawada Tekkosho:Kk Welding device
JPH02164094A (en) * 1988-12-19 1990-06-25 Matsushita Electric Ind Co Ltd Manufacture of printed wiring board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6055695A (en) * 1983-09-07 1985-03-30 ダイソー株式会社 Conductive pattern forming unit of circuit board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6055695A (en) * 1983-09-07 1985-03-30 ダイソー株式会社 Conductive pattern forming unit of circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02122691A (en) * 1988-11-01 1990-05-10 Shinko Electric Ind Co Ltd Manufacture of printed circuit board
JPH02163540A (en) * 1988-12-15 1990-06-22 Kawada Tekkosho:Kk Welding device
JPH02164094A (en) * 1988-12-19 1990-06-25 Matsushita Electric Ind Co Ltd Manufacture of printed wiring board

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