JPS6247197A - Manufacture of multilayer interconnection board - Google Patents
Manufacture of multilayer interconnection boardInfo
- Publication number
- JPS6247197A JPS6247197A JP18709285A JP18709285A JPS6247197A JP S6247197 A JPS6247197 A JP S6247197A JP 18709285 A JP18709285 A JP 18709285A JP 18709285 A JP18709285 A JP 18709285A JP S6247197 A JPS6247197 A JP S6247197A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- inner layer
- plating
- holes
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
内層回路板に両面銅張りＷ４層板を用いノこ多層印刷配
線板に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Use This invention relates to a saw multilayer printed wiring board using a double-sided copper-clad W4-layer board as an inner layer circuit board.
従来の技術
プリプレグを用いプレス方法によらないで製造する多層
配線板の製造方法としては、めっき触媒入り接着剤を塗
布した絶縁板の表裏面にめっきレジスト層を形成した後
、無電解銅めっき液に浸潤して内層回路を形成し、この
内層回路の銅表面を化学的に粗面化処理し、この上に順
次絶縁層、接着剤を形成し、スルーホール用の穴明けを
行い、めっきレジスト層を形成した後、無電解めっきを
施し、外層回路及びスルーホールを形成して多層配線板
を製作していた。Conventional technology A method for manufacturing a multilayer wiring board using prepreg without using a pressing method is to form a plating resist layer on the front and back surfaces of an insulating board coated with an adhesive containing a plating catalyst, and then apply an electroless copper plating solution. The copper surface of the inner layer circuit is chemically roughened, an insulating layer and an adhesive are sequentially formed on this, holes are made for through holes, and a plating resist is formed. After forming the layers, electroless plating was performed to form outer layer circuits and through holes to produce a multilayer wiring board.
発明が解決しようとする問題点
従来の多層配線板における内層回路板の電源部やグラン
ド部は電源の供給間や特性インピーダンスの設定のため
に、銅箔面積を広くとる場合があり、無電解銅めっきに
より行うとコスト高になり、また、外層も無電解めっき
により銅箔層を形成することは少なくとも２回のめっき
工程をたどるため、作業に長時間を要し、生産性が低か
った。Problems to be Solved by the Invention In conventional multilayer wiring boards, the power supply section and ground section of the inner layer circuit board may require a large area of copper foil in order to set the power supply and characteristic impedance. If done by plating, the cost would be high, and forming the copper foil layer on the outer layer by electroless plating would require at least two plating steps, which would take a long time and result in low productivity.
問題点を解決するための手段
本発明は、両面銅張り積層板を用い、スクリーン印刷を
行い、エツヂング処理により内層回路を形成した内層配
線板を製作し、この内層配線板の銅箔表面の粗面化処理
を行い、イの上に絶縁層を印刷被覆し、接着層を形成し
、スルーホール用穴明けを行い、めっき１ノジスト層を
形成した後無電解めっきに」：り外層回路を形成して多
層配線板を製造する。Means for Solving the Problems The present invention uses a double-sided copper-clad laminate, performs screen printing, and forms an inner layer circuit by etching to produce an inner layer wiring board, and improves the roughness of the copper foil surface of this inner layer wiring board. After performing surface treatment, printing an insulating layer on top of A, forming an adhesive layer, drilling holes for through holes, and forming a plating layer, electroless plating is performed to form an outer layer circuit. Then, a multilayer wiring board is manufactured.
作用
本発明の製造方法を用いれば、作業時間の短縮化に寄与
できるのでコスト低減が図れる。Function: Using the manufacturing method of the present invention can contribute to shortening the working time, thereby reducing costs.
実施例
本発明の多層配線板の製造方法は、内層配線板の基材と
して両面銅張り積層板を用い、この積層板にスクリーン
印刷法で残置するエツチングレジスト回路を形成した後
エツチング処理して内層配線板を製作する。Embodiment The method for manufacturing a multilayer wiring board according to the present invention uses a double-sided copper-clad laminate as a base material for the inner layer wiring board, and after forming an etching resist circuit to be left on the laminate by screen printing, etching the inner layer. Manufacture a wiring board.
この内層配線板の表裏面に絶縁層として２００ｐｓ以下
の低粘度に調整した絶縁樹脂を用い、樹脂の吐出量が多
い２０〜１５０メツシユのスクリーン印刷版で印刷する
。この」−に触媒入り接着剤を塗布した後、スルーホー
ル用の穴明けを行い、めっきレジスト層を形成し、無電
解銅めつぎにより外層回路を作り多層配線板をうる。な
、１３、両面銅張り積層板の基板内にめっき触媒が混入
され−Ｃいない場合には、増感剤処理を行ってスルーホ
ール内にめっき触媒のイ」与を行う。An insulating resin whose viscosity is adjusted to a low viscosity of 200 ps or less is used as an insulating layer on the front and back surfaces of this inner layer wiring board, and printing is performed using a 20 to 150 mesh screen printing plate that discharges a large amount of resin. After applying a catalyst-containing adhesive to this layer, holes for through holes are formed, a plating resist layer is formed, an outer layer circuit is formed by electroless copper plating, and a multilayer wiring board is obtained. 13. If the plating catalyst is mixed into the substrate of the double-sided copper-clad laminate and there is no -C, a sensitizer treatment is performed to irrigate the plating catalyst into the through-holes.
内層配線板の基材に両面銅張り積層板を用い回路形成す
ることにより、従来の無電解めっきで回路を形成すると
ぎ３０時間要していたが３時間で１−み、従来方法と本
発明によるＩ’Ｊ Ｘａ方法による特性を下記の表に示
す。By forming a circuit using a double-sided copper-clad laminate as the base material of the inner layer wiring board, it took 3 hours to form a circuit instead of 30 hours using conventional electroless plating. The properties according to the I'J Xa method are shown in the table below.
表
表かられかるように特性としてはほぼ同様の特性かえら
れる。As you can see from the table, the characteristics are almost the same.
発明の効果
本発明は上記に説明した通り、多層配線板を製造するに
際し、内層配線板に両面銅張り積層板を用いることによ
り、回路形成に要する時間を大幅に短縮できた。Effects of the Invention As explained above, in the present invention, when manufacturing a multilayer wiring board, by using a double-sided copper-clad laminate as an inner layer wiring board, the time required for circuit formation can be significantly shortened.
Claims (1)
、この積層板にエッチングレジストを印刷した後、エッ
チング処理して内層配線板を製作し、この内層配線板の
表裏面に順次絶縁層及び接着剤を形成し、スルーホール
用の穴明けを行い、めつきレジスト層を設け、無電解め
っき液に浸漬し銅めつきを形成することを特徴とする多
層配線板の製造方法。(1) A double-sided copper-clad laminate is used as the base material for the inner layer wiring board. After printing an etching resist on this laminate, etching is performed to produce the inner layer wiring board, and the front and back surfaces of the inner layer wiring board are sequentially insulated. A method for producing a multilayer wiring board, which comprises forming a layer and an adhesive, drilling holes for through holes, providing a plating resist layer, and immersing the board in an electroless plating solution to form copper plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18709285A JPS6247197A (en) | 1985-08-26 | 1985-08-26 | Manufacture of multilayer interconnection board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18709285A JPS6247197A (en) | 1985-08-26 | 1985-08-26 | Manufacture of multilayer interconnection board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6247197A true JPS6247197A (en) | 1987-02-28 |
Family
ID=16199963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18709285A Pending JPS6247197A (en) | 1985-08-26 | 1985-08-26 | Manufacture of multilayer interconnection board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6247197A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5013828A (en) * | 1988-04-21 | 1991-05-07 | Central Glass Company, Limited | Preparation of diacyl derivatives of 2'-deoxy-5-fluorouridine via novel intermediate compound |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5522774U (en) * | 1978-08-02 | 1980-02-14 | ||
| JPS5839099A (en) * | 1981-08-31 | 1983-03-07 | シャープ株式会社 | Method of producing multilayer printed circuit board |
| JPS5854520A (en) * | 1981-09-28 | 1983-03-31 | 株式会社東芝 | Method of producing electric contact |
-
1985
- 1985-08-26 JP JP18709285A patent/JPS6247197A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5522774U (en) * | 1978-08-02 | 1980-02-14 | ||
| JPS5839099A (en) * | 1981-08-31 | 1983-03-07 | シャープ株式会社 | Method of producing multilayer printed circuit board |
| JPS5854520A (en) * | 1981-09-28 | 1983-03-31 | 株式会社東芝 | Method of producing electric contact |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5013828A (en) * | 1988-04-21 | 1991-05-07 | Central Glass Company, Limited | Preparation of diacyl derivatives of 2'-deoxy-5-fluorouridine via novel intermediate compound |
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