JPS60193362A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60193362A
JPS60193362A JP5031484A JP5031484A JPS60193362A JP S60193362 A JPS60193362 A JP S60193362A JP 5031484 A JP5031484 A JP 5031484A JP 5031484 A JP5031484 A JP 5031484A JP S60193362 A JPS60193362 A JP S60193362A
Authority
JP
Japan
Prior art keywords
film
melting point
high melting
point metal
wiring layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5031484A
Other languages
Japanese (ja)
Inventor
Tatsuro Okamoto
岡本 龍郎
Hideo Kotani
小谷 秀夫
Shuichi Matsuda
修一 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5031484A priority Critical patent/JPS60193362A/en
Publication of JPS60193362A publication Critical patent/JPS60193362A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent the generation of a hillock on the wiring layers of a semiconductor device by a method wherein films consisting of a high melting point metal or the nitride thereof are provided to the surfaces of the wiring layers consisting of Al or an Al alloy. CONSTITUTION:An insulating film 2 is formed on the main surface of a semiconductor substrate 1, and a film 6 consisting of a high melting point metal is formed thereon. Then a film 3 consisting of Al or an Al alloy is formed, and a film 7 consisting of a high melting point metal is formed thereon. Then patterning of the films 3, 6, 7 is performed to form wiring layers 3a, 3b. Then after a film 8 consisting of a high melting point metal is formed on the whole surface of the top part, out of the film 8, the parts of regions in parallel with the main surface of the substrate 2 are removed to leave only the side face parts 8a-8d. After then, after an interlayer insulating film 4 is formed, a film 5 to be used as a wiring layer is formed. When a semiconductor device is constructed in such a way, because the high melting point metal or the nitride thereof existing on the surfaces of the wiring layers consisting of Al or an Al alloy diffuses to the surfaces of the wiring layers according to posterior heat treatment to form an alloy with the Al, growth of a hillock is suppressed.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明に、半導体装置の配線層の構造に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a structure of a wiring layer of a semiconductor device.

〔従来技術〕[Prior art]

第1図に従来の半導体装置の一例として2層配#i!信
造のものを、その製造方法と共に説明するためVC便造
工程駒に示した断面図である。まず、第1図(a’)V
C示す如く、半導体基本111上に二酸化シリコン(s
ioQ)などD)らなる絶縁膜(2)を形成し、そのに
、VCアルミニウム又はアルミニウム合金からなる被膜
(3)を、スパッタ法あるいは真空蒸看法などで形成す
る。続いて、同図(b) VC示す90く、写真製版と
エツチング法とにより被膜:31のバターニングを行う
ことにより、第lの配線N!4(あ)、 (3b)を形
成する。次に、同図(c)に示す如く、層間絶縁のため
VcSiOa又Fia化シリコy (SisN4) f
zどβ)らなる絶縁膜!412 CjVD法あるいけス
パッタ法などで形成し、続いて同図(dlVc示す如く
絶縁膜(4)上に渠2の配線層illを形成する。その
後、CVD法あるいけスパッタ法で813N4又け5l
ollなど〃〉らなる保護@(図示せず)をと部全面に
形成する。
FIG. 1 shows a two-layer structure #i! as an example of a conventional semiconductor device. It is a cross-sectional view of Shinzo's product shown in the VC Binzo process piece for explaining the manufacturing method thereof. First, Figure 1 (a') V
As shown in C, silicon dioxide (s
An insulating film (2) made of D) such as ioQ) is formed, and a coating (3) made of VC aluminum or an aluminum alloy is formed thereon by sputtering or vacuum evaporation. Subsequently, the first wiring N! is patterned by patterning the film 31 using photolithography and etching as shown in FIG. 9(b) VC. Form 4(a) and (3b). Next, as shown in the same figure (c), for interlayer insulation, VcSiOa or Fia silicon y (SisN4) f
An insulating film made of zdβ)! 412 CjVD method or direct sputtering method, etc., and then, as shown in the same figure (dlVc), the wiring layer ill of conduit 2 is formed on the insulating film (4).After that, 813N 4-way 5l is formed by CVD method or direct sputtering method.
A protection layer (not shown) consisting of oll or the like is formed over the entire surface of the abutment.

従来、の半導体11i +1は、このように構成されて
おり、第1の配am (3a)、 (3b)と第2の配
線層+51 Fi、層間の絶縁膜141で電気的に絶縁
されている。し〃)し、第1及び第2の配置184 (
3a)、 (3h)、+51をアニールするため450
℃前後の熱処理を行なう心安があり、また、保−mをC
VD法により形成する場合には、300〜400℃の熱
処理を受けることになる。
The conventional semiconductor 11i+1 is configured as described above, and is electrically insulated by the first wiring layer (3a), (3b), the second wiring layer +51Fi, and the interlayer insulating film 141. . ) and the first and second arrangements 184 (
3a), (3h), 450 to anneal +51
There is peace of mind in performing heat treatment at around ℃, and it is also possible to
When forming by the VD method, it will undergo heat treatment at 300 to 400°C.

この熱処理により第2図に承す如く第1の配# hv!
Jであるアルミニウム又はアルミニウム合金の被膜の氏
面や側面に突起物(「ヒロック」と称す。)(友)、(
匿)が成長し、第1の配#I!層(あ)+ (”b)と
第2の配#層(51との間の心気的絶縁特性が劣化する
ため素子の歩留低下の大きな原因となっていた。
By this heat treatment, as shown in FIG. 2, the first distribution #hv!
Projections (referred to as "hillocks") on the sides and sides of the aluminum or aluminum alloy coating that is J (Friend), (
Hidden) has grown and the first distribution #I! The deterioration of the insulating properties between the layer (A) + ("b) and the second interconnection layer (51) was a major cause of a decrease in the yield of devices.

〔発1Jのa要〕 この発明ば、上記のような従来のものの欠点を除去する
ためになさねたもので、アルミニウム又はアルミニウム
合金からなる配線層の表面Vc商融点金属又けその窒化
物からなる被膜を形成することにより、熱処理でヒロッ
クが生じない安定な配m11!!1ciする半導体装置
を提供することを目的としている。
[Summary of Part 1J] This invention was made to eliminate the above-mentioned drawbacks of the conventional ones, and it is possible to reduce the surface Vc of a wiring layer made of aluminum or an aluminum alloy from a metal with a commercial melting point or its nitride. By forming a film that is stable, no hillocks occur during heat treatment! ! The purpose is to provide a semiconductor device with 1ci.

〔発明の友織例〕 第3図を参照してこの発明の実砲例を説明する。[Examples of inventions] An example of an actual gun according to the present invention will be explained with reference to FIG.

J3図け、この発明の実砲例の構造をその製造り法の一
例と共VC説明するために製造工程順に記載した断面図
でちる。まず、第3図(a+に示す如く、半導体葉板(
りの主面上に5in2などの絶縁膜(2)を形成し、そ
の上にスパッタ法、真空蒸着法あるいけCVD法などに
よりチタン(T1)やタンタル(Ta)などの高融点金
属からなる被膜(6)を形成する。次に、アルミニウム
又はアルミニウム合金からなる被膜+a+をスパッタ法
、具空蒸右法あるいはCVD法などで形成し、さらにそ
のJz[TiやTaなどの尚戦点金用からなる?を幌(
7)を形成する。続いて、第3図(b) VC示す如く
、写真製版及びエツチング法により、被膜(31、T6
1 、 +71のパターニングを行ない、第1の配線層
(3a)、 (sb)を形成する。次に、第3図(cl
に示す如く、上部全面にT1やTaなとの尚融点金属か
らなる被膜181を形成した後、fJ3図(alVc示
す如く、異方性エツチングにより被膜(8)のうち半導
体基板(2)の主面とほぼ平行なIIIJtの部分を除
去し、側面部(8a)、 (8b)、 (8c)、 (
Ekl)のみを残す。その後、従来の半導体装置と同様
、第3図(e)に示す如く層間の絶縁膜(4)を形成し
た後、窮3図tflVc示す如く第2の配線層となる被
膜(5;を形成する。
Figure J3 is a sectional view showing the structure of an actual gun according to the present invention, along with an example of its manufacturing method, in order of manufacturing steps. First, as shown in Figure 3 (a+), the semiconductor leaf plate (
An insulating film (2) such as 5in2 is formed on the main surface of the film, and a film made of a high melting point metal such as titanium (T1) or tantalum (Ta) is formed on it by sputtering, vacuum evaporation, CVD, etc. (6) is formed. Next, a coating +a+ made of aluminum or an aluminum alloy is formed by a sputtering method, a vacuum evaporation method, a CVD method, etc. The hood (
7). Subsequently, as shown in FIG. 3(b) VC, a film (31, T6) was formed by photolithography and etching.
1 and +71 patterning is performed to form first wiring layers (3a) and (sb). Next, Figure 3 (cl.
As shown in Figure 3, after forming a film 181 made of a melting point metal such as T1 or Ta on the entire upper surface, the main part of the semiconductor substrate (2) of the film (8) is etched by anisotropic etching as shown in Fig. fJ3 (alVc). The portion of IIIJt that is almost parallel to the surface is removed, and the side parts (8a), (8b), (8c), (
Only Ekl) is left. After that, as in the conventional semiconductor device, an interlayer insulating film (4) is formed as shown in FIG. .

次に、史に具体的な寿篩丙について説明する。Next, I will explain the specific history of Shou Shuhei.

表面[5iOa膜を設けた半導体蒸飯上に、スパッタ法
でTiW (T110チ)の膜を100OA形成し、そ
の上にスパッタ法でhl−sl(811%)の被膜を形
成し、さらにそ(D )、 [スパッタ法でTIW (
Tl 1a%)の膜を100OA破着させた後、パター
ニングを行ない、続いてプラズマCVD法によって全面
vc 5iaNa膜を1・2,11m形成した。これを
45σCNjガス雰囲気中で30分間熱処理を行なった
が、上記AtSiの被III Vcヒロックの発生は全
く見られなかった。
A TiW (T110) film of 100 OA was formed on the semiconductor vapor with a 5 iOa film on the surface by sputtering, a hl-sl (811%) film was formed on it by sputtering, and then D), [TIW (
After the Tl (1a%) film was broken down to 100 OA, patterning was performed, and then a VC 5iaNa film of 1.2 and 11 m thick was formed on the entire surface by plasma CVD. This was heat-treated for 30 minutes in a 45σCNj gas atmosphere, but no formation of the above-mentioned AtSi III-Vc hillocks was observed.

さらに、高融点金属として上記のTiWの代りにT1や
Taを用いたもの及びそれらの窒化物であるTiNやT
aNを用いたものについても、ヒロックの発生は全く見
られなかった。
Furthermore, T1 and Ta are used instead of the above-mentioned TiW as high melting point metals, and their nitrides such as TiN and T
In the case of using aN, no hillocks were observed at all.

これは、アルミニウム又はアルミニウム合金からなる配
線層のが面に介在する高融点金属又はその窒化物が後の
熱処理(通常300〜500℃)で、配線層の長面に拡
散して、アルミニウムと合金をつくるので、ヒロックの
成長が抑制されるためである。
This is because the refractory metal or its nitride interposed on the surface of the wiring layer made of aluminum or aluminum alloy diffuses into the long surface of the wiring layer during subsequent heat treatment (usually at 300 to 500°C) and becomes alloyed with aluminum. This is because the growth of hillocks is suppressed.

なお、上記の芙織例は配線層の全面又はE下面に尚融点
金属金被看した場合について説明したが、少なくともヒ
ロックの発生が素子のm進上問題とhる配線層のl1i
iに高融点金属から彦る被膜を設ければよい。
In addition, the above-mentioned example of furori was explained in the case where the entire surface of the wiring layer or the lower surface of the wiring layer is coated with melting point metal gold.
A coating made of a high melting point metal may be provided on i.

また、上記の実砲〃すは、2層配線f1弯造の半導体装
1ilVcついて説明したが、1層配緑h1造や31台
以北の多層配線(1つ造の半導体装置にi 4 ill
できる。
In addition, in the above actual gun, the semiconductor device 1ilVc with two-layer wiring f1 structure was explained, but it is also possible to
can.

〔発明の効果〕〔Effect of the invention〕

以ヒのように、この発明によれは、アルミニウム又はア
ルミニウム合金からなる配線層の表面に高融点金属又は
その窒化物からなる膜を設けるようVC構成したので、
配線層にヒロ′ンクが生しない。
As described below, the present invention has a VC configuration in which a film made of a high melting point metal or its nitride is provided on the surface of a wiring layer made of aluminum or an aluminum alloy.
Hero links do not appear on the wiring layer.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の半導体装lltを製造工程順に示す断面
図、第2図はヒロックが発生した状態を示す断面図、第
3図はこの発明の一実施例をそのjW造方法の一例と共
に示す断面図である。 図において、+11は半導体基板、(3R)、 (3b
)は配線層、+61 、171 、 +81は高融点金
属又はその窒化物力)らなる被膜である。 なお、図中、同一符号は同一または相当部分を示す。 代理人 大岩増雄 第1図 第2図 第3図 第3図 手続補正書(自発) 1.事件の表示 特願昭59−50814号3、補正を
する者 代表者片山仁へ部 4、f(埋入 5、補正の対象 明細書の発明の詳細な説明の欄 6、 補正の内容 (1)明細書第8頁第4行に「素子の歩留低下」とある
のを、「素子の歩留及び信頼性の低下」と訂正する。 以上
Fig. 1 is a cross-sectional view showing a conventional semiconductor device llt in the order of manufacturing steps, Fig. 2 is a cross-sectional view showing a state where hillocks have occurred, and Fig. 3 is a cross-sectional view showing an embodiment of the present invention together with an example of its jW manufacturing method. FIG. In the figure, +11 is the semiconductor substrate, (3R), (3b
) is a wiring layer, and +61, 171, +81 are high melting point metals or their nitrides). In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 Figure 3 Procedural amendment (voluntary) 1. Indication of the case Japanese Patent Application No. 59-50814 3, Part 4, f (embedded 5, detailed description of the invention in the specification subject to the amendment 6, Contents of the amendment (1) to Hitoshi Katayama, representative of the person making the amendment) ) In the fourth line of page 8 of the specification, the phrase "decreased yield of devices" is corrected to "decreased yield and reliability of devices."

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上にアルミニウム又はアルミニウム合金から
なる配線層を設けた半導体装置において、前記配#層の
畏面Vc市一点金属又はその輩化物からなる被覆物を形
成したこと全特徴とする半導体装置。
1. A semiconductor device comprising a wiring layer made of aluminum or an aluminum alloy on a semiconductor substrate, characterized in that a coating made of a metal or a substitute thereof is formed on the surface of the wiring layer.
JP5031484A 1984-03-14 1984-03-14 Semiconductor device Pending JPS60193362A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5031484A JPS60193362A (en) 1984-03-14 1984-03-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5031484A JPS60193362A (en) 1984-03-14 1984-03-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60193362A true JPS60193362A (en) 1985-10-01

Family

ID=12855431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5031484A Pending JPS60193362A (en) 1984-03-14 1984-03-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60193362A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61154048A (en) * 1984-12-26 1986-07-12 Nec Corp Wiring and manufacture thereof
JPH0245959A (en) * 1988-08-06 1990-02-15 Seiko Epson Corp Semiconductor device
JPH02162733A (en) * 1988-12-15 1990-06-22 Nec Corp Semiconductor device
JPH0370137A (en) * 1989-07-20 1991-03-26 Hyundai Electron Ind Co Ltd Element linking metal wiring layer in semiconductor integrated circuit and manufacture thereof
CN103165623A (en) * 2011-12-16 2013-06-19 群康科技(深圳)有限公司 Thin film transistor base plate, preparation method thereof and displayer
US9196734B2 (en) 2011-12-16 2015-11-24 Innocom Technology (Shenzhen) Co., Ltd. Thin-film transistor substrate and method for fabricating the same, display

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4936517A (en) * 1972-08-08 1974-04-04
JPS5467766A (en) * 1977-11-10 1979-05-31 Toshiba Corp Semiconductor device
JPS5615070A (en) * 1979-07-18 1981-02-13 Fujitsu Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4936517A (en) * 1972-08-08 1974-04-04
JPS5467766A (en) * 1977-11-10 1979-05-31 Toshiba Corp Semiconductor device
JPS5615070A (en) * 1979-07-18 1981-02-13 Fujitsu Ltd Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61154048A (en) * 1984-12-26 1986-07-12 Nec Corp Wiring and manufacture thereof
JPH0245959A (en) * 1988-08-06 1990-02-15 Seiko Epson Corp Semiconductor device
JPH02162733A (en) * 1988-12-15 1990-06-22 Nec Corp Semiconductor device
JPH0370137A (en) * 1989-07-20 1991-03-26 Hyundai Electron Ind Co Ltd Element linking metal wiring layer in semiconductor integrated circuit and manufacture thereof
CN103165623A (en) * 2011-12-16 2013-06-19 群康科技(深圳)有限公司 Thin film transistor base plate, preparation method thereof and displayer
US9196734B2 (en) 2011-12-16 2015-11-24 Innocom Technology (Shenzhen) Co., Ltd. Thin-film transistor substrate and method for fabricating the same, display

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