JPS60193194A - デコ−ダ回路 - Google Patents

デコ−ダ回路

Info

Publication number
JPS60193194A
JPS60193194A JP59048702A JP4870284A JPS60193194A JP S60193194 A JPS60193194 A JP S60193194A JP 59048702 A JP59048702 A JP 59048702A JP 4870284 A JP4870284 A JP 4870284A JP S60193194 A JPS60193194 A JP S60193194A
Authority
JP
Japan
Prior art keywords
circuit
threshold voltage
stage
decoder
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59048702A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0518199B2 (enExample
Inventor
Toshi Sano
佐野 東志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59048702A priority Critical patent/JPS60193194A/ja
Publication of JPS60193194A publication Critical patent/JPS60193194A/ja
Publication of JPH0518199B2 publication Critical patent/JPH0518199B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
JP59048702A 1984-03-14 1984-03-14 デコ−ダ回路 Granted JPS60193194A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59048702A JPS60193194A (ja) 1984-03-14 1984-03-14 デコ−ダ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59048702A JPS60193194A (ja) 1984-03-14 1984-03-14 デコ−ダ回路

Publications (2)

Publication Number Publication Date
JPS60193194A true JPS60193194A (ja) 1985-10-01
JPH0518199B2 JPH0518199B2 (enExample) 1993-03-11

Family

ID=12810640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59048702A Granted JPS60193194A (ja) 1984-03-14 1984-03-14 デコ−ダ回路

Country Status (1)

Country Link
JP (1) JPS60193194A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02218096A (ja) * 1989-02-17 1990-08-30 Sharp Corp 半導体メモリの行選択回路
JP2009517980A (ja) * 2005-11-28 2009-04-30 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 1ステージの遅延による投機的なアドレスデコーダ

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07284197A (ja) * 1994-04-08 1995-10-27 Nec Corp ダイポール放射型低周波水中送波器

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02218096A (ja) * 1989-02-17 1990-08-30 Sharp Corp 半導体メモリの行選択回路
JP2009517980A (ja) * 2005-11-28 2009-04-30 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 1ステージの遅延による投機的なアドレスデコーダ
JP4920044B2 (ja) * 2005-11-28 2012-04-18 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 1ステージの遅延による投機的なアドレスデコーダ

Also Published As

Publication number Publication date
JPH0518199B2 (enExample) 1993-03-11

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