JPS60189266A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS60189266A JPS60189266A JP4435084A JP4435084A JPS60189266A JP S60189266 A JPS60189266 A JP S60189266A JP 4435084 A JP4435084 A JP 4435084A JP 4435084 A JP4435084 A JP 4435084A JP S60189266 A JPS60189266 A JP S60189266A
- Authority
- JP
- Japan
- Prior art keywords
- island
- oxide film
- film
- gate oxide
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 239000012212 insulator Substances 0.000 claims abstract description 16
- 239000013078 crystal Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 150000004767 nitrides Chemical class 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 abstract description 2
- 238000002425 crystallisation Methods 0.000 abstract 1
- 230000008025 crystallization Effects 0.000 abstract 1
- 230000002349 favourable effect Effects 0.000 abstract 1
- 238000002161 passivation Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000009413 insulation Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 241000270708 Testudinidae Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体集積回路、特に高密度、高速な半導体集
積回路の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit, and particularly to the structure of a high-density, high-speed semiconductor integrated circuit.
従来例の構成とその問題点
半導体装置は最近ますます高密度化、高速化される傾向
にあシ、そのため絶縁分離の半導体集積回路の開発に対
する要望が高まっている。従来、絶縁物分離の半導体集
積回路の形成には例えば絶縁物基板１１上の絶縁物１２
中にポＩＪ Ｓｉの島１６を形成し、このポリＳｉ島１
５にビームアニールを施すことによシポリＳｉの単結晶
化または大粒径化を行ない、ゲート酸化膜の形成、ゲー
ト形成等の工程を経てトランジスタが形成されていた。Conventional Structures and Problems Semiconductor devices have recently become more dense and faster, and as a result, there has been an increasing demand for the development of semiconductor integrated circuits with insulation isolation. Conventionally, in forming an insulator-separated semiconductor integrated circuit, for example, an insulator 12 on an insulator substrate 11 is used.
A poly-Si island 16 is formed inside the poly-Si island 1.
5 is subjected to beam annealing to make SiPoly Si into a single crystal or to have a large grain size, and through steps such as forming a gate oxide film and forming a gate, a transistor is formed.
このとき、ゲート酸化膜１３は均一な厚みの熱酸化膜又
はｃｖｎ酸化膜を堆積する方法がとられている。この方
法によれば、ポＩＪＳｉ島１５と周囲の絶縁膜１２の界
面ではビームアニールによる微小な結晶成長が生じてい
るのと、界面自体の不安定さのために、トランジスタを
形成した場合に界面でのリーク等による特性の劣化が問
題となっていた。At this time, the gate oxide film 13 is formed by depositing a thermal oxide film or a CVN oxide film with a uniform thickness. According to this method, minute crystal growth occurs at the interface between the poIJSi island 15 and the surrounding insulating film 12 due to beam annealing, and the interface itself is unstable, so when a transistor is formed, the interface Deterioration of characteristics due to leaks, etc., had become a problem.
発明の目的
本発明は以上のような従来の問題に鑑み、ビームアニー
ルによりポＩＪＳｉ等の非単結晶島を良質の結晶領域に
したうえで、ゲート酸化膜の厚みをポリＳ上島と周囲の
絶縁物界面にて厚くする構造をとることによシ、良好な
トランジスタを形成することが可能となる。Purpose of the Invention In view of the above-mentioned conventional problems, the present invention has been developed by converting non-single-crystal islands such as polyS into high-quality crystal regions by beam annealing, and then reducing the thickness of the gate oxide film to the thickness of the polyS upper island and the surrounding insulation. By adopting a structure in which the thickness is increased at the material interface, it is possible to form a good transistor.
発明の構成
本発明は絶縁物にて囲まれた単結晶島にトランジスタを
形成するときに、ゲート酸化膜の厚みを単結晶島の中央
部で単結晶島と周囲の絶縁物との界面での厚みよりも薄
くする構造にょシ、特性の良いトランジスタの形成を可
能にし、高速、高密度のＬＳＩを製造可能とするもので
ある。Structure of the Invention The present invention, when forming a transistor on a single-crystal island surrounded by an insulator, changes the thickness of the gate oxide film at the center of the single-crystal island and at the interface between the single-crystal island and the surrounding insulator. This makes it possible to form a transistor with a thinner structure and better characteristics, and to manufacture high-speed, high-density LSIs.
実施例の説明
本発明の実施例をポリＳｉ島にトランジスタを形成する
場合について以下に説明する。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below regarding a case where a transistor is formed on a poly-Si island.
第２図は本発明の第１の実施例における半導体島の構造
を示す。第２図亀は平面図、ｂはＢ−Ｂ’線断面図であ
る。２１は絶縁物等の基板、２２は酸化膜、２３は周囲
を酸化膜２２に囲まれた結晶化Ｓｉ島である。この結晶
化Ｓｉ島２３０表面にゲート酸化膜２４を形成するが、
このときゲート中央部２６の酸化膜厚を結晶化Ｓｉ島２
３と酸化膜２２との界面よりも薄くなるように形成する
。さらにゲート酸化膜２４の表面にゲート電極となるポ
リＳｉ ２５ を形成する。FIG. 2 shows the structure of a semiconductor island in the first embodiment of the present invention. The tortoise in FIG. 2 is a plan view, and b is a sectional view taken along the line B-B'. 21 is a substrate such as an insulator, 22 is an oxide film, and 23 is a crystallized Si island surrounded by the oxide film 22. A gate oxide film 24 is formed on the surface of this crystallized Si island 230, but
At this time, the thickness of the oxide film in the central part 26 of the gate is
It is formed to be thinner than the interface between oxide film 22 and oxide film 22. Further, poly-Si 25 is formed on the surface of the gate oxide film 24 to serve as a gate electrode.
以上のように結晶化Ｓｉ島２３の中央部のゲート酸化膜
２６の厚さを他の部分の酸化膜厚２４′よりも薄くする
ことにより、トランジスタを形成したときにゲート電圧
をかけることにより、ゲート酸化膜直下にチャネルが形
成されるが、ゲート酸化膜が薄いほどチャネルが形成さ
れやすいため結晶化Ｓｉ島２３の中央部でチャネルが形
成されやすく、ソース、ドレイン電流が結晶化Ｓｉ島中
央部で流れやすく結晶化ａｌ島２３と周囲の絶縁物２２
との界面の影響を受けにくくなり、界面でのリーク等の
影響を低く抑えることができる。As described above, by making the thickness of the gate oxide film 26 in the central part of the crystallized Si island 23 thinner than the oxide film thickness 24' in other parts, by applying a gate voltage when forming a transistor, A channel is formed directly under the gate oxide film, but the thinner the gate oxide film is, the easier the channel is to be formed, so the channel is more likely to be formed in the center of the crystallized Si island 23, and the source and drain currents are more likely to be formed in the center of the crystallized Si island. The crystallized Al island 23 and the surrounding insulator 22 flow easily.
This makes it less susceptible to the influence of the interface with the material, and the influence of leaks at the interface can be suppressed to a low level.
第３図は本発明の第１の実施例の絶縁分離のトランジス
タの製造工程を説明するためのもので、まずＳ工、金属
あるいは絶縁物等の基板２１の表面に約１μｍの酸化膜
２２を形成する。次にポリＳ１膜２３を約０．５μｍ形
成したのちａ、保護酸化膜２７、チツ化膜２６を形成す
るｂｏそしてポリＳ１膜２３をチノ化膜２５をマスクと
して半分だけエツチングしてｃ、ＬＯＧＯ８酸化すると
ポリＳｉ島２３が形成できるｄｏこうした状態でレーザ
ビームｅによるポリＳｉ島２３の結晶化を行なって島２
３′を形成するｅ。次にこのＳｌ島２３′にフィールド
イオン注入を行なったのち、熱酸化膜を堆積することに
よりゲート酸化膜２７を形成する。このゲート酸化膜２
７のＳｉ島中央部２６をエツチングにて膜厚を薄くした
のち、ゲート電極２８を形成し、ソース°ドレインイオ
ン注入を行ない、Ａ７配線、パンシベーション膜を形成
してトランジスタが作製される。FIG. 3 is for explaining the manufacturing process of a transistor with insulation isolation according to the first embodiment of the present invention. First, an oxide film 22 of approximately 1 μm is formed on the surface of a substrate 21 made of S, metal, or insulator. Form. Next, after forming a poly S1 film 23 with a thickness of about 0.5 μm, a, a protective oxide film 27 and a nitride film 26 are formed, and only half of the poly S1 film 23 is etched using the tinoide film 25 as a mask. When oxidized, poly-Si islands 23 can be formed. In this state, the poly-Si islands 23 are crystallized by the laser beam e to form islands 2.
e forming 3'. Next, after performing field ion implantation into this Sl island 23', a gate oxide film 27 is formed by depositing a thermal oxide film. This gate oxide film 2
After etching the central portion 26 of the Si island 7 to reduce its film thickness, a gate electrode 28 is formed, source and drain ions are implanted, and an A7 wiring and a pansivation film are formed to fabricate a transistor.
第４図は本発明の第２の実施例を示す。所定の膜厚のゲ
ート酸化膜２４を形成したのち、Ｓｉ島中央部以外にの
みさらに絶縁膜２９を形成したものである。FIG. 4 shows a second embodiment of the invention. After forming a gate oxide film 24 of a predetermined thickness, an insulating film 29 is further formed only in areas other than the central portion of the Si island.
第５図はＳｉ島と周囲の絶縁物界面にのみ、ゲート酸化
膜上に絶縁膜を形成したものである。In FIG. 5, an insulating film is formed on the gate oxide film only at the interface between the Si island and the surrounding insulator.
以上のように、本実施例によれば完全絶縁分離のトラン
ジスタ形成に際し、Ｓｉ島と周囲の絶縁物との界面上部
のゲート酸化膜厚をＳｉ島中央部上部のゲート酸化膜厚
よりも厚くすることによって、ａｌ島と絶縁物界面の影
響を小さくすることができ、特性の良ｂトランジスタが
形成可能となる。As described above, according to this embodiment, when forming a completely isolated transistor, the gate oxide film thickness above the interface between the Si island and the surrounding insulator is made thicker than the gate oxide film thickness above the central part of the Si island. By doing so, the influence of the interface between the Al island and the insulator can be reduced, and a transistor with good characteristics can be formed.
発明の効果
以上のように、本発明は完全絶縁分離のトランジスタ形
成において、ａｌ島と周囲の絶縁物界面での特性の劣化
をさける構造によシ良質のトランジスタが形成でき、高
速、高密度のＬＳ・工が実現できる。Effects of the Invention As described above, the present invention makes it possible to form high-quality transistors with a structure that avoids deterioration of characteristics at the interface between the Al island and the surrounding insulator in the formation of transistors with complete insulation isolation, and to realize high-speed, high-density transistors. LS/engineering can be realized.
第１図（ａｌ 、 （ｂ）は従来例の完全絶縁分離ａｌ
島に形成したトランジスタの平面図、Ａ−Ａ’線断面図
、第２図（ａＪ 、 （ｂｌはゲート絶縁膜に凹凸を設
けた本発明の一実施例のトランジスタの平面図、Ｂ−Ｂ
′線断面図、第３図（ａｌ〜（ｇ）は第２図の構造のト
ランジスタの製造方法の工程断面図、第４図Ｔａ＋ 、
（ｂ）はゲート酸化膜の上にさらに部分的に絶縁物の
膜を設けた本発明の他の実施例のトランジスタの乎のト
ランジスタの平面図、Ｄ−Ｄ’線断面図である２１・・
・・・一基板、２２・・・・・・酸化膜、２３・・・・
ポリＳｉ、２３’・・・・・結晶化Ｓｌ島、２４・・・
・・ゲート酸化膜、２８・・・・ゲート電極、２６・・
・凹部、２９・・・、絶縁膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名筆
ＩＦ５４
５
第 ２ ＦＡ
第 ３ 図
第３図
第 ４ｔａ
２３′Figure 1 (al) and (b) show the conventional example of complete insulation isolation.
A plan view of a transistor formed in an island, a cross-sectional view taken along the line A-A', and FIG.
Figure 3 (al to (g) are process cross-sectional views of the method for manufacturing a transistor having the structure shown in Figure 2, Figure 4 Ta+,
21(b) is a plan view and a sectional view taken along the line DD' of a transistor according to another embodiment of the present invention in which an insulating film is further provided partially on the gate oxide film.
...One substrate, 22...Oxide film, 23...
Poly-Si, 23'...Crystallized Sl island, 24...
...Gate oxide film, 28...Gate electrode, 26...
- Concave portion, 29..., insulating film. Name of agent: Patent attorney Toshio Nakao and one other person
IF54 5 2nd FA 3rd figure 3rd figure 4ta 23'
Claims (2)
半導体素子が形成され、上記半導体素子のゲート酸化膜
厚が、上記半導体島領域と周囲の絶縁物領域の界面で、
ゲート中央部でのゲート酸化膜厚よシも厚くなっている
ことを特徴とする半導体集積回路装置。(1) A semiconductor element is formed in a semiconductor island region that has been made into a single crystal or has a large crystal grain, and the gate oxide film thickness of the semiconductor element is such that the thickness of the gate oxide film of the semiconductor element is at the interface between the semiconductor island region and the surrounding insulator region,
A semiconductor integrated circuit device characterized in that the thickness of the gate oxide film is thicker at the center of the gate.
半導体素子が形成され、上記半導体素子のゲート酸化膜
上の上記半導体島領域と周囲の絶縁物界面部分に誘電体
膜を形成したことを特徴とする半導体集積回路装置。(2) A semiconductor element is formed in a semiconductor island region that has been made into a single crystal or has a large crystal grain size, and a dielectric film is formed on the gate oxide film of the semiconductor element at the interface between the semiconductor island region and a surrounding insulator. A semiconductor integrated circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4435084A JPS60189266A (en) | 1984-03-08 | 1984-03-08 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4435084A JPS60189266A (en) | 1984-03-08 | 1984-03-08 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60189266A true JPS60189266A (en) | 1985-09-26 |
Family
ID=12689062
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4435084A Pending JPS60189266A (en) | 1984-03-08 | 1984-03-08 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60189266A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6144072A (en) * | 1994-11-02 | 2000-11-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device formed on insulating layer and method of manufacturing the same |
-
1984
- 1984-03-08 JP JP4435084A patent/JPS60189266A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6144072A (en) * | 1994-11-02 | 2000-11-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device formed on insulating layer and method of manufacturing the same |
| US6509583B1 (en) | 1994-11-02 | 2003-01-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device formed on insulating layer and method of manufacturing the same |
| US6653656B2 (en) | 1994-11-02 | 2003-11-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device formed on insulating layer and method of manufacturing the same |
| US7001822B2 (en) | 1994-11-02 | 2006-02-21 | Renesas Technology Corp. | Semiconductor device formed on insulating layer and method of manufacturing the same |
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