JPS61125087A - Insulated gate type field effect semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To eliminate transition region between an insulating region and an active region, by utilizing the facts that an element isolating insulating film agrees with the end part of a channel cutting impurity region, the substrate surface beneath the element isolating insulating film agrees with the substrate of a channel region, and said surfaces are flat. CONSTITUTION:On a substrate 11, a channel doping region 12 and a gate insulating film 13 are formed and thereafter a gate electrode material film 14 is formed. Then, a mask pattern in an active region is formed, and the material film 14 is etched. With a pattern 14a in the active region as a mask, a channel cutting region 15 is formed and a field insulating film 16 is grown. Then the insulating film 16 is etched so that the surface of the pattern 14a is exposed,and a material film 17 is formed. With a resist pattern formed on the material film 17 as a mask, a wiring material film is etched. On the active region, with the wiring pattern as masks, self-aligning etching of the material film pattern is performed. Then impurities are introduced in the substrate,and source and drain region 18 are formed. Thus, a transition region is not present between the element isolating insulating region and the active region, and element isolation, which does not disturb the crystal orientation of the substrate, can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate field effect semiconductor device (MIS type semiconductor device) and a method for manufacturing the same.

[Conventional technology]

The recent development of MIS type semiconductor devices has been remarkable, with advances in miniaturization and a dramatic increase in the degree of integration.

In this context, miniaturization of active elements is being promoted along with manufacturing techniques such as shallow junctions using ion implantation and anisotropic etching using reactive ion etching (hereinafter referred to as RIE). However, in order to achieve high integration, it is necessary not only to miniaturize each active element but also to miniaturize the regions separating each element from each other.

For this reason, techniques for separating fine elements have recently become particularly important, and various techniques for isolating elements have been devised. Typical examples known in the past are shown in Figure 100 (a) and (
Sometimes shown. FIG. 10(a) is a structural cross-sectional view of a method for forming an active region and an isolation region by removing a desired portion of a thick insulating film formed on a substrate to expose the surface of the substrate. Here, the inter-element isolation region is a thick insulating film 3 (hereinafter referred to as field insulating film, power distribution and between each element (generated parasitic MO8),
- It is constituted by an impurity region 2 (hereinafter referred to as a channel cut region) introduced to prevent the transistor effect. In the figure, 1 is a substrate and 4 is a gate insulating film.

Further, FIG. 10(b) shows an element isolation technique using selective oxidation, generally referred to as LOCO8 technique. Here, 6 is an oxidation-resistant film that is patterned in a shape that defines an active region. The channel cut region 2 is introduced outside the active region using the oxidation-resistant film pattern as a mask, and then the entire region is oxidized to form an element isolation oxide film 3t. The element isolation region is composed of the thick element isolation oxide film 3 and the channel cut region 2.

This technique has been widely used because of the advantage that channel cut regions and element isolation oxide films can be manufactured in a self-aligned manner.

[Problem that the invention seeks to solve]

However, the drawback of the first conventional example shown in FIG. 10(a) is that the channel cut region 2 and the element isolation insulating film 3 are not formed in a self-aligned manner. In other words, it must be designed with a certain margin between the channel cut region and the active region, which is inappropriate for miniaturization and high integration.

Furthermore, the following problems have been pointed out in the second conventional example shown in FIG. The first is the intrusion into the active region of the device isolation oxide film, which is called ``Bird's Beak''.

The width of this bird's beak, the transition region from the active region to the element isolation region, has become an obstacle to higher integration. In order to reduce the bird's beak width, an attempt was made to appropriately select the thickness of the oxide film 5 and nitride film 6 under the nitride film, but the nitridation phenomenon of the substrate, known as the white ribbon 1, became an obstacle and eliminated the bird's beak. It has been reported that this technique has little effect on the channel cut impurity due to the heat treatment during selective oxidation.
It has the disadvantage that it tends to cause a decline in transistor performance. Third, since this technology locally oxidizes the substrate, stress occurs during oxidation, causing disorder in the substrate crystals, that is, crystal defects.
, provoked. Defects generated during selective oxidation are a major cause of decreased yield and reliability of high-density integrated devices. It is an object of the present invention to provide an element isolation structure that does not have a transition region between active regions and does not disturb the crystallinity of a substrate, and a method for manufacturing the same.

[Failure to solve the problem]

The insulated gate field effect semiconductor device according to the first aspect of the present invention has an active region formed on the main surface of a semiconductor substrate of one conductivity type and composed of a source/drain impurity diffusion layer region and a channel region of opposite conductivity type. a gate insulating film provided in contact with the channel region; a gate electrode provided in contact with the gate insulating film and covering the channel region; and a substrate other than the channel region and the source/drain diffusion layer region. an insulated gate comprising: an element isolation insulating film provided in the element isolation insulating film; a channel cut impurity region having the same conductivity type as the substrate under the element isolation insulating film; and wiring electrically connecting the gate electrodes. In the type field effect semiconductor device, the ends of the element isolation insulating film and the channel/channel cut impurity region are aligned, and further, the substrate surface under the Vc element isolation insulating film and the substrate surface of the channel region are aligned and flat. It is composed of the following characteristics.

Further, the method for manufacturing an insulated gate field effect semiconductor device according to the invention of t42 of the present invention includes a step of introducing a channel doping impurity into a predetermined position of a substrate, a step of forming a gate insulating film on the substrate, and a step of forming a gate insulating film on the substrate. a step of patterning a gate electrode material pattern on an insulating film, a step of introducing a channel cut impurity t- using the gate electrode material as a mask, a step of forming an insulating film so as to fill in between the gate electrode material patterns, exposing the upper surface of the gate electrode material; forming a wiring material on the gate electrode material and the insulating film on the substrate; etching and patterning the wiring material and the gate electrode material; and a step of introducing impurities of opposite conductivity type into the substrate. [Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(e) are sectional views shown in order of steps to explain the structure and manufacturing method of an embodiment of the present invention.

First, in FIG. 1(a), 11 is a substrate, 13 is a gate insulating film, and 12 is a channel doping region. A channel doping region 12 and a gate insulating film 1 are formed on the substrate.
3, a gate electrode material film 14 is formed.

Next, as shown in FIG. 1(b), a mask pattern defining an active region is formed using the well-known 7-photoresist technique, and the gate electrode material film 14 is etched. For the etching of this gate electrode material film, anisotropic etching such as RIB etching is preferable because the dimensional deviation between the desired pattern and the mask pattern is small.

Next, a channel cut impurity is introduced into the substrate 11 as a pattern 14aQ mask defining the active region to form a channel cut region 15.

For device miniaturization, high-energy ion implantation is preferable for this method.

Next, as shown in FIG. 1C, an insulating film 16 is grown by, for example, bias sputter deposition.

At this time, the gate electrode material pattern 14a is covered with an insulating film VC, but the thickness of the insulating film varies.
It is important to form it thinly above the substrate and thickly above the substrate.

Such insulating film growth can be achieved by appropriately adjusting the bias conditions, for example, by bias silicon dioxide film sputtering. For example, under a bias condition of 200V, 2000V is applied on a 60OOX polycrystalline silicon film pattern.
'A. A silicon dioxide film of Vc7ooo1 could be grown on the substrate.

Next, as shown in FIG. 1(d), the insulating film 16 is etched so that the surface of the one gate electrode material pattern 14a is exposed. Thereafter, a wiring material film 17 is formed.

At this time, the thickness of the inter-element isolation insulating film 16a is determined by the initial thickness of the inter-element insulating film 16 grown on the substrate and the amount of etching of the insulating film. A channel cut region 15, which has already been introduced, is formed in a self-aligned manner on the lower substrate of the element isolation insulating film 16a. The parasitic transistor threshold value can be set to a desired value by the impurity concentration in this region and the thickness of the element isolation insulating film, and a rough and good element isolation breakdown voltage can be realized.

Next, as shown in FIG. 1(e), a desired gate electrode pattern and wiring pattern mask are formed on the wiring material film 17 by the well-known 7-photoresist technique. After that, the wiring material film is etched using the resist pattern as a mask, and the gate electrode material film pattern is etched on the active region.
Etching is performed in a self-aligned manner using the wiring pattern as a mask. Next, impurities are introduced into the substrate using a well-known technique such as ion implantation to form source/drain regions 18. At this time, the channel length of the gate electrode is defined by the gate electrode pattern 14b and the source-drain junction depth K. Therefore, in order to miniaturize the device, the etching of the wiring material film and gate electrode material film is performed using RIE, etc. It is also desirable that the source/drain junction be as shallow as possible when anisotropically etched.

FIG. 2 is a schematic plan view of the MIS type semiconductor device manufactured through the above steps, and FIG. 1(e) is a structural cross-sectional view of the plane A'. Further, the structural cross-sectional view along the BB' plane corresponds to the gt diagram (d).

After this (using a well-known technique, an insulating film is formed between the metal wiring and the interlayer insulating film, a part of the interlayer insulating film on the source/drain impurity region 18 and the gate electrode wiring 17a is removed to form an opening, and the metal electrode, A MIS type semiconductor device is obtained by forming metal wiring.

According to the structure described above, it is possible to eliminate the transition region from the active region to the element isolation region, such as a bird's beak, which occurs in the conventional LUCO8 technology.

Further, by using anisotropic etching such as HIE, it becomes possible to form the active region in a lump having a small dimensional deviation from the design value.

Further, after forming the channel cut impurity region, the channel cut impurity region can be formed in a self-aligned manner only under the element isolation insulating film, which is different from the method in which a thick oxide film is removed to form an active region.

Therefore, there is no need to allow for a design margin between the active region and the channel cut region, and furthermore, the number of 7 otolithography steps for introducing channel cut impurities can be reduced by 1 step.

Further, by using a low-temperature thick film formation technique such as a sputter silicon dioxide film deposition method, the heat treatment after the channel cut impurity treatment can be performed at a low temperature. Therefore, the intrusion of channel cut impurities into the active region can also be reduced.

As described above, according to the button of the present invention, the element isolation region can be formed in self-alignment with the active region, thereby increasing the degree of integration of the semiconductor integrated circuit device. Furthermore, it has the effect of suppressing the narrow channel effect and preventing a decline in the MID transistor performance.

Further, according to the present invention, the substrate is not locally oxidized to a large extent. Therefore, crystal defects caused by stress during selective oxidation, which were a problem with the LOGO8 technology, do not occur.

Therefore, it becomes possible to manufacture a highly reliable MIS type semiconductor device at a high yield.

FIGS. 3(a) and 3(b) are cross-sectional views shown in order of steps to explain another embodiment of the present invention and its manufacturing method. This embodiment describes an example in which FIGS. 1(a) to (e) are applied to a single channel type MI S#-type semiconductor device tff, whereas application to a complementary type rvl I S type semiconductor device will be explained. do.

FIG. 3(a) is a structural cross-sectional view of the step of introducing channel cut impurities into one channel region. Here, 20 is a mask material for channel cut impurity introduction, and 19
Reference numeral 15 indicates an impurity well of the γ■ type opposite to that of the substrate, and a channel cut impurity region 15 of the same quaternary conductivity type as the substrate. The subsequent manufacturing steps are carried out in the same manner as in the embodiment described above, and the element quantity I'11 according to the present invention is insulating film 16a and gate electrode 14b.
, a wiring 17a, a source/drain region of a conductivity type opposite to that of the substrate 11, and a source/drain region 18b of a conductivity type opposite to that of the impurity well 19 are formed. get. The effects of the present invention are similar to those described above in a complementary MIS type semiconductor device. However, complementary MIS type semiconductor devices generally have strict requirements for minute leakage, and one of the advantages of the present invention, which is less occurrence of crystal defects, further increases its effectiveness.

It should be noted that various materials and manufacturing methods can be used for K in carrying out the present invention.

For example, for the gate electrode material 14 and the wiring material 17, polycrystalline silicon, a high melting point metal material such as molybdenum or tungsten, or a silicate film of metal and silicon can be used. Further, as for the substrate material, a substrate made of silico 2 gallium arsenide or the like can be easily used. Furthermore, the gate insulating film may also be made of nitride or a vapor-deposited insulating film, instead of being an oxide of the substrate. The element isolation insulating film is also not limited to a silicon dioxide film formed by bias sputtering.

〔Effect of the invention〕

As explained above, according to the present invention, an element isolation structure and its manufacturing method that does not have a transition region between an element isolation insulating region and an active region and does not disturb the crystallinity of the substrate can be obtained, and an insulated gate electric field Effectively, it is possible to achieve miniaturization and high reliability of the semiconductor device.

[Brief explanation of drawings]

FIGS. 1(a) to 1(e) are cross-sectional views showing the structure of an embodiment of the present invention and the manufacturing method thereof in the order of steps;
FIG. 2 is a schematic plan view of a partial process of one embodiment of the present invention shown in FIG. 1, and FIGS. 3(a) and (b) illustrate the structure and manufacturing method of another embodiment of the present invention. 4(a) and Φ) are cross-sectional views showing an element isolation structure of a conventional insulated gate field effect semiconductor device. 1...Substrate, 2...Channel cut area, 3...Field insulating film, 4, 5...
...Gate insulating film, 6... Oxidation-resistant film, 11
...Substrate, 12...Channel doping region, 13...Gate insulating film, 14...
...Gate electrode material film, 14a...Gate electrode material pattern, 14b...Gate electrode pattern, 15...Channel cut region, 16.1
6a...Field insulating film, 17...
Wiring material film, 17a...gate 'lli electrode wiring, 18.18a...source-drain region, 1
9... Impurity well, 20... Mask material for channel stopper introduction. 10 Figure 2

Claims (2)

[Claims] (1) An active region consisting of a source/drain impurity diffusion layer region and a channel region of the opposite conductivity type formed on the main surface of a semiconductor substrate of one conductivity type, and a gate insulator provided in contact with the channel region. a gate electrode provided in contact with the gate insulating film and covering the channel region; an inter-element isolation insulating film provided on the substrate other than the channel region and the source/drain diffusion layer region; In an insulated gate field effect semiconductor device comprising a channel-cut impurity region of the same conductivity type as the substrate and a wiring electrically connecting the gate electrodes under the isolation insulating film, the inter-element isolation insulating film and the channel An insulated gate field effect semiconductor device characterized in that the ends of the cut impurity regions coincide with each other, and further, the substrate surface under the element isolation insulating film and the substrate surface of the channel region coincide and are flat. (2) A step of introducing channel doping impurities into a predetermined position of the substrate, a step of forming a gate insulating film on the substrate, a step of patterning a gate electrode material pattern on the gate insulating film, and a step of forming a gate electrode material pattern on the gate insulating film. a step of introducing a channel cut impurity using the material as a mask; a step of forming an insulating film so as to fill in between the gate electrode material patterns; a step of exposing the upper surface of the gate electrode material; a step of forming a wiring material on the insulating film; a step of etching and patterning the wiring material and the gate electrode material; and a step of introducing an impurity of a conductivity type opposite to that of the substrate into the substrate. A method for manufacturing an insulated gate field effect semiconductor device.