JPS60189155U - Data clock regeneration circuit - Google Patents
Data clock regeneration circuitInfo
- Publication number
- JPS60189155U JPS60189155U JP7656984U JP7656984U JPS60189155U JP S60189155 U JPS60189155 U JP S60189155U JP 7656984 U JP7656984 U JP 7656984U JP 7656984 U JP7656984 U JP 7656984U JP S60189155 U JPS60189155 U JP S60189155U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- regeneration circuit
- data clock
- clock regeneration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のデータクロック再生回路を用いたＣＡＴ
Ｖシステムにおける受信機の一例を示すブロック図、第
２図はこの考案の一実施例を示すブロック図、第３図は
第２図の動作説明に供するための信号波形図、第４図は
第２図の具体的な回路構成の一例を示す回路構成図であ
る。
２？はデータ比較器、２３は移相器、２４，２５はイク
スクルーシブオア（Ｆ ＯＲ）回路、２６はローパスフ
ィルタ、２７は増幅器、２８は電圧制御型発塀器、２９
は１／２分周器、３０．３４はＤ型フリップフロップ回
路、３１はインバータである。Figure 1 shows a CAT using a conventional data clock recovery circuit.
FIG. 2 is a block diagram showing an example of a receiver in the V system, FIG. 2 is a block diagram showing an embodiment of this invention, FIG. 3 is a signal waveform diagram for explaining the operation of FIG. FIG. 2 is a circuit configuration diagram showing an example of a specific circuit configuration of FIG. 2; 2? is a data comparator, 23 is a phase shifter, 24 and 25 are exclusive OR (FOR) circuits, 26 is a low-pass filter, 27 is an amplifier, 28 is a voltage-controlled oscillator, 29
is a 1/2 frequency divider, 30.34 is a D-type flip-flop circuit, and 31 is an inverter.
Claims (1)
発生する移相手段と、該移相手段の出力を加算する加算
手段と、基準信号を発生する発振手段と、該発振手段の
出力と上記加算手段の出力を位相比較し、−波した信号
を上記発振手段に制御信号として供給する制御手段と、
上記発振手段、の出力及び該出力を反転した信号が夫々
入力信号及びクロック信号として供給されるフリップフ
ロップ手段とを備え、該フリップフロップ手段の出力側
に上記データ信号より再生されたクロック信号を得るよ
うにしたことを特徴とするデータクロック再生回路。a phase shifter for waveform shaping a data signal to generate a signal having a predetermined phase difference; an addition means for adding the outputs of the phase shifter; an oscillation means for generating a reference signal; A control means that compares the phases of the output of the addition means and supplies a negative signal to the oscillation means as a control signal;
and flip-flop means to which the output of the oscillation means and a signal obtained by inverting the output are supplied as an input signal and a clock signal, respectively, and a clock signal reproduced from the data signal is obtained on the output side of the flip-flop means. A data clock regeneration circuit characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7656984U JPS60189155U (en) | 1984-05-25 | 1984-05-25 | Data clock regeneration circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7656984U JPS60189155U (en) | 1984-05-25 | 1984-05-25 | Data clock regeneration circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60189155U true JPS60189155U (en) | 1985-12-14 |
Family
ID=30618828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7656984U Pending JPS60189155U (en) | 1984-05-25 | 1984-05-25 | Data clock regeneration circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60189155U (en) |
-
1984
- 1984-05-25 JP JP7656984U patent/JPS60189155U/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS60189155U (en) | Data clock regeneration circuit | |
| JPH0650883B2 (en) | Demodulation circuit for DPSK modulation data | |
| JPS6067556U (en) | clock regeneration circuit | |
| JPS6068742U (en) | automatic frequency control circuit | |
| JPS5929812U (en) | FM modulation circuit | |
| JPS60145721U (en) | modulation circuit | |
| JPS62164651U (en) | ||
| JPS5893048U (en) | oscillation circuit | |
| JPS59195883U (en) | RF converter color subcarrier oscillation circuit | |
| JPS60108045U (en) | pulse shaping circuit | |
| JPS609311U (en) | PLL-PLL type demodulation circuit | |
| JPS5883843U (en) | Multipath interference removal circuit | |
| JPS59129228U (en) | PLL circuit | |
| JPS6043031U (en) | frequency converter | |
| JPS5927639U (en) | Phase throttle loop circuit | |
| JPS5847928U (en) | Reference clock signal generation circuit for data processing equipment | |
| JPS6047357U (en) | Clock generation circuit | |
| JPS5849285U (en) | timer clock circuit | |
| JPS5937893U (en) | phase synchronized circuit | |
| JPH03115955U (en) | ||
| JPS58144928U (en) | phase lock droop | |
| JPH04115363U (en) | Digital interface device | |
| JPS588240U (en) | phase synchronized circuit | |
| JPS59127344U (en) | exciter | |
| JPS6090953U (en) | Frequency deviation modulator carrier signal generator |