JPS60187536U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS60187536U
JPS60187536U JP1984074726U JP7472684U JPS60187536U JP S60187536 U JPS60187536 U JP S60187536U JP 1984074726 U JP1984074726 U JP 1984074726U JP 7472684 U JP7472684 U JP 7472684U JP S60187536 U JPS60187536 U JP S60187536U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
substrate
semiconductor pellet
semiconductor
side wall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984074726U
Other languages
Japanese (ja)
Inventor
慎一 鈴木
Original Assignee
関西日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 関西日本電気株式会社 filed Critical 関西日本電気株式会社
Priority to JP1984074726U priority Critical patent/JPS60187536U/en
Publication of JPS60187536U publication Critical patent/JPS60187536U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743—Apparatus for manufacturing layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例を示す要部平面図、第２図は
第１図の半導体装置の製造途中でのリードフレームの部
分平面図、第３図及び第４図は第２図のＣ−Ｃ線に沿う
各状態での断面図、゛第５図は本考案の他の実施例を示
す半導体装置の製造途中でのリードフレームの部分平面
図、第６図及び第７図は従来の半導体装置の要部平面図
及びＡ−Ａ線に沿う断面図、第８図は第６図の半導体装
置の等価回路図、第９図は第６図の半導体装置製造に使
用するリードフレームの部分平面図、第１０図は第９図
のリードフレームの製造途中の部分拡大図、第１１図及
び第１２図は第１０図のＢ−Ｂ線に沿う各状態での断面
図を示す。 ４、・・・・・・半導体ペレットマウント部、４′・・
・・・・エツジ、７・・・・・・半導体ペレット、１０
・・・・・・半田、１１′・・・・・・エツジ。 よ＃ａ−（ ＴＴ Ｊ＋（λも　　　　　。FIG. 1 is a plan view of a main part showing an embodiment of the present invention, FIG. 2 is a partial plan view of a lead frame in the middle of manufacturing the semiconductor device shown in FIG. 1, and FIGS. 3 and 4 are views shown in FIG. 5 is a partial plan view of a lead frame in the middle of manufacturing a semiconductor device showing another embodiment of the present invention, and FIGS. 6 and 7 are sectional views taken along line C-C of A plan view of essential parts of a conventional semiconductor device and a sectional view taken along line A-A, FIG. 8 is an equivalent circuit diagram of the semiconductor device shown in FIG. 6, and FIG. 9 is a lead frame used for manufacturing the semiconductor device shown in FIG. 6. FIG. 10 is a partial enlarged view of the lead frame in FIG. 9 during manufacture, and FIGS. 11 and 12 are cross-sectional views taken along line B--B in FIG. 10. 4,... Semiconductor pellet mount section, 4'...
...Edge, 7...Semiconductor pellet, 10
...Handa, 11'...Etsuji. Yo#a-(TT J+(λ also.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板の半導体ペレットマウント部上に半田を介して半導
体ペレットをマウントしたものにおいて、前記半導体ペ
レットマウント部を基板側壁近傍に位置させ半田の一部
を基板側壁と隣接部分に食み出させたことを特徴とする
半導体装置。In a device in which a semiconductor pellet is mounted on a semiconductor pellet mount portion of a substrate via solder, the semiconductor pellet mount portion is located near a side wall of the substrate so that a part of the solder protrudes into the side wall of the substrate and the adjacent portion. Characteristic semiconductor devices.
JP1984074726U 1984-05-21 1984-05-21 semiconductor equipment Pending JPS60187536U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984074726U JPS60187536U (en) 1984-05-21 1984-05-21 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984074726U JPS60187536U (en) 1984-05-21 1984-05-21 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS60187536U true JPS60187536U (en) 1985-12-12

Family

ID=30615282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984074726U Pending JPS60187536U (en) 1984-05-21 1984-05-21 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS60187536U (en)

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