JPS60186043A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS60186043A
JPS60186043A JP59041608A JP4160884A JPS60186043A JP S60186043 A JPS60186043 A JP S60186043A JP 59041608 A JP59041608 A JP 59041608A JP 4160884 A JP4160884 A JP 4160884A JP S60186043 A JPS60186043 A JP S60186043A
Authority
JP
Japan
Prior art keywords
pellet
integrated circuit
cap
iron
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59041608A
Other languages
Japanese (ja)
Inventor
Sakae Yatagai
谷田貝　栄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59041608A priority Critical patent/JPS60186043A/en
Publication of JPS60186043A publication Critical patent/JPS60186043A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

PURPOSE:To eliminate a finger contact of a semiconductor pellet and to protect against an electric field and a magnetic field disturbance by placing a protective cap plated with copper with iron as a material on a semiconductor pellet. CONSTITUTION:A semiconductor pellet 6 is placed on a hybrid integrated circuit thickness substrate 3, and connected with a conductive passage on the substrate via bonding wirings 7. Further, a protective cap 1 is coated on the pellet 6. The cap 1 is made of iron, and plated with copper, temporarily attached with resin 5, cap leads 2, 2 are formed by soldering 8 on a ground conductive path 4 on the substrate by a solder dip by soldering. A protective cap 1 is disposed at the ground potential, has an electric field shielding effect, and performs the role of a jumper wire of low resistance. Further, since the iron is used, a magnetic field shielding effect is provided, and since the pellet is coated with the bonding wirings, the wirings are not disconnected by the external pressure due to the finger contact.

Description

【発明の詳細な説明】 イ、産業上の利用分野 本発明は、混成集積回路用厚膜回路基板に集積回路やト
ランジスタなどの半導体ベレットを搭載して構成した混
成集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a hybrid integrated circuit constructed by mounting semiconductor pellets such as integrated circuits and transistors on a thick film circuit board for the hybrid integrated circuit.

口、従来技術 従来、上述のような混成集積回路では、シリコン系の樹
脂でベレットを保護し、その後部品搭載を行う製造工程
が一般的にとられている。しかしながら、このシリコン
保護体では、リード付け、部品搭載などの後工程におい
て、グリコート衣面に不用意に手を触れり場合、ワイヤ
切れなどの不良を引起すという欠点があった。BACKGROUND OF THE INVENTION Conventionally, for hybrid integrated circuits as described above, a manufacturing process has generally been adopted in which the pellet is protected with a silicone resin and then components are mounted. However, this silicone protector has a drawback in that if the glycoat coated surface is carelessly touched during post-processes such as lead attachment and component mounting, defects such as wire breakage may occur.

ハ１発明の目的 本発明の目的は、厚膜回路基板に半導体ベレットを搭載
後の後工程において、前記半導体ベレットに触手が起ら
ないような、また、電界および磁界妨害からも保護され
た混成集積回路を提供するにある。C1 Object of the Invention An object of the present invention is to provide a hybrid structure that prevents tentacles from occurring on the semiconductor pellet in the post-process after mounting the semiconductor pellet on a thick film circuit board, and that is also protected from electric and magnetic field disturbances. To provide integrated circuits.

二１発明の構成 本発明によれは、半導体ベレットを搭載した厚膜回路基
板に対し、前記半導体ベレットを被って、鉄を材料とし
てその上に銅メッキを施した保護キャップを搭載した混
成集積回路が得られる。21. Structure of the Invention According to the present invention, a hybrid integrated circuit is provided, in which a thick film circuit board on which a semiconductor pellet is mounted is mounted with a protective cap made of iron and plated with copper on top of the semiconductor pellet. is obtained.

ホ、実施例 つぎに本発明を実施例によシ説明する。E, Example Next, the present invention will be explained using examples.

第１図は本発明の一実施例の平面図、第２図は第１図の
要部断面図である。第１図と第２図において、混成集積
回路厚膜基板３上に半導体ベレット６が搭載され、ボン
ディングワイヤ７でもって゛基板上の導電路と接続がと
られている。さらに、半導体ベレット６を被って、保護
キャップ１がかぶせられている。保護キャップ１は、鉄
を材料としてその上に銅メッキが施されたものマ！′あ
って、樹脂５によシ仮付は後、キャップリード２．２の
部分を、基板上のグランド用導電路４に、ノ・ンダデイ
ソプによりハンダ伺げ８がなされている。FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a sectional view of a main part of FIG. In FIGS. 1 and 2, a semiconductor bullet 6 is mounted on a hybrid integrated circuit thick film substrate 3, and is connected to a conductive path on the substrate by a bonding wire 7. Further, a protective cap 1 is placed over the semiconductor pellet 6. The protective cap 1 is made of iron with copper plating applied on top! After temporarily attaching the resin 5, the cap lead 2.2 is soldered to the ground conductive path 4 on the board using a solder paste.

へ１発明の効果 このような本発明の混成集積回路では、保護キャップ１
はグランド電位となシ、電界シールド効果を有する。ま
た、低抵抗のジャンパー線の役目を果す。さらに、妖が
］オ科であるため、磁界シールド効果があり、また、半
導体ベレットを、ボンディングワイヤ部マで含めて被っ
ているので、触手などの外部圧力イ１ワイヤ切れを起す
こともない。1 Effects of the Invention In the hybrid integrated circuit of the present invention, the protective cap 1
is at ground potential and has an electric field shielding effect. It also serves as a low resistance jumper wire. Furthermore, since the monster is an insect, there is a magnetic field shielding effect, and since the semiconductor bullet is covered with the bonding wire part, external pressure such as tentacles will not cause the wire to break.

なお、半導体ベレットが複数個ある場合には、保護ギャ
ップの形状は半球状にとどまらず、複数個を含む形状に
作成することもできる。また、ジー’Ｉ’７パ用キャッ
プリードは２本にとどまらず３本以上あってもよい。In addition, when there are a plurality of semiconductor pellets, the shape of the protective gap is not limited to a hemispherical shape, but can also be created to include a plurality of pellets. Furthermore, the number of cap leads for G'I'7P is not limited to two, but may be three or more.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の平面図、第２図は第１図の
要部断面図である。 １・・・・・・保瞳キャップ、２・・・・・・キャップ
リード、３・・・・・・混成集積回路用基板、４・・・
・・・グランド用導電路、５・・・・・・仮付は樹脂、
６・・・・・・半導体ベレット、７・・・・・・ボンデ
ィングワイヤ、８・・・・・・はんだ付けはんだ。FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a sectional view of a main part of FIG. DESCRIPTION OF SYMBOLS 1... Eye protection cap, 2... Cap lead, 3... Substrate for hybrid integrated circuit, 4...
...Ground conductive path, 5...Temporarily attached with resin,
6... Semiconductor pellet, 7... Bonding wire, 8... Soldering solder.

Claims (1)

【特許請求の範囲】[Claims] 混成集積回路用基板に半導体ベレットを搭載してなる混
成集積回路において、前記半導体ベレットを被って、鉄
を材料としてその上に銅メッキを施した保岐キャップを
前記基板に搭載したことを特徴とする混成集積回路。A hybrid integrated circuit comprising a semiconductor bullet mounted on a hybrid integrated circuit board, characterized in that a Hoki cap made of iron and plated with copper is mounted on the board, covering the semiconductor bullet. hybrid integrated circuit.
JP59041608A 1984-03-05 1984-03-05 Hybrid integrated circuit Pending JPS60186043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59041608A JPS60186043A (en) 1984-03-05 1984-03-05 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59041608A JPS60186043A (en) 1984-03-05 1984-03-05 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS60186043A true JPS60186043A (en) 1985-09-21

Family

ID=12613068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59041608A Pending JPS60186043A (en) 1984-03-05 1984-03-05 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS60186043A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150282392A1 (en) * 2014-04-01 2015-10-01 Baomin Liu Combined electromagnetic shield and thermal management device
CN110459530A (en) * 2019-07-26 2019-11-15 南通通富微电子有限公司 Encapsulating structure
CN110534502A (en) * 2019-07-26 2019-12-03 南通通富微电子有限公司 Encapsulating structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150282392A1 (en) * 2014-04-01 2015-10-01 Baomin Liu Combined electromagnetic shield and thermal management device
US9420734B2 (en) * 2014-04-01 2016-08-16 Advanced Micro Devices, Inc. Combined electromagnetic shield and thermal management device
CN110459530A (en) * 2019-07-26 2019-11-15 南通通富微电子有限公司 Encapsulating structure
CN110534502A (en) * 2019-07-26 2019-12-03 南通通富微电子有限公司 Encapsulating structure
CN110459530B (en) * 2019-07-26 2021-07-02 南通通富微电子有限公司 Packaging structure
CN110534502B (en) * 2019-07-26 2021-12-10 南通通富微电子有限公司 Packaging structure

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