JPH03206691A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH03206691A JPH03206691A JP188190A JP188190A JPH03206691A JP H03206691 A JPH03206691 A JP H03206691A JP 188190 A JP188190 A JP 188190A JP 188190 A JP188190 A JP 188190A JP H03206691 A JPH03206691 A JP H03206691A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- resin
- metallic
- insulating substrate
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000011347 resin Substances 0.000 claims abstract description 11
- 229920005989 resin Polymers 0.000 claims abstract description 11
- 230000000694 effects Effects 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 4
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract 2
- 239000010931 gold Substances 0.000 abstract 1
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 239000004020 conductor Substances 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路に関し、特にシールド性を必要と
する半導体素子を搭載した混成集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit, and particularly to a hybrid integrated circuit mounted with a semiconductor element requiring shielding properties.
従来、この種の混成集積回路は、第３図に示すように、
絶縁性基板１上に半導体素子３を搭載し金線４を用いて
ワイヤボンディング法により接続し樹脂５でコーティン
グする。次に抵抗，コンデンサ等の受動素子７を搭載し
て半田付け接続し、絶縁性基板上の一辺にクリップ端子
８を取付け絶縁基板１上の外部接続端子にクリップ端子
８を半田付け固定した後、金属ケース１０に封入して金
属ケース１０内に樹脂１１を封入し金属ケース１０を接
地することによりシールド効果を持たせて外来ノイズか
らの遮断及び相互干渉を軽減させていた。Conventionally, this type of hybrid integrated circuit, as shown in FIG.
A semiconductor element 3 is mounted on an insulating substrate 1, connected by wire bonding using gold wire 4, and coated with resin 5. Next, passive elements 7 such as resistors and capacitors are mounted and connected by soldering, a clip terminal 8 is attached to one side of the insulating board, and the clip terminal 8 is soldered and fixed to the external connection terminal on the insulating board 1. By enclosing a resin 11 in the metal case 10 and grounding the metal case 10, a shielding effect is provided, thereby blocking external noise and reducing mutual interference.
上述した従来の混成集積回路は、部品を搭載した絶縁性
基板を金属ケースに封入しているので外形寸法が大きく
なり高密度実装に必要な混成集積回路の小型化に対応で
きないという欠点がある。The above-mentioned conventional hybrid integrated circuit has the drawback that the insulating substrate on which the components are mounted is enclosed in a metal case, so the external dimensions are large and the hybrid integrated circuit cannot be miniaturized, which is necessary for high-density packaging.
本発明は、半導体素子及び電気部品を搭載した絶縁性基
板と、この絶縁性基板上の外部接続され前記絶縁性基板
に固着されるクリップ端子と前記半導体素子及び電気部
品を覆って前記絶縁性基板の外周に形成される外装樹脂
とを備える混成集積回路に於いて、搭載部品のうちシー
ルド効果が必要な半導体素子部にのみシールド用金属カ
バーを有している。The present invention provides an insulating substrate on which a semiconductor element and an electric component are mounted, a clip terminal on the insulating substrate that is externally connected and fixed to the insulating substrate, and a clip terminal that covers the semiconductor element and the electric component and covers the insulating substrate. In a hybrid integrated circuit including an exterior resin formed on the outer periphery of the hybrid integrated circuit, a shielding metal cover is provided only on the semiconductor element portion of the mounted components that requires a shielding effect.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の断面図である．第１図
に示すように、厚さ０．６３５ｍＩＩ１のセラミック基
板ｌに銀一パラジウムからなる厚さ約１０μｍの導体パ
ターン２を形威し半導体素子３を搭載し、例えば線径３
０μｍの金線４によりワイヤボディング法にて接続する
。次に半導体素子３を保護するためにフェノール樹脂５
を塗布し１５０℃の恒温槽内で１〜３時間放置し加熱硬
化させる。次に金属製のシールド力バー６と抵抗又はコ
ンデンサなどの受動素子７を搭載し半田リフロー法によ
り半田付けする。次にセラミック基板１上の縁部に形成
した外部接続端子ランドにクリップ端子８を取り付けて
半田接続しクリップ端子８の先端部を露出した状態で全
体にフェノール外装樹脂９を塗布し１５０℃の恒温槽内
で１〜３時間放置し加熱硬化させて戒る。FIG. 1 is a sectional view of the first embodiment of the present invention. As shown in FIG. 1, a conductor pattern 2 made of silver and palladium with a thickness of about 10 μm is formed on a ceramic substrate l with a thickness of 0.635 mII1, and a semiconductor element 3 is mounted thereon.
Connection is made using a wire boarding method using a gold wire 4 of 0 μm. Next, in order to protect the semiconductor element 3, a phenol resin 5 is used.
is applied and left in a constant temperature bath at 150°C for 1 to 3 hours to heat and harden. Next, a metal shielding force bar 6 and a passive element 7 such as a resistor or a capacitor are mounted and soldered using a solder reflow method. Next, the clip terminal 8 is attached to the external connection terminal land formed on the edge of the ceramic substrate 1 and connected by soldering. With the tip of the clip terminal 8 exposed, a phenol exterior resin 9 is applied to the entire surface and kept at a constant temperature of 150°C. Leave in the tank for 1 to 3 hours to heat and harden.
第２図は本発明の第２の実施例の断面図である．第２図
に示すように、この実施例ではセラミック基板に於いて
半導体素子３と反対側のセラミック基板１の面に導体パ
ターン２を形成している。この実施例では半導体素子３
の裏側からのノイズに対しても遮断できる利点がある。FIG. 2 is a sectional view of a second embodiment of the present invention. As shown in FIG. 2, in this embodiment, a conductor pattern 2 is formed on the surface of the ceramic substrate 1 opposite to the semiconductor element 3. In this embodiment, the semiconductor element 3
It has the advantage of being able to block out noise from the back side.
以上説明したように本発明はシールド効果を必要とする
半導体素子上にのみシールド力バーを形成し全体を樹脂
コートすることにより金属ケースが不要となり小型化が
達成できる効果がある．またシールド力バーと受動素子
は同時に搭載し半田リフロ一により半田付接続するので
工程が短縮できるという効果もある。As explained above, the present invention has the effect of forming a shielding force bar only on a semiconductor element that requires a shielding effect and coating the entire body with resin, thereby eliminating the need for a metal case and achieving miniaturization. In addition, the shielding force bar and the passive element are mounted at the same time and connected by soldering using solder reflow, which has the effect of shortening the manufacturing process.
第１図は本発明の第１の実施例の断面図、第２図は本発
明の第２の実施例の断面図、第３図は従来構造の断面図
である，
１・・・セラミック基板、２・・・導体パターン、３・
・・半導体素子、４・・・金線、５・・・フェノール樹
脂、６・・・シールド力バー ７・・・受動素子、８・
・・クリップ端子、９・・・外装樹脂、１０・・・金属
ケース、１１・・・樹脂，Fig. 1 is a sectional view of a first embodiment of the present invention, Fig. 2 is a sectional view of a second embodiment of the invention, and Fig. 3 is a sectional view of a conventional structure. 1... Ceramic substrate , 2... conductor pattern, 3.
... Semiconductor element, 4... Gold wire, 5... Phenol resin, 6... Shielding force bar 7... Passive element, 8...
...Clip terminal, 9...Exterior resin, 10...Metal case, 11...Resin,
Claims (1)
絶縁性基板上の外部接続端子に接続固着されるクリップ
端子と、前記半導体素子及び電気部品を覆って前記絶縁
性基板の外周に形成される外装樹脂とを備える混成集積
回路において、前記搭載部品のうちシールド効果を必要
とする半導体素子部にのみシールド用金属カバーを有す
ることを特徴とする混成集積回路。An insulating substrate on which a semiconductor element and an electric component are mounted, a clip terminal connected and fixed to an external connection terminal on the insulating substrate, and a clip terminal formed on the outer periphery of the insulating substrate to cover the semiconductor element and the electric component. What is claimed is: 1. A hybrid integrated circuit comprising an exterior resin, wherein a shielding metal cover is provided only on a semiconductor element portion of the mounted components that requires a shielding effect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP188190A JPH03206691A (en) | 1990-01-08 | 1990-01-08 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP188190A JPH03206691A (en) | 1990-01-08 | 1990-01-08 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03206691A true JPH03206691A (en) | 1991-09-10 |
Family
ID=11513909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP188190A Pending JPH03206691A (en) | 1990-01-08 | 1990-01-08 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03206691A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5323533A (en) * | 1991-03-26 | 1994-06-28 | Thomson-Csf | Method of producing coaxial connections for an electronic component, and component package |
| US5400949A (en) * | 1991-09-19 | 1995-03-28 | Nokia Mobile Phones Ltd. | Circuit board assembly |
| WO2003041163A1 (en) * | 2001-11-09 | 2003-05-15 | 3D Plus | Device for the hermetic encapsulation of a component that must be protected against all stresses |
-
1990
- 1990-01-08 JP JP188190A patent/JPH03206691A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5323533A (en) * | 1991-03-26 | 1994-06-28 | Thomson-Csf | Method of producing coaxial connections for an electronic component, and component package |
| US5400949A (en) * | 1991-09-19 | 1995-03-28 | Nokia Mobile Phones Ltd. | Circuit board assembly |
| US5442521A (en) * | 1991-09-19 | 1995-08-15 | Nokia Mobile Phones Ltd. | Circuit board assembly |
| WO2003041163A1 (en) * | 2001-11-09 | 2003-05-15 | 3D Plus | Device for the hermetic encapsulation of a component that must be protected against all stresses |
| FR2832136A1 (en) * | 2001-11-09 | 2003-05-16 | 3D Plus Sa | DEVICE FOR HERMETIC ENCAPSULATION OF COMPONENT TO BE PROTECTED FROM ANY STRESS |
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