JPS60170328A - Analog-to-digital converting device - Google Patents

Abstract

PURPOSE:To perform conversion of high resolution with a small number of comparators, by repeatedly operating plural comparators when an analog signal is converted into a digital signal. CONSTITUTION:In the first place, a switch (S) 18 is set to the (a) side by a clock source 17 and signals from an analog signal input section 13 are inputted in (n) sets of comparators 14. In the remaining input section of the comparators 14 a reference voltage produced by a power source 11 and series resistance 12 is inputted and the compared result between the signals and reference voltage is inputted in a shift register 22 through an encoder 21 after respectively passing through AND circuits 15. The output of the AND circuits 15 controls (n) pieces of Ss 16, selects a reference voltage to be inputted in the comparators 14, and inputs the selected reference voltage in a differential amplifier 19. The amplifier 19 amplifies a value which is obtained by subtracting one of reference voltages from a value outputted from a delay circuit 20 by (n+1) times and outputs the amplified result. Then the S 18 is set to the (b) side by the clock source 17 and the output of the amplifier 19 is made to be inputted. This operation is repeated for (m) times and, as a result, conversion of high resolution can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an analog/digital conversion device using a plurality of comparators.

Conventional configuration and ranking points The following describes a conventional analog/digital conversion device.

Figure 1 is a block diagram of an analog/digital conversion device using multiple comparators, where 1 is a power supply, 2 is a series resistor, 3 is an analog signal input section, 4 is a plurality of comparators, 6 is an encoder, and 6 is a digital converter. This is a signal output section.

The operation of the conventional analog/digital converter configured as described above will be described below.

First, a plurality of reference voltages are generated from a power supply 1 and a series resistor 2 and inputted to a plurality of comparators 4, respectively.

The plurality of comparators 4 compare the magnitude of the analog signal voltage input from the analog signal input section 3 with the reference voltage. The encoder 5 whose result is made with a logic circuit
A necessary digital signal input to the digital signal output section 6 is outputted from the digital signal output section 6.

However, in the above configuration, if the resolution is n bits, (2-1) ノ=+nno< latators are required, and the problem is that the number of comparators increases dramatically when trying to obtain high resolution. It had

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems, and an object thereof is to provide an analog/digital conversion device that can configure a high-resolution device with a small number of comparators.

Structure of the Invention The present invention comprises a power supply, a series resistor for generating a plurality of reference voltages using the power supply, a plurality of comparators that compare the magnitudes of the plurality of reference voltages and an analog signal, and the plurality of comparators. a plurality of AND circuits whose inputs are the outputs of the plurality of AND circuits, a plurality of switches controlled by the outputs of the plurality of AND circuits, an encoder whose input is the output of the AND circuits, and a shift register whose input is the output of the encoder. a switch that selects an analog signal to be input to the plurality of comparators; a delay circuit that delays the analog signal; and a differential amplifier that receives the reference voltage selected by the plurality of switches and the output of the delay circuit. This is an analog/digital conversion device equipped with a switch for selecting the analog signal and a clock source for controlling the shift register. A high-resolution device can be constructed using a comparator.

DESCRIPTION OF EMBODIMENTS FIG. 2 shows a block diagram of an analog/digital conversion device in an embodiment of the present invention.

In FIG. 2, 11 is a power supply, 12 is a series resistor, 13 is an analog signal input section, 14 is n number of converters, 1
6 is n two-person AND circuits, 16 x n switches, 17 is a clock source, 18 is a switch, 19 x differential amplifier, 20 is a delay circuit, 21 is an encoder, 22 is a shift register, 23 is a digital This is a signal output section.

The operation of the analog/digital converter of this embodiment configured as described above will be described below.

With the clock source 1T, the switches 18 become individual a,
Analog signals are inputted from the analog signal input section 13 to the n concise signals 14, respectively. Further, n reference voltages generated by the power supply 11 and the series resistor 12 are respectively input to the remaining one input section of the n comparators 14. The result of comparing the size in each comparator is A
The signal passes through the ND circuit 15, is converted into a binary number by the encoder 21, and is input to the shift register 22. Sunda AND circuit 1
The output of 5 controls n switches 16, and inputs the maximum reference voltage among the n reference voltages whose magnitudes are compared with the analog signal and which are smaller than the analog signal to one input of the differential amplifier. let The other input section has a delay circuit 2.
Input from 0.

This is the analog signal that was previously input to the delay circuit 20 from the analog signal input section 13. The differential amplifier 19 multiplies (n+1) the value obtained by subtracting one value of the reference voltage from the value output from the delay circuit 20 and outputs the result.

Since the switch 18 is set to the [b side] immediately after the start of analog/digital conversion by the clock source 1γ, the output of the differential amplifier is inputted to the n comparators 14 [. Then, the value converted into a binary number in the same manner as before is input to the shift register 22 which is controlled by the output of the clock source 17.

Initially, the analog signal input from the analog signal input section 13 is input to the delay circuit 20, but thereafter the output of the differential amplifier 19 is input.

If this series of operations is repeated m times, m60g2(n+1
) bits are converted from analog to digital.

As described above, according to this embodiment, a high-resolution device can be configured with a small number of comparators by repeatedly operating a plurality of the same comparators.

fLt is a 16-bit parallel type analog/digital converter with a comparator of at least (216-1)-66535.
However, in this device, if m in the above is 4, only n-15 conoparators are required.

Furthermore, with this device, the number of series resistors needed to create a highly accurate reference voltage can also be reduced.

Effects of the Invention According to the present invention, high resolution can be achieved with a small number of comparators by providing a comparator, a switch controlled by the output state of the comparator, a differential amplifier, and a delay circuit that outputs the input signal of the differential amplifier. If you configure the device, you will be lucky.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional analog/digital converter, and FIG. 2 is a block diagram of an analog/digital converter according to an embodiment of the present invention. ...Swin-F-119...Differential amplifier, 2o...
...Delay circuit. Name of agent: Patent attorney Toshio Nakao (1st person)
Condolence diagram 2

Claims (1)

[Claims] A power supply, a series resistor that uses this power supply to create multiple reference voltages, multiple comparators that compare the magnitude of the multiple reference voltages and analog signals, and multiple comparators that take the outputs of the multiple comparators as inputs. an AND circuit, and a plurality of switches controlled by the outputs of the plurality of AND circuits,
an encoder that receives the output of the AND circuit; a shift register that receives the output of the encoder; a switch that selects an analog signal to be input to the plurality of comparators; a delay circuit that delays the analog signal; An analog device comprising: a differential amplifier inputting a reference voltage selected by a plurality of switches and the output of a delay circuit; and a clock source controlling the switch for selecting the analog signal and the shift register. /Digital conversion device.