JPS628618A - Analog-digital converting circuit - Google Patents

Abstract

PURPOSE:To decrease the number of voltage comparator circuits by applying N-bit AD conversion in two lots consisting of high-order N1 bits and low-order N2 bits. CONSTITUTION:Voltages e1, e2, e3 at P sets of voltage dividing points and an analog input voltage are compared by conducting the 1st switch means 6, 7, 8 to latch an output code of a digital signal of a decoder circuit 27 by a latch circuit 28 of two latch circuits. Then the digital signal output code of the decoder circuit is latched by the other latch circuit 29 by conducting one of the 2nd switch means 12, 13, 14, 15 and the 3rd switch means 9, 10, 11 in response to the output code. A digital signal output to an input analog voltage is obtained by using the digital signal output code of the said two latch circuits.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an AD conversion circuit.

[Conventional technology]

Various types of AD conversion circuits have been put into practical use, from low speed ones to high speed ones.
D-conversion circuits can be broadly classified into those using a successive approximation method and those using a parallel comparison method. This successive approximation type AD conversion circuit uses a binary search method to repeatedly compare with a reference voltage and sequentially determines the upper bits.
It is widely used in the fields of measurement, control, and communications because it provides a high-precision reference, but an n-bit AD conversion circuit requires n comparison processing. Also, AD with parallel comparison method
Since the conversion circuit simultaneously compares and processes analog quantities, it is suitable for high-speed applications, but requires as many voltage comparison circuits as there are quantization levels.

[Problem that the invention seeks to solve]

The above-mentioned conventional n-bit AD conversion circuit using the successive approximation method requires n comparison processing, so it has the disadvantage that it is not suitable for high-speed applications. Since this method requires as many voltage comparator circuits as the number of voltage comparators, it has the disadvantage that it is not suitable for converting circuits with a large number of bits.

Currently, AD converters are used for a wide variety of purposes, and therefore, AD converters with various conversion speeds are required depending on the use. For example, you need something faster than a successive approximation method, but
Using a parallel comparison type conversion circuit when you do not need the same high speed as the parallel comparison type
Particularly in the case of integration, this leads to an increase in chip size, which is not economical.

[Means for solving problems]

The AD conversion circuit of the present invention has 2N''-1 comparison means each receiving an analog signal on one input, and a 2N1 threshold value for determining the upper N1 bits on each other of the comparison means. a first supply means for supplying the input to an input; a first storage means for determining and storing the upper N1 bits according to the output of the comparing means; and a first storage means for determining the lower N2 bits according to the upper N1 bits. Said 2N1
a second supply means for supplying one of the one threshold value and the differential amplified voltage of the analog signal to one of the comparison means;
and second storage means for determining and storing the lower N2 bits in accordance with the output of the comparison means.

[Operation/principle of the present invention]

N (N=N1+N2 where N 1 = N 2 or N 1
= N 2+ and N2 is a positive integer), and when realizing an AD conversion circuit with a resolution of 2
” -1) by a voltage dividing circuit, P←2N
A voltage comparator circuit is connected to each of the voltage dividing points Ll>.

Further, the inputs of the two first switch means are connected to the analog input terminal, and the other input terminal of the voltage comparator circuit is connected to the output of the first switch means, respectively. The magnitude of the voltage and the voltage at the voltage dividing point are compared. Furthermore, a boundary detection circuit is provided having P+1 output lines for inputting the output signals of the P voltage comparison circuits and detecting boundary points at which the output signals change.

Further, the inputs of P+1 second switch means are connected to the P voltage dividing points and the ground point, respectively, and the outputs of the second switch means are commonly connected to the input terminal of the differential amplifier.

By applying the input voltage of the analog input terminal to the other input terminal of the differential amplifier, the differential amplifier calculates the difference between the voltage of the common output terminal of the second switching means and the voltage of the analog input terminal. Outputs a voltage amplified by 2N1.

Further, the inputs of 2N''-1 third switch means are commonly connected to the output of the differential amplifier, and the outputs of the third switch means are respectively connected to the outputs of the first switch means of the voltage comparison circuit. and finally, a decoder circuit that receives the output signal of the boundary detection circuit as an input, and two latch circuits that receive the output signal of the decoder circuit as input. Constructing a conversion circuit.In the AD conversion circuit having such a configuration, first, the first switch means is made conductive to compare the voltages at the P voltage division points and the analog input voltage, and convert the digital signal of the decoder circuit. The signal output code is latched by one of the two latch circuits.

Next, one of the second switch means according to the output code.
Then, by making the third switch means conductive, the digital signal output code of the decoder circuit is latched by the other latch circuit. A digital signal output corresponding to the input analog voltage can be obtained by the digital signal output codes of the two latch circuits.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the human conversion circuit of the present invention.
2 is a signal waveform diagram showing the operation in FIG. 1, and FIGS. 3 and 4 are circuit diagrams showing examples of the boundary detection circuit and decoder circuit in FIG. 1, respectively.

In FIG. 1, the AD conversion circuit includes an analog signal input terminal 1, a voltage divider circuit resistor 2. ~5
and, for example, a common output terminal 16 of Sui, Chiro, 15, and Sui, Chiro, 9, which are constructed of field effect transistors,
Common output terminal 17 of Sui, Chia, 10, switch 8,
11 common output terminal 18 and switch 12. -15 common output terminal 19, inverter 20, and differential amplifier 21
and voltage divider circuit resistance 2. The divided voltage at each voltage dividing point where the reference voltage VRIF is divided stepwise by ~5
The voltage comparison circuit 2-2.23.24 which compares the voltages of the common output terminals 16, 17, and 18 respectively and the output signals of the voltage comparison circuits 22.23.24 are input and the output signal is "0". .

A boundary detection circuit 25 that detects the boundary of "1", a child circuit 26 and a decoder circuit 27 that receive the output of the boundary detection circuit 25, and a latch circuit 2N. 29, and a control signal input terminal 30. 32, and an output terminal 33. ~36.

In addition, in Sui, Chiro, and 7.8, when the input signal of the control signal input terminal 30 is at the "1" level, the analog signal "input voltage C0 of the input terminal 10 is outputted to the common output terminals 16, 17.
When the output signal of the inverter 20 is at the "1" level, the switches 9, 10, 11 invert the input signal of the control signal input terminal 30. oM each common output terminal 16.
I will tell you on 17.18. By the way, the differential amplifier 21 uses the output voltage e4 of the common output terminal 19 and the analog signal input terminal 10.
Voltage e'6 = 4, which is amplified by 4 times the difference voltage of input voltage e0
Outputs (e, -e,). Also, switches 12 and 13
, 14, 15 are the outputs D4., 14, and 15 of the latch circuit 26, respectively. D
3. When D2゜Dl is at "1" level, the reference voltage VRI?
*Divided voltage elye! w'l is transmitted to the common output terminal 19, respectively. The output signals of the voltage comparison circuits 22, 23, 24 are the voltages of the common output terminals 16, 17.18, respectively, which are the divided voltages e1 t'! It has a characteristic of outputting the "1" level when it is larger than t eB, and outputting the rOJ level when it is smaller. When the input signal of the black signal input terminal CK changes from the "1" level to the rOJ level, the child circuit 26 latches the output signal of the boundary detection circuit 25, and the output signal is transmitted to the switches 12 and 13 degrees. 14.15 This is a control signal that controls conduction and non-conduction. In addition, the latch circuit 2N. 29 reads the output signal of the decoder circuit 27 and latches it at the rOJ level when the input signal of the clock signal input terminal CK is at the "1" level.

In this embodiment configured as described above, the control signal input terminals 30, 31, and 32 have the terminals shown in FIG. 2 [3], respectively.
Signals with waveforms as shown in (b) and (c) are input. As shown in FIG. 2(a)K, when the input signal of the quantity control signal input terminal 30 from time Tm to TC is at the rlJ level, the switches 6, 7, 8 are in a conductive state, but the output signal of the inverter 20 is Since it becomes "0" level, switch 9
, 10.11 are in a non-conducting state.

Therefore, the input voltage e applied to the analog signal input terminal 1 is transmitted to the common output terminals 16, 17, and 18, and the magnitudes of this input voltage e0 and the divided voltage e110* tel are determined by the voltage comparator circuit 22, 23, 24, eo > 61 s et > eo > et
ea, )e6''>e3. When es>eo, the 3-bit parallel output signals of the voltage comparison circuit 22゜23.24 are (111), (011), (001), (000), respectively.
becomes. Inputs of the boundary detection circuit 25 (A3, A2, A
The relationship between I ) and output (B4.B3.B2.Bl) is the first
As shown in the table, this is realized, for example, by a boundary detection circuit consisting of inverters 37, 38, 39 and NOR gates 40, 41 as shown in FIG.

The decoder circuit 27 in Table 1 is the output of the boundary detection circuit 25 (B4°B
3. B2. Bl) and its input (B4.B3゜B2
The relationship between the outputs (F2, Fl) and the outputs (F2, Fl) is as shown in Table 2, and this is realized, for example, by a decoder circuit consisting of a Noah game (42.43) as shown in FIG.

According to Table 2, the magnitude of voltage C0 applied to analog signal input terminal IK is 6. >et, 63 >eo>at,
The outputs (F2.Fl)K of the decoder circuit 27 are digital outputs (ti), (to)*(ox), and (oo), respectively, according to four types of input conditions: ex>e・>es * es>eo. Obtainable. Further, the latch circuit 2N has its clock signal input terminal CK set to the "1" level at time TRI, as shown in FIG. 2(b), and doubles the output signal of the decoder circuit 27. Therefore, the decoder circuit 27
The output (pz, pi) signals of the latch circuit 2N (
f(4,B3) and its output terminals 33 and 34
You can get digital output.

Next, as shown in FIG. 2(a), at time Tc, the control signal input terminal 300A force signal changes from the "1" level to "0".
When the clock signal input terminal CK changes from the "1" level to the "0" level, the latch circuit 26 changes the clock signal input terminal CK from the "1" level to the "0" level, and transfers the input (c4.c3.c2°CI) signal to its output (B4.B3.B2 .Di) Latch Ic. Therefore, after time Tc, the output of the boundary detection circuit 25 (B4.B3.B
2. The signal of Bl) is directly sent to the output of the latch circuit 26 (B
4. B3. B2. DI), but as can be seen from Table 1, the output is 0.

B3. B2. 1 bit of the 4-bit signal i of Bl).

Since only the output of the latch circuit 26 (B4.B3.B2.DI) is at the "1" level, any one of the outputs (B4.B3.B2.DI) is also 1 bit.

Only bit bit is at rlJ level and the other 3 bits are at rOJ level. As already described, the input voltage e0 of the analog signal input terminal 1 is eg) e,.

eg>eo>eg t et>eo>es * es>
When eo, the output of the boundary detection circuit 25 (B4.B3.B2
．． Bl) are (1000) and (0100) respectively
, (0010), (0001), the switches 12, 13, 14, and 15 are conductive after time Tc when el > atO, switch 12 * e, )
eo) For 6g, switch 13, e,)e,)eg
When , switch 14 e When es>eo, switch 1
It is 5. By the way, the differential amplifier 21 has a common output terminal 19.
It is set to amplify the voltage difference e(1)e4 between the output voltage e4 and the input voltage e0 by four times, and generally when the number of upper conversion bits is Nl, the voltage difference e6-e4. Set to amplify by 2x1. Also, the divided voltage CI.

easem is usually a divided voltage obtained by equally dividing the reference voltage VRgF, and VRIF -1! l ==el -eg
=5. −e,=4. =RIP, and the input voltage e0 is eg>eo>ex At this time, only the switch 13 is conductive, so the common output terminal 19
is the divided voltage e! is given, and the output voltage ej of the differential amplifier 21 becomes ej=4(eo eg) -et )>
It is o. Since the output signal of the inverter 20 is at the "1" level after time TC, switch 9, 10.1
1 is conductive and the output voltage eQ of the differential amplifier 21 and the divided voltage e
The magnitude of 1 tet *em is the voltage comparator circuit 2.
2, 23, and 24. Input voltage C0 is e
When l >eo >ex, the output voltage ej=4 (e,
-! , ) and the divided voltage e1 r eg t el are compared, and 4(eg ex)>extex>4(
eo ex)>easem)4 (eg -eg)
ies, e, )4 (When e(1-<4), that is, the output signals of the pressure comparator circuits 22, 23, and 24 are (1
11), (011), (001), and (000), the output (F2.Fl) of the decoder circuit 27 is (11) and (10), respectively, according to Tables 1 and 2.

(oi), (oo), the magnitude of the input voltage e6,
Digital signal output can be obtained according to four conditions of size. Similarly, when the input voltage e0 is eg)eo>es, the switch 14 becomes conductive, so 4(eO-e
g))el,e,)4(eg-es)>et,e
g)4(eo eg)>esseg>4(eo
The output of the decoder circuit 27 (F2.
A digital signal output can be obtained at Fl). Also e, )e, , e.

The same applies when >eoO. By the way, the output of the decoder circuit 27 (F2.Fl) is the input of the child circuit 29 (G2゜G
l), and the latch circuit 29 outputs "1" to the black and white signal input terminals CK via the control signal input terminal 31.
When a level signal is input, the input (G2, Gl)
The signal of is latched to the output (I(2, Hl).
As shown in C), at time TD, the control signal input terminal 3
When a "1" level signal is input to the clock signal input terminal CK through the circuit 2, the signal causes the output (F2.Fl) of the decoder circuit 27 to rise, and the output (N
2, Hl), and the output (N2, Hl
) appears at output terminal 35°36.

As explained above, in the case of the 4-pin AD conversion circuit of this embodiment, as shown in FIG. Input voltage e0 is e6 >et, el
>eo >ex, el >66>eg, eB>
Decoder circuit 27 decoded according to the four states of 86
The output (F2.Fl) of latch circuit 2 at time TB
Double check N and connect output terminals 33 and 34 as shown in Figure 2(d).
It is possible to obtain the upper two bits of the AD conversion result as shown in FIG. Next, the top two bits after time Tc.

switches 12, 13, 14 based on the conversion result of
By making any one of F2.Pi conductive, the digital signal obtained at the output (F2.Pi) of the decoder circuit 27 is latched by the latch circuit 29 at time TD, and the digital signal is output to its output terminals 35 and 36 as shown in FIG. A as shown in (e)
The lower two bits of the D conversion result can be obtained.

In the case of 4 bits in this embodiment, in the conventional parallel comparison method, 1
Although five voltage comparison circuits are required, it is sufficient to prepare three voltage comparison circuits. Furthermore, although this embodiment shows the case of 4 even bits, in the case of odd bits, for example, in the case of a 2m+1 (m is a positive integer) bit AD converter, the upper m+1 bits and the lower m bits It is obvious that it can be realized separately, and the number of voltage comparison circuits required in this case is 2m+1.

〔Effect of the invention〕

As explained above, the present invention provides N(=N1+N2:N1
．． N2 is a positive integer and N1≧N2) The AD conversion of the bits is performed twice: upper N1 bits and lower N2 bits. Although the conversion speed is a little slower, the number of voltage comparison circuits can be reduced. For example, in a conventional parallel comparison type AD conversion circuit, 2a-1 voltage comparison circuits are required for an n-bit configuration, but according to the present invention, 2m/!
Since only l (if n is an even number) voltage comparator circuits are required, and the number can be greatly reduced, the area of each chia can be greatly reduced when integrated, and its economical effect will be greatly increased. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the AD conversion circuit of the present invention, FIG. 2 is a signal waveform diagram showing the operation in FIG. 1, and FIGS. 3 and 4 are boundary detection in FIG. 1, respectively. FIG. 2 is a circuit diagram showing an example of a circuit and a decoder circuit. 1... Analog signal input terminal, 2. ~5...
...Voltage divider circuit resistance, 6. ~15...Switch, 16. ~19... Common output terminal, 20, 37
．． ~39...Inverter, 21...Differential amplifier, 22. ~24...Voltage comparison circuit, 2
5... Boundary detection circuit, 26, 2N, 29...
... Latch circuit, 27 ... Decoder circuit, 3
0. ~32... Control signal input terminal, 33. ~3
6...Output terminal, 40. ~43...Noah Gate. Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 2^N^1 is an AD conversion circuit that converts an analog signal into a digital signal consisting of upper N1 bits and lower N2 bits, and the analog signal is used as one input, respectively.
- one comparison means, first supply means for supplying 2^N^1-1 thresholds for determining said N1 upper bits to respective other inputs of said comparison means; a first storage means for determining and storing the upper N1 bits according to the output of the means; and the 2^N^1-1 for determining the lower N2 bits according to the upper N1 bits.
a second supply means for supplying a differential amplified voltage between one of the threshold values and the analog signal to one of the comparison means; and a second supply means for determining and storing the lower N2 bits according to the output of the comparison means. An AD conversion circuit comprising: 2 storage means.