JPH09246928A - Multiplexer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve A/D conversion precision turning at least one of analog signal input terminals to a reference signal input terminal, selecting reference signals every time of the selection of respective analog signals, reducing the effect of the analog signal level of a previous channel and selecting the analog signals. SOLUTION: In the selection of the analog signals by address signal input, these respective multiplexers 31-3k select one analog signal, then select the reference signal once and select the analog signal of a new channel thereafter. The multiplexer 4 of a post stage defines the respective output signals of the multiplexers 31-3k as analog signal inputs, selects one of them corresponding to address signals and sends the output to an A/D converter 2. In this case, for the switching timing of the multiplexers, the reference signal is selected after the selection of the analog signal and thereafter, the new analog signal is selected. The level of the selected analog signal input becomes rise or fall from the level of the reference signal at all times and signal changeover from a fixed reference level is performed at all times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexer for time-divisionally capturing multi-input analog signals.

[0002]

2. Description of the Related Art Various digital processing devices such as a digital protective relay convert an analog signal into a digital signal and convert it into digital data for various processing. Therefore, when a large number of analog signals are taken in, the analog signal is converted into a digital signal. A multiplexer is provided in the preceding stage so that only one A / D converter is required.

FIG. 3 shows a conventional circuit diagram. Each of the plurality of multiplexer circuits 1 ₁ to 1 _N has, in addition to a plurality of analog signal input terminals, an address signal input terminal for selecting each analog signal and an enable signal input terminal for selecting the multiplexer itself. There is.

The output terminals of the multiplexer circuits 1 ₁ to 1 _N are connected in parallel to each other to be time-divided analog input signals to the A / D converter 2, and the A / D converter 2 converts them into digital signals. The conversion is done.

In this configuration, first, one of the multiplexers 1 ₁ to 1 _N to be used is selected by the enable signal, and one of the analog input signals to be used is selected as the channel by the address signal of the selected multiplexer. This selected analog input signal is A / D
It is converted into a digital signal by the converter 2.

[0006]

SUMMARY OF THE INVENTION In a conventional circuit,
An analog signal switched in time division is applied to the A / D converter 2, and the analog signal is sequentially converted into a digital signal.

The analog signal waveform to the A / D converter 2 at this time is, for example, as shown in FIG. 4, and the analog input signal is sequentially switched at the switching timing of the multiplexer. In the figure, the maximum value + 10V and the minimum value -10V are alternately switched.

The switching of the analog input signal is performed with a certain rise time or fall time, and the time is different depending on the analog input signal level before switching and the analog input signal level after switching.

Therefore, if the switching timing interval of the multiplexer is shortened in order to increase the selection speed of the multiplexer, the level of the switched analog input signal is the same as that of the previous channel due to the existence of the switching time for switching the analog input signal. It is affected by the level of the analog input signal and is used for A / D conversion without the level being established, thus deteriorating the conversion accuracy.

In other words, in order to ensure a certain conversion accuracy, the number of analog input channels within a certain time is limited, and the conversion speed is reduced.

It is an object of the present invention to provide a multiplexer capable of selectively outputting an analog signal with less influence from the analog signal level of the previous channel.

[0012]

According to the present invention, in a multiplexer for extracting a large number of analog signal inputs in a time division manner and extracting them as inputs of an A / D converter, at least one of the analog signal input terminals is a reference signal input terminal. The reference signal is selected every time each of the analog signals is selected.

[0013]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. The multiplexers 3 _{1 to} 3 _{K in the} preceding stage have an enable signal input terminal, an address signal input terminal, and a plurality of analog signal input terminals like the conventional multiplexer, but the different part is one of the plurality of analog signal input terminals. One is used as a reference signal (0V) input terminal.

Each of the multiplexers 3 _{1 to} 3 _K is set to 1 when selecting an analog signal by inputting an address signal.
After selecting one analog signal, the reference signal is selected once, and then the analog signal of a new channel is selected as a selection circuit configuration or an address signal.

The multiplexer 4 in the subsequent stage receives the output signals of the multiplexers 3 _{1 to} 3 _K as analog signal inputs, selects one of them as an address signal, and outputs the selected output to the A / D converter 2. Use as input signal.

The operation of selecting the analog signal according to the present embodiment is as shown in FIG. 2, and the switching timing of the multiplexer is the selection of the analog signal, the selection of the reference signal, and the subsequent selection of a new analog signal. .

Therefore, when the analog signal input of a certain channel is selected, the reference signal is selected before that, and the level of the selected analog signal input always rises or falls from the level of the reference signal. Therefore, the signal is always switched from the constant reference level.

As a result, the level of the selected analog signal is less influenced by the previous analog signal level, and as a result, the A / D conversion accuracy is increased at the same conversion speed as the conventional one, or the same conversion accuracy is obtained. Then, the switching timing cycle can be shortened to increase the conversion speed.

The multiplexer 4 in the subsequent stage is connected in cascade with the multiplexers 3 _{1 to} 3 _K to increase the switching speed for a large number of analog signal inputs. Along with this,
In the embodiment, the case where the reference signal input terminals are individually provided to the multiplexers 3 _{1 to} 3 _K in the preceding stage is shown, but the reference signal input terminals are provided only to the multiplexer 4, and the reference signal is provided between the channels on the multiplexer 4 side. It can also be configured to be inserted.

It is also possible to alternately provide the reference signal input terminal with each analog signal input terminal and select the analog signal and the reference signal alternately by operating the multiplexer in ascending or descending order.

[0021]

As described above, according to the present invention, at least one of the analog signal input terminals is used as the reference signal input terminal, and the reference signal is selected every time each analog signal is selected. The analog signal can be selectively output by reducing the influence from the analog signal level of
There is an effect that the A / D conversion accuracy and the conversion speed can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an output waveform of the embodiment.

FIG. 3 is a conventional circuit diagram.

FIG. 4 is a conventional output waveform.

[Explanation of symbols]

1 ... Multiplexer 2 ... A / D converter 3 ₁ , 3 _K ... Pre-stage multiplexer 4 ... Post-stage multiplexer

Claims (1)

[Claims] 1. A multiplexer in which a large number of analog signal inputs are selected in a time division manner and taken out as inputs of an A / D converter, and at least one of the analog signal input terminals is used as a reference signal input terminal, and each analog signal is selected. A multiplexer characterized in that the reference signal is selected each time.