JP2000022540A - Ad conversion circuit - Google Patents

Ad conversion circuit

Info

Publication number
JP2000022540A
JP2000022540A JP10190608A JP19060898A JP2000022540A JP 2000022540 A JP2000022540 A JP 2000022540A JP 10190608 A JP10190608 A JP 10190608A JP 19060898 A JP19060898 A JP 19060898A JP 2000022540 A JP2000022540 A JP 2000022540A
Authority
JP
Japan
Prior art keywords
conversion
analog signal
digital
multiplexer
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10190608A
Other languages
Japanese (ja)
Other versions
JP3152208B2 (en
Inventor
Takeya Nakamura
剛也 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19060898A priority Critical patent/JP3152208B2/en
Publication of JP2000022540A publication Critical patent/JP2000022540A/en
Application granted granted Critical
Publication of JP3152208B2 publication Critical patent/JP3152208B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To secure the digital conversion value which is fast and sequentially converted at a short time interval and regardless of its waiting time by directly inputting the analog signal selected by a multiplexer to an AD conversion part to convert it into a digital signal. SOLUTION: An analog signal selection switch S1 of the 1st channel of a multiplexer 1 is closed and also an analog signal selection switch S2 of the 2nd channel and an analog input selection switch S3 of the 3rd channel of the multiplexer 1 are opened respectively by the control signal of a control arithmetic part 3. At the same time, an AD conversion part 2 samples an analog signal ViC and immediately converts it into a digital signal to secure the digital conversion value. Then the part 2 also samples the signal ViC and converts it into a digital signal to secure the digital conversion value after a time (t). Thus, the analog signal value is calculated as the digital value based on the digital conversion. value obtained at two points set before and after a selected analog signal Vi1, the sampling interval time and a time constant that is inherent in the analog input part of the part 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、アナログ信号入力
をマルチプレクサで順次切り換え選択して、AD変換部
でデジタル変換するAD変換回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AD conversion circuit for sequentially switching and selecting an analog signal input by a multiplexer and performing digital conversion by an AD converter.

【0002】[0002]

【従来の技術】従来のこの種のAD変換回路は、マルチ
プレクサが複数の信号スイッチング素子を有するため、
スイッチの端子容量の総和が大きくなることに加えて、
これらスイッチング素子を接続する配線が長くなるた
め、浮遊容量が大きくなり、その結果、マルチプレクサ
の入力端からAD変換部へ至るまでの入力系の容量が大
きくなっていた。
2. Description of the Related Art In a conventional AD converter of this type, a multiplexer has a plurality of signal switching elements.
In addition to increasing the total terminal capacitance of the switch,
Since the wiring for connecting these switching elements becomes longer, the stray capacitance increases, and as a result, the capacitance of the input system from the input terminal of the multiplexer to the AD converter increases.

【0003】[0003]

【発明が解決しようとする課題】このため、アナログ信
号がマルチプレクサの入力端に入力された時点から、そ
のアナログ信号によって上記入力系の容量が充分にチャ
ージされる時間まで、つまりAD変換部での変換精度に
影響を与えない程度にチャージされるまで待ってから、
AD変換部での変換を実行しなければならなく、この待
ち時間のために順次変換の速度が遅くなる問題点があっ
た。例えば、入力電圧の0.1%の精度が必要な場合に
は、入力系に固有の時定数をΤとすると、約6Τ時間の
待ち時間が必要であった。
For this reason, from the time when an analog signal is input to the input terminal of the multiplexer until the time when the capacitance of the input system is sufficiently charged by the analog signal, that is, in the AD conversion unit. Wait until it is charged to the extent that conversion accuracy is not affected,
The conversion in the AD converter must be performed, and this waiting time causes a problem that the speed of the sequential conversion is reduced. For example, when an accuracy of 0.1% of the input voltage is required, a waiting time of about 6 hours is required, assuming that the time constant inherent to the input system is Τ.

【0004】本発明は、AD変換部の前段でのこのよう
な待ち時間に依存せずに、それよりも短い時間間隔で高
速に順次変換したデジタル変換値が得られるAD変換回
路を提供することにある。
An object of the present invention is to provide an AD conversion circuit capable of obtaining a digitally converted value which is sequentially converted at high speed at shorter time intervals without depending on such a waiting time at the preceding stage of the AD converter. It is in.

【0005】[0005]

【課題を解決するための手段】アナログ信号がマルチプ
レクサに入力される前の段階では、AD変換部のアナロ
グ入力部分の電圧は不定であるが、アナログ信号がマル
チプレクサに入力されると、AD変換部のアナログ入力
部分の電圧は、固有の時定数τにより決定される時間の
関数として、マルチプレクサの入力端のアナログ信号電
圧に漸近していく。時定数τが既知であれば、AD変換
部のアナログ入力部分の電圧が、マルチプレクサの入力
端のアナログ信号電圧と同じになるまで待たなくとも、
直ちにAD変換したデジタル変換値から、アナログ信号
電圧の値の算出は可能である。
Before the analog signal is input to the multiplexer, the voltage of the analog input portion of the AD converter is indefinite, but when the analog signal is input to the multiplexer, the voltage of the AD converter is changed. The voltage at the analog input of the multiplexer approaches the analog signal voltage at the input of the multiplexer as a function of time determined by an inherent time constant τ. If the time constant τ is known, it is not necessary to wait until the voltage of the analog input portion of the AD converter becomes the same as the analog signal voltage of the input terminal of the multiplexer.
The value of the analog signal voltage can be immediately calculated from the digitally converted value obtained by the AD conversion.

【0006】本発明は、このことに着目したもので、マ
ルチプレクサで選択されたアナログ信号がAD変換部へ
直接入力されて同時にデジタル変換される構成とし、A
D変換部で変換された前回のデジタル変換値と今回のデ
ジタル変換値とAD変換部でのサンプリング時間間隔t
と、AD変換部のアナログ入力部分の時定数τとから、
入力されたアナログ信号の値を制御演算部でデジタル値
として算出する。
The present invention focuses on this point, and has a configuration in which an analog signal selected by a multiplexer is directly input to an AD converter and is simultaneously converted into a digital signal.
The previous digital conversion value converted by the D conversion unit, the current digital conversion value, and the sampling time interval t in the AD conversion unit
And the time constant τ of the analog input part of the AD converter,
The value of the input analog signal is calculated as a digital value by the control operation unit.

【0007】すなわち、本発明では、AD変換部の前段
で待ち時間をおかずにAD変換部で直ちにAD変換し、
時間的に前後2点の変換値V1・V2の差分と、その時
間間隔t(サンプリング時間間隔)と、AD変換部のア
ナログ入力部分の時定数τとから、入力されたアナログ
信号の値を近似的なデジタル値として算出する。従っ
て、AD変換部でのサンプリング時間間隔tを、従来に
おける待ち時間よりも短くすることで、従来よりも高速
化が図れる。
That is, in the present invention, the A / D converter immediately performs the A / D conversion without a waiting time in the preceding stage of the A / D converter.
Approximate the value of the input analog signal from the difference between the converted values V1 and V2 at two points before and after, the time interval t (sampling time interval), and the time constant τ of the analog input portion of the AD converter. It is calculated as a typical digital value. Accordingly, by making the sampling time interval t in the AD conversion unit shorter than the conventional waiting time, it is possible to achieve a higher speed than in the past.

【0008】制御演算部は、CPUと、AD変換部で変
換されたデジタル変換値を記憶するメモリと、マルチプ
レクサの切換タイミング及びAD変換部の変換タイミン
グの時間制御を行うためのタイマとで構成できる。
The control operation section can be constituted by a CPU, a memory for storing the digital conversion value converted by the AD conversion section, and a timer for performing time control of the switching timing of the multiplexer and the conversion timing of the AD conversion section. .

【0009】[0009]

【発明の実施の形態】次に、本発明の実施の形態を図面
を参照して説明する。
Next, embodiments of the present invention will be described with reference to the drawings.

【0010】図1において、本発明によるAD変換回路
は、複数の入力チャネルの1つを順次切り換え選択する
マルチプレクサ1と、これにて選択入力されるアナログ
信号をデジタル変換するAD変換部2と、その変換され
たデジタル変換値を演算するとともに、これらマルチプ
レクサ1及びAD変換部2を制御する制御演算部3とで
構成される。
In FIG. 1, an A / D conversion circuit according to the present invention includes a multiplexer 1 for sequentially switching and selecting one of a plurality of input channels, an A / D converter 2 for digitally converting an analog signal selected and input by the multiplexer, It is composed of a control operation unit 3 that calculates the converted digital conversion value and controls the multiplexer 1 and the AD conversion unit 2.

【0011】マルチプレクサ1は、複数個(図では3
個)のアナログ信号選択スイッチS1〜S3を有し、こ
れらスイッチS1〜S3の開閉タイミングを制御演算部
3により制御される。スイッチS1〜S3を順次オンす
ることにより選択入力されたアナログ信号は、従来のよ
うに入力系の容量が充分にチャージされる時間まで待つ
ことなく、AD変換部2にて一定のサンプリング時間間
隔tでデジタル変換される。その変換タイミングは制御
演算部3にて制御される。
A plurality of multiplexers 1 (3 in the figure)
) Analog signal selection switches S1 to S3, and the opening and closing timing of these switches S1 to S3 is controlled by the control calculation unit 3. The analog signal selected and input by sequentially turning on the switches S1 to S3 is supplied to the AD converter 2 at a constant sampling time interval t without waiting for a time until the input system capacitance is sufficiently charged as in the prior art. Is converted to digital. The conversion timing is controlled by the control calculation unit 3.

【0012】図3に、制御演算部3の内部構成まで示し
た実施例を示す。制御演算部3は、CPU4と、AD変
換部2で変換されたデジタル変換値を記憶するメモリ5
と、マルチプレクサ1のスイッチS1〜S3の開閉タイ
ミング及びAD変換部2の変換タイミングの時間制御を
行うためのタイマ6とからなる。
FIG. 3 shows an embodiment showing the internal configuration of the control operation unit 3. The control operation unit 3 includes a CPU 4 and a memory 5 that stores the digital conversion value converted by the AD conversion unit 2.
And a timer 6 for performing time control of the opening / closing timing of the switches S1 to S3 of the multiplexer 1 and the conversion timing of the AD converter 2.

【0013】次に、動作について説明する。アナログ信
号Vi1の変換を行う場合、制御演算部3の制御信号に
より、マルチプレクサ1の第1チャネルのアナログ信号
選択スイッチS1を閉じ、第2チャネルのアナログ信号
選択スイッチS2及び第3チャネルのアナログ入力選択
スイッチS3を開く。同時にAD変換部2でアナログ信
号ViCをサンプリングして直ちにAD変換を行い、デ
ジタル変換値Vt1を得る。
Next, the operation will be described. When the conversion of the analog signal Vi1 is performed, the analog signal selection switch S1 of the first channel of the multiplexer 1 is closed by the control signal of the control operation unit 3, and the analog signal selection switch S2 of the second channel and the analog input selection of the third channel are selected. Open the switch S3. At the same time, the analog signal ViC is sampled by the AD converter 2 and AD conversion is immediately performed to obtain a digital conversion value Vt1.

【0014】次にt時間後、制御演算部3の制御信号に
より、AD変換部2でアナログ信号ViCをサンプリン
グしてAD変換を行い、デジタル変換値Vt2を得る。
ここで、選択されたアナログ信号Vi1の前後2点のデ
ジタル変換値をVt1、Vt2、サンプリング間隔時間
をt、AD変換部2のアナログ入力部分に固有の時定数
をτとすると、アナログ信号ViCは近似的に以下の式
で表される。
Next, after a time t, the analog signal ViC is sampled by the A / D converter 2 and subjected to A / D conversion by the control signal of the control calculator 3, thereby obtaining a digital conversion value Vt2.
Here, assuming that the digital conversion values at two points before and after the selected analog signal Vi1 are Vt1 and Vt2, the sampling interval time is t, and the time constant unique to the analog input portion of the AD converter 2 is τ, the analog signal ViC is It is approximately expressed by the following equation.

【0015】Vi1 = {Vt2−Vt1・e^(−
t/τ)}/{1−e^(−t/τ)}
Vi1 = {Vt2-Vt1.e} (-
t / τ)} / {1-e} (-t / τ)}

【0016】制御演算部3において、上式によりVi1
を算出し、デジタル値を得る。以下、次のアナログ信号
選択スイッチを選択し、同様な手順でAD変換を順次実
行する。このときサンプリング間隔時間tを、従来のA
D変換回路で必要とされる待ち時間より短くすることに
より、高速にAD変換を実行できる。
In the control calculation unit 3, Vi1
Is calculated to obtain a digital value. Hereinafter, the next analog signal selection switch is selected, and AD conversion is sequentially performed in the same procedure. At this time, the sampling interval time t is
AD conversion can be performed at high speed by making the waiting time shorter than that required by the D conversion circuit.

【0017】図2は、本発明の動作を説明したタイミン
グチャートである。ここでt1は1回目のアナログ信号
サンプリングの時刻、t2は2回目のアナログ信号サン
プリングの時刻、tはサンプリング時間間隔、Vt1は
1回目のアナログ信号サンプリングの時刻にAD変換部
2に入力されている電圧、Vt2は2回目のアナログ信
号サンプリングの時刻にAD変換部2に入力されている
電圧である。
FIG. 2 is a timing chart for explaining the operation of the present invention. Here, t1 is the time of the first analog signal sampling, t2 is the time of the second analog signal sampling, t is the sampling time interval, and Vt1 is input to the AD converter 2 at the time of the first analog signal sampling. The voltage Vt2 is the voltage input to the AD conversion unit 2 at the time of the second analog signal sampling.

【0018】[0018]

【発明の効果】本発明によれば、AD変換部の前段で待
ち時間をおかずにAD変換部で直ちにAD変換し、時間
的に前後2点の変換値V1・V2の差分と、その時間間
隔t(サンプリング時間間隔)と、AD変換部のアナロ
グ入力部分の時定数τとから、入力されたアナログ信号
の値を近似的なデジタル値として算出するので、従来よ
りも短い時間間隔で高速に順次変換したデジタル変換値
が得られる。
According to the present invention, A / D conversion is immediately performed by the A / D conversion unit without a waiting time at the preceding stage of the A / D conversion unit, and the difference between the converted values V1 and V2 at two points before and after the time is calculated. Since the value of the input analog signal is calculated as an approximate digital value from t (sampling time interval) and the time constant τ of the analog input portion of the AD conversion unit, the value is sequentially and quickly increased at a shorter time interval than in the related art. A converted digital value is obtained.

【0019】また、従来のAD変換回路では複数のAD
変換部で対応していた構成を、本発明では1個のAD変
換部だけで済むため、回路構成が簡素になり、コストが
低減できる。
In a conventional AD conversion circuit, a plurality of ADs
The present invention requires only one A / D converter, instead of the configuration supported by the converter, so that the circuit configuration is simplified and the cost can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明によるAD変換回路の一例のブロック図
である。
FIG. 1 is a block diagram of an example of an AD conversion circuit according to the present invention.

【図2】本発明の動作を説明したタイミングチャートで
ある。
FIG. 2 is a timing chart illustrating the operation of the present invention.

【図3】制御演算部の内部構成まで示した実施例のブロ
ック図である。
FIG. 3 is a block diagram of an embodiment showing up to an internal configuration of a control operation unit.

【符号の説明】[Explanation of symbols]

1 マルチプレクサ 2 AD変換部 3 制御演算部 S1〜S3 アナログ信号選択スイッチ DESCRIPTION OF SYMBOLS 1 Multiplexer 2 AD conversion part 3 Control operation part S1-S3 Analog signal selection switch

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】アナログ信号入力を順次切り換え選択する
マルチプレクサと、このマルチプレクサで選択されたア
ナログ信号をデジタル変換するAD変換部とを有するA
D変換回路において、前記マルチプレクサで選択された
アナログ信号が前記AD変換部へ直接入力されて同時に
デジタル変換される構成としたこと、AD変換部で変換
された前回のデジタル変換値と今回のデジタル変換値と
AD変換部でのサンプリング時間間隔tとAD変換部の
アナログ入力部分の時定数τとから、入力されたアナロ
グ信号の値をデジタル値として算出する制御演算部を備
えたことを特徴とするAD変換回路。
A multiplexer comprising: a multiplexer for sequentially switching and selecting an analog signal input; and an AD converter for digitally converting the analog signal selected by the multiplexer.
In the D conversion circuit, the analog signal selected by the multiplexer is directly input to the A / D conversion unit and is simultaneously converted into a digital signal, and the previous digital conversion value converted by the A / D conversion unit and the current digital conversion A control operation unit for calculating the value of the input analog signal as a digital value from the value, the sampling time interval t in the AD conversion unit, and the time constant τ of the analog input part of the AD conversion unit. AD conversion circuit.
【請求項2】制御演算部は、CPUと、AD変換部で変
換されたデジタル変換値を記憶するメモリと、マルチプ
レクサの切換タイミング及びAD変換部の変換タイミン
グの時間制御を行うためのタイマとを有している請求項
1記載のAD変換回路。
The control operation unit includes a CPU, a memory for storing the digital conversion value converted by the AD conversion unit, and a timer for performing time control of the switching timing of the multiplexer and the conversion timing of the AD conversion unit. 2. The AD conversion circuit according to claim 1, comprising:
JP19060898A 1998-07-06 1998-07-06 AD conversion circuit Expired - Fee Related JP3152208B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19060898A JP3152208B2 (en) 1998-07-06 1998-07-06 AD conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19060898A JP3152208B2 (en) 1998-07-06 1998-07-06 AD conversion circuit

Publications (2)

Publication Number Publication Date
JP2000022540A true JP2000022540A (en) 2000-01-21
JP3152208B2 JP3152208B2 (en) 2001-04-03

Family

ID=16260910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19060898A Expired - Fee Related JP3152208B2 (en) 1998-07-06 1998-07-06 AD conversion circuit

Country Status (1)

Country Link
JP (1) JP3152208B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008182508A (en) * 2007-01-25 2008-08-07 Hitachi Ltd A/d conversion apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008182508A (en) * 2007-01-25 2008-08-07 Hitachi Ltd A/d conversion apparatus

Also Published As

Publication number Publication date
JP3152208B2 (en) 2001-04-03

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