JP3467392B2 - Programmable controller - Google Patents

Description

BACKGROUND OF THE INVENTION [0001] [Technical Field of the Invention The present invention is, programmable co
The present invention relates to a controller (hereinafter, referred to as a PC), and particularly to a technique for removing noise that enters an analog input module of the PC.
About . 2. Description of the Related Art A conventional PC analog input circuit will be described with reference to FIGS. FIG. 5 is a schematic diagram of a conventional PC analog input circuit, and FIG. 6 is a schematic diagram of a noise waveform input in the conventional PC analog input circuit. As shown in FIG. 5, the analog input circuit PC, the selection of n input terminals 2 where n analog signal 1 is inputted, switching the n analog signals 1, one analog signal 1 1 and an A / D converter 4 for converting the analog signal 1 into a digital signal. [0003] to the analog input circuit of a conventional PC shown in FIG. 5, the analog input signal waveform noise waveform 30 as shown in the left diagram Ru have <br/> riding of FIG. 6 illustrating a case where the input. In the above circuit, it is assumed that sampling is performed at the timing when the noise waveform 30 is running as shown in the right diagram of FIG. Analog input circuits of the PC, because it does not include the noise removing circuit, the analog input signal digital
The converted data fluctuates by the noise voltage 31. As a result, the converted data may become abnormal. [0004] Various improvements have been proposed for abnormalities in the conversion data of the analog input circuit of the conventional PC. For example, there are provided sampling / hold means for sampling and holding an analog signal input from an analog input terminal at a predetermined timing by a plurality of capacitors and a plurality of switches, and A / D conversion means for converting an analog signal into a digital signal. In an analog signal sample obtained by executing a plurality of successive sample / hold operations, an analog signal corresponding to an average value is generated by operating a capacitor and a switch of the sampling / hold means, and this analog signal is converted into a digital signal. There is a method for removing noise. As a technique related to this, there is a technique described in JP-A-3-128531. In the above method, the capacitor and the switch must be prepared for a plurality of samples,
There is a problem that the circuit becomes large and the control device becomes complicated. Further, for example, an analog signal is converted into a digital signal, the sampled digital signal is sampled a plurality of times, the sampled digital signal is averaged and stored, and the current analog signal is converted into a digital signal. And the stored averaged digital signal to eliminate noise. Related to this is a technique described in Japanese Patent Application Laid-Open No. Hei 7-110652. The method, for performing all the processing after the digital signal conversion, a microprocessor and ROM and RAM are required, the cost of the circuit is increased. SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and provides a PC which can easily reduce the influence of noise disturbance invading an analog input circuit of the PC with a simple circuit configuration. That is the purpose. [0007] A programmer according to the present invention.
Bull controller configuration is one of a plurality of analog signals
A selector for selecting two analog signals; and
A first capacitor that holds and charges one analog signal, an A / D converter that converts the analog signal to a digital signal, and a digital signal that is converted to the digital signal
A RAM for storing signal data , means for reading converted digital data of another analog signal stored in the RAM, a D / A converter for converting the read digital value to another analog signal, and a D / A converter A second capacitor for holding and charging another converted analog signal , and a first switch for connecting the selector and the RAM
Comprising circuit and a second switching circuit, and a timing generating circuit for controlling these, one fixed in the first switching circuit
Connect the contact terminals to the selector and connect the other fixed contact terminals to the front.
Connected to the movable contact terminal of the second switching circuit,
The first capacitor is connected to the movable contact terminal of the first switching circuit.
Connect the capacitors, other fixed contact terminal of the first switching circuit
At the connection point between the movable contact terminal of the second switching circuit and
A second switching circuit for connecting a second capacitor;
Of the A / D converter and D
/ A converter and connected to the RAM,
Animing generating circuit, wherein the first switching circuit and the second
Switching circuit and hold the current analog signal.
To charge the first capacitor and calculate the previous average value to the R
Read from AM, D / A convert and charge second capacitor
And calculate an average value from both capacitor values.
/ D-converted up to and storing in the RAM
It is a programmable controller . An embodiment according to the present invention will be described below with reference to FIGS. In order to solve the above problems, the configuration of the embodiment of the PC according to the present invention
In the analog input circuit C, and the analog input signal at the present time to together Charging the capacitor, already digital value data converted A / D, and charges the capacitor analog input signal is converted again D / A, these two capacitors By providing a means for averaging the values, the influence of noise disturbance entering the analog input circuit is removed. Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic diagram of an embodiment according to a PC of the present invention. As shown in the figure, a plurality of analog input terminals 5a.
6n are connected. Next, these analog signals 5a.
Is connected to an analog channel switch 7 (multiplexer), so that an arbitrary analog signal is selected. The analog channel switching device 7 is connected to a timing generation circuit 8, and the timing generation circuit 8 generates an analog channel switching control signal 10 to be transmitted to the analog channel switching device 7. The analog channel switch 7 includes:
A changeover switch 13 having fixed contact terminals a, b (hereinafter, referred to as terminals a, b, respectively) and a movable contact terminal c (hereinafter, referred to as terminal c), and fixed contact terminals A, B (hereinafter, referred to as terminals A, B, respectively). ) And a changeover switch 18 having a movable contact terminal C (hereinafter, referred to as a terminal C) are connected in series. The terminal a is connected to the analog channel.
The terminal b is connected to the terminal C, respectively. A capacitor 12 is connected between the movable contact terminal c and the ground, and a capacitor 14 is connected between the connection between the terminal b and the terminal C and the ground. Further, terminal A
A / D converter 17, the the terminal B D / A converter
The converters 17 and 15 are connected to the RAM 15
16 are connected. Further, the timing generation circuit 8 and the RAM 16 are connected. The address bus 9 is connected to the timing generation circuit 8 and the data bus 19 is connected to the RAM 16. [0015] Next, the P of the embodiment of the present invention having the above configuration is described.
The operation of C will be described with reference to FIGS. FIG.
1 is a schematic diagram of one sampling waveform of the analog input in the PC of FIG. 1, FIG. 3 is a schematic diagram of another sampling waveform of the analog input in the PC of FIG. 1, and FIG.
It is a flowchart figure which shows the function of C. At the present time, in step 1, FIG.
Analog Chang analog input signal having a waveform as shown in the
It is input to the flannel switch 7. In Step 2, now, when it is sampled at (a) point on the waveform, Ana
The analog signal VA is selected by the log channel switch 7. In step 3, the changeover switch 13 is set to the terminal a
Side, and holds, and charges the capacitor 12 with the analog signal VA. [0017] the previous one as an example, a description will be given of removal of the previous value. The sampling position on the waveform at this point is sampling at the position (b) in FIG. 3 (point affected by noise). Step 11, 1
In steps 2 and 13, operations similar to those in steps 1 to 3 are performed, and the capacitor 12 is charged. That is, the analog signal VB is selected by the analog channel selector 7 at the sampling position (b) shown in FIG. 3, the changeover switch 13 is switched to the terminal a side and held, and the capacitor 12 shown in FIG. analog signal VB which noise waveform is superimposed at the position (b) of is charged. In step 14, the changeover switch 18
Is switched to the terminal A side and held.
Is switched to the terminal b side and held, and the signal value of the capacitor 12 is converted into a digital signal by the A / D converter 17. Next, in step 15, the digital signal converted to the address X of the RAM 16 is stored. Next, in step 16, the RAM 16
Digital signal D / A con converted from the corresponding address of
It is converted into an analog signal by the barter 15. Step 1
7, when the changeover switch 18 is switched to the terminal B side and held, the converted analog signal, the voltage VB
To charge the capacitor 14. In step 18, the changeover switch 18
When the switch is switched to the terminal A side and the changeover switch 13 is switched to the terminal b side, since the capacitor 12 and the capacitor 14 are connected in parallel, the voltage VA at the sampling position (a) in FIG. B) the voltage VB at
The two voltages will be averaged. The ratio of the influence of the current value and the previous value in this averaging can be freely determined by selecting the capacitance of the capacitors 12 and 14. In step 19, the averaged analog signal is converted into a digital value by the A / D converter 17. In step 20, the digital value is R
It is stored at the address X of AM16. In this way, X, X +
At the addresses 1, X + 2..., The analog signal values averaged to reduce the influence of noise are sequentially stored as digital signal values in a time-series sequence. When a new analog signal is sampled, the RAM 16
Is averaged with the average value stored at the address X, thereby reducing the influence of noise. That is, the n-th sampled analog signal is averaged with the (n-1) -th average value. Thereafter, the same operation is repeated, and this operation is sequentially performed for each input, and the data is stored in the corresponding addresses. This is sent to RAM1 from another device.
By reading the address of No. 6, it is possible to read out from the data bus 19. According to the present invention , the influence of noise disturbance invading the analog input circuit of the PC can be reduced with a simple circuit configuration.
In addition , a PC that can be easily reduced can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of an embodiment of a PC according to the present invention. FIG. 2 is a schematic diagram of one sampling waveform of an analog input in the PC of FIG. 1; FIG. 3 is a schematic diagram of another sampling waveform of analog input in the PC of FIG. 1; FIG. 4 is a flowchart illustrating functions of the PC in FIG. 1; FIG. 5 is a schematic diagram of a conventional PC analog input circuit. FIG. 6 is a schematic diagram of a sampling waveform of an analog input circuit of a conventional PC. [Description of Signs] 1 ... Analog signal source 2 ... Analog input terminal group 3 ... Analog channel switching device 4 ... A / D converter 5 ... Analog input terminal 6 ... Analog input signal source 7 ... Analog channel switching device 8 ... Timing generator 9 Address bus 10 Analog channel switching control signal 11 Analog signal 12 Capacitor 13 Switching switch 14 Capacitor 15 D / A converter 16 RAM 17 A / D converter 18 Switching switch 19 Data bus 30 Noise waveform 31: Noise voltage

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-9-159496 (JP, A) JP-A-3-128531 (JP, A) JP-A-9-261463 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G05B 19/05

Claims (1)

(57) Claims: 1. A selector for selecting one analog signal from a plurality of analog signals, and a first capacitor for holding and charging the selected one analog signal. And an A / D converter for converting the analog signal into a digital signal.
And Ta, D converting a RAM for storing the signal data converted into the digital signal, means for reading the converted digital data of the other analog signals stored in the RAM, the read digital values to another analog signal / A
A second capacitor and converters, other analog signal converted the D / A is being held charged, the election
A first switching circuit for connecting the selector and the RAM, and a second switching circuit.
And circuit, comprising a timing generation circuit for controlling these, wherein the selector of one of the fixed contact terminal of the first switching circuit
And the other fixed contact terminal is connected to the second switching circuit.
Connected to the moving contact terminal, and connected to the first switching circuit.
Connecting the first capacitor to a movable contact terminal;
Another fixed contact terminal of the first switching circuit and the second switching circuit
The second capacitor is connected to the connection point with the movable contact terminal of
The fixed contact terminal of the second switching circuit.
Via the A / D converter and D / A converter, respectively
And connected to the RAM, and in the timing generation circuit,
The first switching circuit and the second switching circuit are switched, and
Hold the analog signal at the time point and
And the previous average value is read from the RAM, and D /
A is converted and the second capacitor is charged.
The average value is calculated, and the average value is subjected to A / D conversion to obtain the RA.
A programmable controller characterized by storing in M
Laura .