JPH05259916A - Current addition type d/a converter - Google Patents

Abstract

PURPOSE:To prevent the glitch caused to the output voltage when the input data to be converted are varied continuously by providing a current addition type D/A converter provided with plural basic cells consisting of constant current sources and arranged in a matrix and also contains a decoder to select the cells to be outputted to the input digital signal. CONSTITUTION:This current addition type D/A converter is provided with the basic cells 1-31 arranged in a matrix and consisting of the constant current sources, the switches, and the logic circuits which perform the ON/OFF control of these switches and also contains a decoder 52 which produces the control signals xi, yj and zi to select the cells to be outputted to the input digital. The decoder 52 selects the cells in such a combination that produces no glitch as long as the input data are varied continuously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current-summing type D / A converter using a plurality of constant current sources, and a glitch generated in a conversion output during a transient response when an input digital signal to be changed changes. This is to reduce and remove.

[0002]

2. Description of the Related Art In recent years, with the progress of digital signal processing technology, the demand for high speed and high accuracy of D / A converters is increasing.

A circuit of a conventional current addition type D / A converter will be described below with reference to the drawings. FIG. 3 is a block diagram of a conventional current addition type 5-bit D / A converter. Figure 3
1 to 31 are 31 cells arranged in a matrix, 52 is a decoder, 61 and 62 are latch circuits, 6
3 is a clock input terminal (CLK), 51 is a digital input terminal, 72 is a bias circuit for setting the current value of the constant current source of each cell, 71 is a reference power input terminal for bias setting, 41 is the current of the D / A converter. It is an output terminal. Normally, a resistor 42 is connected to the output terminal 41, and the other end of 42 is grounded. The cells 21 and 28 are shown in FIG. Each cell is composed of a constant current source, a switch SW, and some logic circuits, and three control lines xi, yj, zi input to each cell are provided.
The switch SW is controlled as shown in (Table 1).

[0004]

[Table 1]

For example, in the 21st cell, the switch SW is turned ON only when both x3 and y5 are 1 or z3 is 1.
21 is connected. In the following, the switch SW21 in each cell is "selected" to be connected to the ON side.
Express. With such a configuration, the decoder 52 controls to select the corresponding cell according to the data input to the digital input terminal 51, and the current of the selected cell is output from the current output terminal 41. The numbers 1 to 31 also indicate the cell selection order when the input data is counted up from 1 to 31 in decimal.

For example, when the input data corresponding to the decimal number 9 is input to the D / A converter, the state of each control line is as shown in (Table 2), and the hatched line in FIG. The indicated cell is selected and its output is output from the current output terminal 41.

[0007]

[Table 2]

[0008]

By the way, xi, y
The signals of the j and zi control lines have a slight time difference in transmission time between the signals or between the cells due to factors such as the asymmetry of the wiring and the manufacturing process. As a result, when the input data is changed from data 1 to data 2, third data (data 3) may momentarily occur on the control line. This data 3 is data 1 and data 2
If the number is not between the two, a glitch may occur in the voltage of the output terminal 41 in some cases. This situation (Table 1)
Occurs when there are a plurality of cells changing from mode 2 to mode 3 or vice versa. That is, in order to maintain the "selected" state between the data 1 and the data 2, from the state where only the control signals xi and yj are applied (mode 3) to the state where only the control signal zi is applied (mode 2), or When there are a plurality of cells that transit from the state in which only the control signal zi is applied (mode 2) to the state in which only the control signals xi and yj are applied (mode 3), a glitch occurs unless the changes in each control signal are simultaneous. .. For example, when the input data changes from 8 to 9, and each control signal of yj changes faster than the control signals of xi and zi, the signal state shown in (Table 3) is obtained.

[0009]

[Table 3]

This state is the same signal state as when the input data is 1, and for cells 2 to 8, there is a transition from mode 3 to mode 2 in (Table 1). In this signal state, the current value corresponding to the output value necessarily appears at the output terminal 41. The change in the voltage of the output terminal 41 at this time is shown in FIG.
Shown in. Such glitches pose a serious problem for a D / A converter used for image signal processing.

An object of the present invention is to solve the above-mentioned conventional problems, and an object thereof is to provide a current addition type D / A converter which is free from glitches in continuous input data transitions.

[0012]

To achieve this object, a current summing D / A converter of the present invention comprises a constant current source and a switch for selectively connecting the constant current source to a common output terminal. A cell matrix in which a plurality of cells each having a logic circuit for driving the switch are arranged in a matrix of N rows and M columns, and a first control signal is commonly applied to each cell in each row. A plurality of first control line zi groups provided in each row, and a plurality of second control lines zi provided in each row for commonly applying a second control signal to each cell in each row. A group of control lines xi, and a group of a plurality of third control lines yj provided for each column in order to commonly apply a third control signal to the cells of each odd-numbered row of each column , A third control signal commonly applied to each cell of each row of each even-numbered column A group of a plurality of fourth control lines “yj” provided for each column for applying the fourth control signal of the phase, and the first, second, and second groups according to the data value of the input digital signal. It is composed of a decoder for selectively applying the control signals to predetermined control lines in the third and fourth control line groups.

[0013]

This structure eliminates the cell that causes the transition between the mode 2 and the mode 3 in (Table 1) as when the input data shown in (Table 2) changes from 8 to 9, so that the input As long as the data changes continuously, the glitch of the above problem will not occur.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a current addition type 5-bit D / A converter according to the present invention. In FIG. 1, 1 to 31 are 31 cells arranged in a matrix, 52 is a decoder, 61 and 62 are latch circuits, 63 is a clock input terminal (CLK), 51 is a digital input terminal, and 72 is each cell. Bias circuit for setting current value of constant current source, 71 is reference input terminal for bias setting, 41 is D
It is a current output terminal of the / A converter. Usually, a resistor 42 is connected to the current output terminal 41, and the other end of the resistor 42 is grounded. The number in each cell indicates the order of cells to be selected when the input data is counted up from 1 to 31 in decimal. Further, cells 21 and 28 are shown in FIG. Each cell is composed of a constant current source, a switch, and some logic circuits.

The control lines connected to the logic circuit of each cell are z1 to z1 provided in each row in order to apply the first control signal commonly to the cells in each row of the cell matrix.
a first control line zi group of z4, a second control line xi group of x1 to x4 provided for each row for commonly applying a second control signal to each cell of each row, and Third control line yj group of y1 to y8 provided for each column for commonly applying the third control signal to each cell of each odd-numbered row of each column, and an even number of each column A fourth control line of "y1" to "y8" provided for each column for applying a fourth control signal having a phase opposite to that of the third control signal to each cell in each row It is composed of a "yj" group.

When the second and third control signals are applied together through the second and third control lines, the logic circuit of the cell receives the second and fourth control lines through the second and fourth control lines. It is configured to close the switch of the cell when four control signals are applied together or when the first control signal is applied through the first control line.

That is, the y control of each cell 1 to 8.17 to 24 in the odd-numbered row of the cell matrix is performed by the control lines y1 to y.
8 allows y of cells 9 to 16.25 to 31 in even rows.
The control is configured to be controlled by the control lines "y1" to "y8", respectively.

Further, according to the data value of the input digital signal, each control signal is selectively applied to a predetermined control line in each of the first, second, third and fourth control line groups. The decoder 52 generates a control signal for each control line group so as not to cause a transition between mode 2 and mode 3 in (Table 1) when the data value of the input digital signal continuously changes. Is configured to.

The current addition type D / A configured as described above.
In the converter, the state of each control line for all input data is shown in (Table 4).

[0020]

[Table 4]

As shown in (Table 4), there is no cell that causes a transition between mode 2 and mode 3 in (Table 1) when the input data continuously changes. As described above, as long as the input data continuously changes, the glitch can be eliminated, which is an excellent effect.

[0022]

As is apparent from the above description, according to the present invention, when the input data changes by one, the decoder that eliminates the cells that cause the transition between the modes 2 and 3 in (Table 1). With the configuration, it is possible to provide a glitch-free D / A converter as long as the input data continuously changes.

[Brief description of drawings]

FIG. 1 is a block diagram of a current addition type D / A converter according to an embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing a structure inside a cell in the embodiment.

FIG. 3 is a block diagram of a current addition type D / A converter in a conventional example.

FIG. 4 is an electric circuit diagram showing a structure inside a cell in the conventional example.

FIG. 5 is a diagram showing a response characteristic of output voltage when input data changes from 8 to 9 in the conventional example.

[Explanation of symbols]

 1-31 31 cells arranged in a matrix 41 current output terminal 42 current-voltage conversion resistor 51 digital data input terminal 52 decoder circuit 61, 62 latch circuit 63 clock input terminal 71 reference voltage input terminal 72 bias setting circuit

Claims (1)

[Claims] 1. N rows of a plurality of cells each having a constant current source, a switch for selectively connecting the constant current source to a common output terminal, and a logic circuit for driving the switch,
A cell matrix arranged in a matrix of M columns, and a plurality of first control line zi groups provided in each row for applying a first control signal commonly to each cell in each row, A plurality of second control line xi groups provided for each row for commonly applying a second control signal to each cell for each row, and an odd-numbered cell for each row in each column A group of a plurality of third control lines yj provided for each column to commonly apply a third control signal, and an even-numbered third cell for each row in each column. Group of a plurality of fourth control lines “yj” provided for each column for applying a fourth control signal having a phase opposite to that of the first control signal and the first digital signal according to the data value of the input digital signal. ,second,
And a decoder for selectively applying the control signals to a predetermined control line in each of the third and fourth control line groups, and the logic circuit of each cell includes the second and third control lines. When both second and third control signals are applied through a line, when both second and fourth control signals are applied through the second and fourth control lines, or through the first control line The decoder is configured to close the switch of the cell when a first control signal is applied, and the decoder controls the control signal of each control line group when the data value of the input digital signal continuously changes. Is configured not to generate a code that causes a glitch, and a current having a value corresponding to the data value of the input digital signal is obtained at the output terminal.