JPH09307445A - Digital-to-analog converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a D/A converter which has high accuracy and generates no glitch noises. SOLUTION: In this converter, the current source cells C1 to C16 are arranged in a matrix form in both row and column directions. The cells C1 to C16 are selected in response to the signals of control signal lines A, B, C, X and Y which are set based on the digital signals. Then the current of the selected current source cell is supplied to a common resistance, so that the analog signal generated at the common resistance is outputted. The signal of the line X changes earlier than the signals of lines A, B and C, and the signal of the line Y changes later than the signals of lines A, B and C respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current output type digital-analog converter (hereinafter, simply referred to as a D / A converter).

High-speed D / A converters of recent years are required to have high precision. Therefore, it is necessary to shift to the matrix cell system (composite switch) rather than the segment system (single switch).

[0003]

2. Description of the Related Art In a conventional matrix cell type D / A converter, as shown in FIG. 6, a plurality of current source cells 11 are arranged in a matrix in a row direction and a column direction, and each current source cell 1
1 is connected to a common resistor (not shown).

Each current source cell 11 is provided with a constant current source 12 connected to a power source V _CC , a switch 13, and a selection circuit 14 for controlling ON / OFF of the switch 13. Selection circuit 1
4 includes an AND circuit 15 and an OR circuit 16. AND
Two input terminals of the circuit 15 are connected to a control signal line B extending in the row direction and a control signal line X extending in the column direction.
The two input terminals of the OR circuit 16 are connected to the control signal line A extending in the row direction and also connected to the output terminal of the AND circuit 15.

Whether the signal on the control signal line A is at H level,
When both the signal of the control signal line B and the signal of the control signal line X are H level, the output signal of the OR circuit 16 becomes H level. At this time, the switch 13 is turned on and the constant current source 1
A current of 2 flows through the resistor and an analog signal is output based on the voltage drop across the resistor.

The signals on the control signal lines A, B and X are signals that can be switched based on a digital code. As shown in FIG. 7, the signals on the control signal lines A, B and X can be switched simultaneously. ing.

[0007]

However, in the conventional matrix cell type D / A converter, the signals on the control signal lines A, B, and X in each current source cell 11 are delayed by a signal delay due to the wiring resistance or the like. Changes in the two cannot occur at the same time. Therefore, as shown in FIG. 8A, the state in which the seven current source cells 11 are selected based on the digital value “0111” is changed to the digital value “1101” as shown in FIG. 8C. When 13 current source cells 11 are selected based on this, in the process, the selected state of the current source cells shown in FIG. 8B or 8D occurs. FIG.
In (b), the signal of the control signal line A is switched after the signal of the control signal line B or X is switched, and 2
The two selected current source cells are deselected. After that, as shown in FIG. 8C, eight current source cells are newly selected, and as a result, thirteen current source cells are selected. That is, when the number of selected current source cells changes from 7 to 13, the selected number of current source cells becomes 5 as shown in FIG. 8B, which is less than the initial selected number of 7, Glitch noise occurs.

FIG. 8D shows the case where the signal on the control signal line B or X is switched after the signal on the control signal line A is switched, and eight current source cells are newly selected.
After that, as shown in FIG. 8C, the two selected current source cells are deselected, and as a result, 13 current source cells are selected. That is, when the number of selected current source cells changes from 13 to 7, the selected number of current source cells becomes 15 as shown in FIG. 8D, which exceeds the final selected number of 13. Glitch noise occurs.

Further, as shown in FIG. 9A, from the state where 13 current source cells 11 are selected based on the digital value "1101", as shown in FIG. 9C, the digital value " When the seven current source cells 11 are selected based on "0111", the selected state of the current source cells shown in FIG. 9B or 9D occurs in the process. FIG.
In (b), the signal on the control signal line A is switched after the signal on the control signal line B or X is switched.
The two selected current source cells are deselected. Thereafter, as shown in FIG. 9C, two new current source cells are newly selected, and as a result, seven current source cells are selected.
That is, when the number of selected current source cells changes from 13 to 7, as shown in FIG. 9B, the number of selected current source cells becomes 5, which is less than the final selected number of 7.
Glitch noise occurs.

FIG. 9D shows the case where the signal on the control signal line A is switched after the signal on the control signal line A is switched, and two current source cells are newly selected.
After this, as shown in FIG. 9C, the eight selected current source cells are deselected, and as a result, seven current source cells are selected. That is, the number of selected current source cells is 1
When the number of current source cells is changed from 3 to 7, as shown in FIG. 9D, the selected number of current source cells is 15, which exceeds the initial selected number of 15. Therefore, glitch noise occurs.

The present invention has been made to solve the above problems, and an object thereof is to provide a highly accurate digital-analog converter that does not generate glitch noise.

[0012]

To achieve the above object, the digital-analog converter of the present invention comprises first to third control signals for controlling a current source cell in a first direction, A fourth and a fifth control signal for controlling the current source cell in the second direction, wherein the fourth control signal is changed before the change of the first to third control signals,
The control signal is changed after the change of the first to third control signals.

(Operation) Therefore, in the process of changing the selected current source cell, the number of selected current source cells does not exceed the range from the initial number to the final number, so that the occurrence of glitch noise is prevented. Therefore, the accuracy of D / A conversion is improved.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a matrix cell type D / A converter 20 of the present embodiment. In addition, D of this embodiment
The A / A converter 20 will be described as one that converts a 4-bit digital code into an analog signal.

The D / A converter 20 includes 16 current source cells C.
Four of the current source cells C1 to C16 are arranged in a matrix in the row direction which is the first direction and the column direction which is the second direction, and the current source cells C1 to C16 are connected to the ground G via the common resistor R1.
Connected to ND. An output terminal Vout is connected between the resistor R1 and the current source cell, and the output terminal Vout outputs an analog signal VA based on the voltage drop at the resistor R1.

Each of the current source cells C1 to C16 has a constant current source 21 connected to a power source V _CC , a switch 22, and a switch 2.
A selection circuit 23 for controlling ON / OFF of 2 is provided. The selection circuit 23 includes a buffer 24, two AND circuits 25, 2
6 and an OR circuit 27.

The input terminal of the buffer 24 is connected to the signal on the first control signal line A extending in the row direction, and the buffer 24 outputs a signal in phase with the signal on the first control signal line A. A
Two input terminals of the ND circuit 25 are connected to a second control signal line B extending in the row direction and a fourth control signal line X extending in the column direction. The two input terminals of the AND circuit 26 have a third control signal line C extending in the row direction and a fifth control signal line C extending in the column direction.
Of the control signal line Y. OR circuit 27-3
One input terminal is connected to the output terminal of the buffer 24, the output terminal of the AND circuit 25, and the output terminal of the AND circuit 26.

Therefore, when the signal on the control signal line A is at the H level, or when the signals on the control signal line B and the control signal line X are both at the H level, or the control signal line C
When both the signal of 1) and the signal of the control signal line Y are at H level, the output signal of the OR circuit 27 becomes at H level. That is, the signal on the control signal line B is the first designation signal for designating the current source cell in the row direction and for selecting the predetermined current source cell together with the signal on the control signal line X. The signal on the control signal line C is a second designation signal for designating a current source cell in the row direction and for selecting a predetermined current source cell together with the signal on the control signal line Y. At this time, switch 2
2 is turned on, the current of the constant current source 21 flows through the resistor R1, and the analog signal VA is output based on the voltage drop at the resistor R1.

The signals on the control signal lines A, B, C, X and Y are
The signal is a signal that is switched by a control circuit (not shown) based on the code of the digital signal, and the control signal lines A, B,
The C, X, Y signals are switched based on a predetermined priority.

In this embodiment, as shown in FIG. 3, the level (H or L) of the signal on the control signal line X is changed based on the new digital code.
Is switched to. Next, the signal on the control signal line B is switched from the L level to the level (H or L) for changing the analog signal. Then, the signal on the control signal line A is switched to the level (H or L) for changing the analog signal. After that, the signal of the control signal line C is switched from the level (H or L) for changing the analog signal to the L level. Next, the signal on the control signal line Y is switched to the level (H or L) for changing the analog signal. After that, the signal of the control signal line C is switched from the L level to the level (H or L) for changing the analog signal. Finally, the signal on the control signal line B is switched from the level (H or L) for changing the analog signal to the L level.

Next, the operation of the D / A converter 20 configured as described above will be described with reference to FIGS. FIG. 4 shows seven current source cells C1 to C based on the digital value "0111".
The case where 13 current source cells C1 to C13 are selected based on the digital value “1101” from the state where 7 is selected is shown. As shown in FIG. 4A, the digital value “011
1 ”in response to the signal on the control signal line A, the four current source cells C1 to C4 are selected and the control signal line C is selected.
Of the three current source cells C5 to C7 are selected based on the signal of the control signal line Y and the signal of the control signal line Y.
1 to C7 are selected. First, when the signal on the control signal line X changes to the level for changing the analog signal, the signal on the control signal line B is at the L level. Therefore, there is no change in the current source cell selected based on the change in the signal on the control signal line X.

Next, the signal on the control signal line B changes to a level for changing the analog signal. At this time, since the signal of the control signal line X has already changed, the current source cell C13 is newly selected as shown in FIG.

Subsequently, when the signal on the control signal line A is switched to the level for changing the analog signal, the signal shown in FIG.
As shown in (c), the current source cells C1 to C4, C5 to C
8, C9 to C12 are selected, and 13 current source cells are selected at this point.

After this, the signal on the control signal line C is switched to the L level, but since the current source cells C5 to C7 have already been selected based on the signal on the control signal line A, the signal on the control signal line C is changed. Based on the change to the L level, the current source cell C
5 to C7 are never deselected.

Next, the signal on the control signal line Y changes to a level for changing the analog signal.
Signal is at L level. Therefore, there is no change in the current source cell selected based on the change in the signal on the control signal line Y.

After that, the signal on the control signal line C changes from the L level to the level for changing the analog signal.
At this time, since the signal on the control signal line Y has already changed, the current source cell C13 is reselected. Finally, the signal of the control signal line B is switched to the L level, but since the current source cell C13 has already been selected based on the signal of the control signal line C and the signal of the control signal line Y, the current source cell C13 is not No selection is made, and as a result, 13 current source cells are selected as shown in FIG.

In FIG. 5, seven current source cells C1 to C7 are selected based on the digital value "0111" from the state where 13 current source cells C1 to C13 are selected based on the digital value "1101". Indicate the case. As shown in FIG. 5A, the current source cells C1 to C4, C5 to C8, C are responsive to the signal on the control signal line A based on the digital value "1101".
9 to C12 are selected, and one current source cell C is selected based on the signal of the control signal line C and the signal of the control signal line Y.
13 is selected, and 13 current source cells C1 to C1 are selected.
3 is selected.

First, when the signal on the control signal line X changes to the level for changing the analog signal, the signal on the control signal line B is at the L level. Therefore, the control signal line X
There is no change in the current source cell selected on the basis of the change in the signal of.

Next, although the signal on the control signal line B changes to a level for changing the analog signal, the current source cell C
5 to C7 are already selected based on the signal on the control signal line A, the current source cell C5 is selected as shown in FIG.
Since ~ C7 is double-selected with the control signal line A, there is no change.

Next, when the signal on the control signal line A is switched to the level for changing the analog signal, the signal shown in FIG.
As shown in (c), the current source cells C8 and C9 to C12 are deselected.

Next, when the signal on the control signal line C is switched to the L level, the current source cell C13 becomes non-selected as shown in FIG. 5 (d). Next, the signal on the control signal line Y changes to a level for changing the analog signal, but the signal on the control signal line C is at the L level. Therefore, there is no change in the current source cell selected based on the change in the signal on the control signal line Y.

Thereafter, the signal on the control signal line C changes from the L level to the level for changing the analog signal.
At this time, since the portion selected based on the signals of the control signal lines C and Y has already been selected, there is no change in the selected current source cell. Finally, the signal on the control signal line B is switched to the L level, but there is no change in the selected current source cell, and as a result, as shown in FIG. 5D, seven current source cells are selected. .

The present embodiment has the following effects. (1) The control signal lines A, B, C in the row direction and the control signal lines X, Y in the column direction are provided, and the signal of the control signal line X is changed before the signals of the control signal lines A, B, C are changed. Change the control signal line Y
Signal of control signal line A, B, C is changed after each one change. Further, the signals of the control signal lines A, B, and C in the row direction are changed in the order of the signal of the control signal line B, the signal of the control signal line A, and the signal of the control signal line C. Therefore, in the process of changing the selected current source cell, the number of selected current source cells does not exceed the range from the initial number to the final number, and it is possible to prevent the occurrence of glitch noise and to reduce D / The accuracy of A conversion can be improved.

The present invention can be embodied by being arbitrarily modified as follows. (1) The control signal lines A, B, and C may be signal lines in the column direction, and the control signal lines X and Y may be signal lines in the row direction.

[0035]

As described above in detail, the present invention can provide a highly accurate digital-analog converter that does not generate glitch noise.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a matrix cell type D / A converter of the present embodiment.

FIG. 2 is a circuit diagram showing the current source cell of FIG.

FIG. 3 is a time chart of control signals

FIG. 4 is an explanatory diagram showing the operation of the present embodiment.

FIG. 5 is an explanatory diagram showing the operation of the present embodiment.

FIG. 6 is a circuit diagram showing a conventional current source cell.

7 is a time chart of control signals in FIG.

FIG. 8 is an explanatory diagram showing an operation of a conventional example.

FIG. 9 is an explanatory diagram showing an operation of a conventional example.

[Explanation of symbols]

 A first control signal line B second control signal line C third control signal line C1 to C16 current source cell X fourth control signal line Y fifth control signal line VA analog signal

Claims (4)

[Claims] 1. A plurality of current source cells are arranged in a matrix in a first direction and a second direction orthogonal to the first direction, and the plurality of current source cells are arranged in a first direction based on a digital signal. A digital signal which is selected in response to a direction control signal and a second direction control signal, and which supplies the current of the selected current source cell to a common resistor to output an analog signal generated in the resistor. -In the analog converter, first to third control signals for controlling the current source cell in the first direction, and fourth and fifth control signals for controlling the current source cell in the second direction. A control signal, the fourth control signal is changed before the change of the first to third control signals, and the fifth control signal is changed after the change of the first to third control signals. Digital-to-analog converter. 2. The digital-analog converter according to claim 1, wherein the first to third control signals are changed at different times based on a predetermined priority order. 3. The first control signal is a selection signal for selecting all current source cells in the first direction, and the second control signal specifies a current source cell in the first direction. And a first designation signal for selecting a predetermined current source cell together with the fourth control signal, wherein the third control signal designates the current source cell in the first direction and a fifth control signal. The digital-analog converter according to claim 1 or 2, which is a second designation signal for selecting a predetermined current source cell. 4. The digital-analog converter according to claim 1, wherein a period in which the third control signal is invalid is included in a period in which the second control signal is valid. .