JPH0226416A - A/d converting circuit - Google Patents

Abstract

PURPOSE:To obtain a high-speed A/D converting circuit whose structure is simplified by determining more significant bits and after that, determining less significant bits based on the result. CONSTITUTION:The title circuit consists of a first resistance group 14, a first comparing circuit group 17, a first encoder 20, a first register 21, a subtracting circuit 22, a switch group 23, a second resistance group 25, a second comparing circuit group 28, a second encoder 30, a second register 31 and a selecting circuit 32. The more significant bits are determined, after that, a reference voltage is selected in accordance with the result, an input signal is subtracted from the reference voltage, the less significant bits are obtained from the result of the subtraction and therefore, the number of bits to be processed by a circuit to make an A/D conversion can be made into about 1/2 of the total number of bits. Thus, the high-speed A/D converting circuit can be obtained with the simple structure.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to an A/D (analog/digital) conversion circuit for converting an analog input signal to a digital signal. Regarding the A/D conversion circuit used for measurement.

(B) Conventional technology Various A/D conversion circuits for converting analog signals into digital signals have been proposed in the past, and are selectively used depending on the application. As the A/D conversion circuit, an integral type A/D conversion circuit is mainly used, and this is applied to digital multimeters, electronic scales, and the like. Further, as a medium-speed A/D conversion circuit whose conversion time is from several μs to several hundred μs, a successive approximation type A/D conversion circuit is used, and this is applied to PCM communications, digital audio, and the like. Further, as a high-speed A/D conversion circuit with a conversion time of several hundred ns or less, a parallel comparison type A/D conversion circuit is used and is applied in the fields of video signal processing and measurement. Regarding A/D conversion circuits, please refer to 1 Illustrated A/D dated July 30, 1985.
This is explained in detail in ``Introduction to D Converter''.

By the way, the high-speed parallel comparison A/D conversion circuit is
When high-order bits are used, the circuit becomes complicated, and when integrated into an IC, the chip area increases and current consumption increases. Figure 2 shows the 4-bit A/
This shows a D conversion circuit, with 16 resistors (2a> to (2p)) connected in series between the i source terminal (1) and the ground.
One input terminal is connected to each connection point of the resistors (2a) to (2p), and the other input terminal is connected to the signal input terminal (
3) 15 comparison circuits (4a) to (4o
) and an encoder (5) that encodes the output signals of the comparison circuits (4a) to (4o). As is clear from Figure 2, in the case of the parallel comparison method,
Even when configuring a 4-bit A/D conversion circuit, 16 resistors and 15 comparison circuits are required. Generally, when configuring an n-bit A/D conversion circuit, 2 resistors and 15 comparison circuits are required. 2°-1 circuits are required.

A series-parallel comparison type A/D conversion circuit has been proposed as an improvement on the parallel comparison type A/D conversion circuit to reduce the number of elements. In the case of 4 bits, this A/D conversion circuit consists of 16 resistors (7a) to (7p) connected in series between the power supply terminal (6) and the ground, as shown in Figure 3.
and three upper bit comparison circuits (9a), one input terminal of which is connected to a predetermined connection point of the resistors (7a) to (7p), and the other input terminal of which is connected to the signal input terminal (8).
) to (9c) and the comparison circuits (9a) to (9C)
a first encoder that encodes the output signal of the encoder and generates an output signal of the upper 2 bits;
The first to fourth switch groups (11a) to (lid) connected to predetermined connection points of (7p) and the signal input terminal (
8), three lower bit comparison circuits (12a) to (12a) to (8) compare the input signals that can be applied to the reference voltages obtained from the first to fourth switch groups (lla) to (lid);
12c) and the comparison circuits (12a) to (12c
) and a second encoder (13) that encodes the output signal of the encoder and generates an output signal of the lower two bits. In the case of the A/D conversion circuit shown in Fig. 3, first to fourth
All the switches constituting the switch groups (lla) to (lid) are fully open, and A/D conversion of the upper two bits is performed. That is, the first to third comparison circuits (9a) to (9
C), the reference voltage and the input voltage are compared, and rH or "L" output signals are generated at the output terminals of the first to third comparison circuits (9a) to (9C). Said first
The output signals of the third comparison circuits (9a) to (9C) are as follows:
The signal is applied to the first enhancer (10) to be enhooded. Therefore, at the output end of the first encoder (10),
An output signal is generated representing the upper two bits of the digital signal. The output signal of the first encoder (10) is 0,0, depending on the level of the input signal.

(0,1), (1,0), (1,1).

The comparison circuits (9a) to (9c) and the first enhancer (10
), when A/D conversion of the upper 2 bits is performed,
According to the output signal of the first encoder (10), the first
One of the fourth switch groups (lla) to (lid) is selected, and the switches constituting the selected switch group are closed. For example, when the output signal of the first encoder (10) is (0, 0), the fourth switch group (lid) is selected, and similarly, when the output signal is (0, 1), the third switch group (lld) is selected.
c) is (1,0), the second switch group (llb)
is (1, 1), the first switch group (lla) is selected. 1st to 4th switch group (lla)
When one of (lid) to (lid) is selected, the reference voltage corresponding to the selected switch group is applied to the lower bit comparison circuit (12
a) to (12c) and compared with the input signal. Therefore, an output signal rH or rL is generated at the output terminals of the comparison circuits (12a) to (12c), and the output signal is encoded by the second encoder (13). As a result, an output signal of the lower two bits is generated from the second enhancer (13).

If you use the A/D conversion circuit shown in Figure 3, you can convert analog content into 4
It can be converted into a bit digital signal. At that time, the number of comparison circuits is only 6, so even though the encoder and the first to fourth switch groups are increased compared to the circuit in Figure 2, the overall circuit can be simplified. . In particular, when the number of bits increases (for example, in the case of 8 bits, the circuit in Figure 2 requires 255 comparators, but the circuit in Figure 3 requires only 30). A significant decrease can be measured.

(c) Problems to be Solved by the Invention However, even in the A/D conversion circuit shown in FIG. 3, when obtaining a digital signal of high-order bits, the number of elements becomes extremely large, which poses a problem. For example, if the A/D conversion circuit is
When configured with 6 bits, 510 comparison circuits and 65536 resistors are required. Therefore, an A/D conversion circuit with a further simplified configuration has been desired.

(d) Means for Solving the Problems The present invention has been made in view of the above points, and includes a first A/D converter that generates a digital signal of upper bits corresponding to the level of an analog input signal. , a reference voltage generation circuit that selectively generates one of a plurality of reference voltages according to the output signal of the A/D converter, and a reference voltage generation circuit that outputs the reference voltage of the reference voltage generation circuit and the analog input signal. It is characterized by comprising an arithmetic circuit that performs arithmetic operations, and a second A/D converter to which an output signal of the arithmetic circuit is applied and generates a digital signal of lower bits corresponding to the level of the analog input signal. .

(*) Effect According to the present invention, the first reference voltage generated from the first resistor group and the analog input signal are compared, and the digital signal corresponding to the upper bit generated from the first encoder is transferred to the first register. is stored in Then, a selection circuit closes one switch of the switch group in response to the digital signal stored in the first register. Then, a first reference pressure is generated in response to this, and an arithmetic operation is performed between the first reference voltage and the analog input signal in an arithmetic circuit. Then, in the second comparing circuit group, the output signal of the arithmetic circuit is compared with the second reference voltage generated from the second resistor group, and the digital signal corresponding to the lower bit generated from the second encoder is compared with the second reference voltage generated from the second resistor group. Can be stored in register.

(f) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, (14)
are first reference voltage generation resistors (16a) to (16) connected in series between the first reference power supply terminal (15) and the ground.
d), the first resistor group (17) is the resistor (16a
) to (16d) for generating an output signal of "H" or "L" by comparing the first reference voltage obtained at each connection point with the input analog signal applied to the input terminal (18). The first comparator circuit consists of third comparator circuits (1, 9a) to (19c).
A comparison circuit group (20) is the first to third comparison circuits (1
a first encoder (21) that encodes the output signals of 9a) to (19c) and generates a 2-bit digital signal;
) is a first register that stores the upper two bits of the digital signal obtained from the first encoder (20), and (22) is a first reference voltage obtained at each connection point of the resistors (16a) to (16d). A subtraction circuit (23) that performs subtraction with the input analog signal is connected to the resistors (16a) to (16).
d) first to fourth switches (24g) that apply the first reference voltage generated at each connection point to the subtraction circuit (22);
(25) is a second switch group consisting of resistors (27a) to (27d) for generating a second reference voltage connected in series between the second reference power supply terminal (26) and the ground. The resistor group (28) compares the second reference voltage obtained at each connection point of the resistors (27a) to (27d) with the output signal of the subtraction circuit (22), and calculates rH or r
The fourth to sixth comparison circuits (29
A second comparison circuit group consisting of a) to (29c), (30)
are the fourth to sixth comparison circuits (29a) to (29c
), a second encoder (31) encodes the output signal of the second encoder (30) and generates a 2-bit digital signal; (31) a second register that stores the lower two bits of the digital signal obtained from the second encoder (30); ) is a selection circuit that selectively drives the first to fourth switches (24a) to (24d) in accordance with the control signal generated from the first register (21).

FIG. 1 is a circuit diagram for converting an input analog signal into a digital signal of a total of 4 bits, ie, the upper 2 bits and the lower 2 bits. In this case, if the first reference voltage applied to the first reference power supply terminal (15) is Vref, the second reference voltage applied to the second reference power supply terminal (26) is Vref/N
(However, it needs to be N-2", where n is the number of upper bits. Therefore, in the embodiment shown in FIG. 1,
For the upper and lower bits each, the second reference voltage is set to V.
It is set to ref/4.

Further, the first and second enhancers (20) and (30)
are the first comparison circuit group (17) and the second comparison circuit group (28).
) to convert the 3-bit digital signal obtained from It becomes a signal. Further, the selection circuit (32) has a first register (2).
1) Generates 4-bit digital signals (A to D) for switching the first to fourth switches (24a) to (24d) in accordance with the 2-bit control signal from Thus, the selection circuit (32) generates a 4-bit digital signal in response to the output of the 2-bit first register (21).

Next, the A/D conversion operation will be explained. Input terminal (1
The input analog signal Via from 8) is applied to the first to third comparison circuits (19a) to (19c), and the three first reference voltages (V+, V
z, Vs). At that time, the input analog signal V
The first to third comparison circuits (19a) depending on the level of im.
An output signal of ``rH'' or ``rL'' is generated at the output terminals of (19c) and is encoded by the first encoder (20), so that a 2-bit digital signal is generated at the output terminal of the first encoder (20). Occur. The first encoder (20
) is stored in the first register (21), and the upper two bits of the digital signal are generated at the first and second output terminals (33) and (34>), and the control signal is sent to the selection circuit (32>). Signal can be applied.

The control signals (0,0), (0,1), (1°0), (
1, 1), the selection circuit (32) generates signals A, B, C, and D for selecting one of the first to fourth switches (24a) to (24d). Therefore, the selected one of the first to fourth switches (24a) to (24d) is closed, and the corresponding first reference voltage is applied to the subtraction circuit (22) and subtracted from the input analog signal. Ru.

The output voltage Δ■ of the subtraction circuit (22) is applied to the fourth to sixth comparison circuits (29a) to (29c), and is applied to the three second reference voltages (V4, V4,
Vs, va). At that time, the fourth to sixth comparison circuits (29
Since an output signal of "rH" or "L" is generated at the output terminals of a) to (29c) and encoded by the second encoder (30), a 2-bit signal is generated at the output terminal of the second encoder (30). A digital signal is generated.

The output digital signal of the second encoder (30) is stored in the second register (31), and lower two bit digital signals are generated at the third and fourth output terminals (35) and (36).

Now, if an analog input signal having a level of V, <V, <V is applied as the input signal Vla,
By converting the upper 2 bits, the first register (2
A digital signal of (0, 1) is stored in 1). Then, a control signal is applied from the first register (21) to the selection circuit (32), and the selection circuit (32) generates a signal B for turning on only the second switch (24b). When the second switch (24b) is turned on, the input signal Vi
Subtraction is performed between m and the first reference voltage V, and the lower two bits are converted in accordance with the subtracted output ΔV (=V, , -Vl). The subtraction output Δ■ is v, <ΔV<
Assuming that the level is V*, the second register (31)
A digital signal of (1, 0) is stored in . Therefore, the first to fourth output terminals (33) to (36) receive 4-bit digital signals (0, 36) corresponding to the analog input signal level.
1, 1, O) occurs.

As is clear from FIG. 1, according to the present invention, the upper bit is determined and then the lower bit is determined based on the result. Therefore, when the upper bit and the lower bit are equal, the upper and lower bits are The number of bits of the A/D conversion circuit that determines each can be set to . Therefore, N bits of A
If the /D conversion circuit is configured as shown in Figure 1, the number of resistors is 2.
×2 N /* pieces, the number of comparison circuits is 2X (2””-1)
This can be significantly reduced compared to conventional methods. This becomes more effective when obtaining a digital signal with high-order bits. For example, in the case of 16 bits, Figure 1 Figure 2 Figure 3 Number of resistors 512 65.536 65.53
6 Number of comparison circuits 510 65.535 51
It becomes 0.

In the embodiment shown in FIG. 1, the case where the upper bits and lower bits have the same number of bits has been explained, but this does not necessarily have to be the same, and in the embodiment, the first criterion Since the reference voltage applied to the power supply terminal (15) was of positive polarity (+Vref), the subtraction circuit (22>) was used, but depending on the polarity of the reference voltage, the subtraction circuit (22) may operate as an addition circuit. However, this is essentially a subtraction operation.

(G) Effects of the Invention As described above, according to the present invention, a high-speed A/D conversion circuit can be provided with a simple configuration. In particular, in the present invention, after determining the upper bit, a reference voltage is selected according to the result, the reference voltage is subtracted from the input signal, and the lower bit is obtained from the subtraction result.
The number of bits processed by each A/P conversion circuit can be made approximately equal to the total number of bits. Therefore, the number of resistors and comparison circuits can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams showing a conventional A/D conversion circuit, and FIGS. 4 and 5 are circuit diagrams of a conventional A/D conversion circuit. FIG. 3 is a diagram showing an output digital signal obtained from an A/D conversion circuit. (14)...First resistance group, (15)...First reference tolerance terminal, (17)...First comparison circuit group, (20
)...first encoder, (21)...first register, (22)...subtraction circuit, (23)...switch group, (25)...second resistance group, (26)... ...
second reference power supply terminal, (28)... second comparison circuit group,
(30)...Second encoder, (31)...Second encoder
Register, (32)...Selection circuit.

Claims (4)

[Claims] (1) A first A/D converter that generates a high-order bit digital signal corresponding to the level of an analog input signal;
/D converter output signal according to one of a plurality of reference voltages.
a reference voltage generating circuit that selectively generates a reference voltage; an arithmetic circuit that performs an arithmetic operation on the output reference voltage of the reference voltage generating circuit and the analog input signal; and a second A/D converter that generates a lower bit digital signal corresponding to the level of the A/D converter. (2) A first resistance group consisting of a plurality of resistors connected in series between the first reference power source and the ground, and a first reference voltage and analog input obtained at the connection point of the plurality of resistors in the first resistance group. a first comparison circuit group for upper bits comprising a plurality of comparison circuits for comparing signals; a subtraction circuit for subtracting a first reference voltage generated in the first resistance group from the analog input signal; a group of switches that respectively apply a first reference voltage obtained at the connection point of a plurality of resistors of one resistor group to the subtracting circuit; and a second group of resistors that includes a plurality of resistors connected in series between a second reference power source and ground. a second comparison circuit group for lower bits comprising a resistor group and a plurality of comparison circuits that compare a second reference voltage obtained at a connection point of a plurality of resistors of the second resistance group and an output signal of the subtraction circuit; , first and second encoders that encode output signals of the first and second comparison circuit groups, respectively; first and second registers that store output signals of the first and second encoders, respectively; and a selection circuit that selects and drives one of the switch groups according to the output signal of the register, and transmits the high-order bit digital signal to the output terminal of the first register and the low-order bit digital signal to the output terminal of the second register. An A/D conversion circuit characterized by generating a signal. (3) The first reference voltage of the first reference power source is Vref, and the second reference voltage of the second reference power source is Vref/N(N
3. The A/D conversion circuit according to claim 2, wherein: =2^n, where n is the number of upper bits. (4) The number of bits of the upper bit digital signal generated at the output end of the first register is equal to the bit number of the lower bit digital signal generated at the output end of the second register. A/D according to claim 2
conversion circuit.