JPS60163870U - Video signal contour enhancement circuit - Google Patents
Video signal contour enhancement circuitInfo
- Publication number
- JPS60163870U JPS60163870U JP4966984U JP4966984U JPS60163870U JP S60163870 U JPS60163870 U JP S60163870U JP 4966984 U JP4966984 U JP 4966984U JP 4966984 U JP4966984 U JP 4966984U JP S60163870 U JPS60163870 U JP S60163870U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- contour enhancement
- enhancement circuit
- input video
- signal contour
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Picture Signal Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の垂直輪郭強調回路のブロック図、第２図
はテレビジョン信号のインクレース走査を説明する図、
第３図は被写体の撮像画面を示す図、第４図はその映像
信号の対応を説明する図、第５図は本考案の一実施例の
ブロック図である。
３１：フィールド遅延回路、３３ ： ＩＨ遅延回路、
３５，３９：加算器、３６：ゲイン変換器、３７：減算
器。FIG. 1 is a block diagram of a conventional vertical contour enhancement circuit, and FIG. 2 is a diagram illustrating incremental scanning of a television signal.
FIG. 3 is a diagram showing an image capturing screen of a subject, FIG. 4 is a diagram explaining the correspondence of video signals, and FIG. 5 is a block diagram of an embodiment of the present invention. 31: Field delay circuit, 33: IH delay circuit,
35, 39: adder, 36: gain converter, 37: subtracter.
Claims (1)
期間）遅延させた信号と１フイールド＋１／２Ｈ遅延さ
せた信号を得る手段と、上記２つの遅延信号を加算する
第１の演算手段と、上記入力映像信号と上記第１の演算
手段の出力信号を減算する第２の演算手段と、該第２の
演算手段の出力信号を上記入力映像信号に加算する第３
の演算手段を有することを特徴とする映像信号輪郭強調
回路。means for obtaining a signal obtained by delaying the input video signal by 1 field - 1/2H (H is a horizontal scanning period) and a signal obtained by delaying the input video signal by 1 field + 1/2H; and a first calculation means for adding the two delayed signals. , a second arithmetic means for subtracting the output signal of the first arithmetic means from the input video signal, and a third arithmetic means for adding the output signal of the second arithmetic means to the input video signal.
1. A video signal contour emphasizing circuit, characterized in that it has a calculation means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4966984U JPS60163870U (en) | 1984-04-06 | 1984-04-06 | Video signal contour enhancement circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4966984U JPS60163870U (en) | 1984-04-06 | 1984-04-06 | Video signal contour enhancement circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60163870U true JPS60163870U (en) | 1985-10-31 |
Family
ID=30567076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4966984U Pending JPS60163870U (en) | 1984-04-06 | 1984-04-06 | Video signal contour enhancement circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60163870U (en) |
-
1984
- 1984-04-06 JP JP4966984U patent/JPS60163870U/en active Pending
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